JPH0136362Y2 - - Google Patents
Info
- Publication number
- JPH0136362Y2 JPH0136362Y2 JP1984150788U JP15078884U JPH0136362Y2 JP H0136362 Y2 JPH0136362 Y2 JP H0136362Y2 JP 1984150788 U JP1984150788 U JP 1984150788U JP 15078884 U JP15078884 U JP 15078884U JP H0136362 Y2 JPH0136362 Y2 JP H0136362Y2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- converter
- circuit
- amplifier
- potential point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Measurement Of Current Or Voltage (AREA)
- Analogue/Digital Conversion (AREA)
Description
【考案の詳細な説明】
「産業上の利用分野」
この考案は電圧又は電流測定器等に利用するこ
とができるAD変換装置に関する。[Detailed Description of the Invention] "Industrial Application Field" This invention relates to an AD conversion device that can be used in voltage or current measuring instruments, etc.
「従来技術」
第3図に従来のAD変換装置を示す。この例で
はICテスタの直流動作試験に用いる電圧、電流
測定用AD変換装置の場合を例示して示す。``Prior Art'' Figure 3 shows a conventional AD converter. In this example, a case of an AD converter for measuring voltage and current used in a DC operation test of an IC tester will be illustrated.
図中100はパフオーマンスボードを示す。こ
のパフオーマンスボード100に被試験IC10
1が装着され、この被試験IC101の直流特性
を試験する状態を示す。 In the figure, 100 indicates a performance board. This performance board 100 has 10 ICs under test.
1 is attached and the DC characteristics of this IC 101 under test are tested.
ICの直流特性試験は大別すると電流印加電圧
測定モードと、電圧印加電流測定モードとがあ
る。 IC DC characteristic tests can be roughly divided into a current applied voltage measurement mode and a voltage applied current measurement mode.
電流印加電圧測定モードは被試験ICの端子間
(一方の端子はコモン端子の場合が多い)に電流
源を接続し、端子間に所定の電流を流したときそ
の端子間に予定した電圧が発生するか否かを試験
する試験モードを指す。 In current applied voltage measurement mode, a current source is connected between the terminals of the IC under test (one terminal is often a common terminal), and when a specified current is passed between the terminals, a planned voltage is generated between the terminals. Refers to the test mode that tests whether or not the
また電圧印加電流測定モードは被試験ICの端
子間に所定の電圧を印加した状態でICに流入す
る電流値が予定した値となつているか否かを判定
する試験モードを指す。 Further, the voltage application current measurement mode refers to a test mode in which it is determined whether the current value flowing into the IC is a predetermined value while a predetermined voltage is applied between the terminals of the IC under test.
図の例では電圧印加電流測定モードの接続状態
を示す。つまり第3図において200はDA変換
部、300は被試験IC101に所定の電圧を印
加する電圧発生回路、400は電圧発生回路30
0から被試験IC101に流入する電流値をAD変
換するためのAD変換部を示す。 The example shown in the figure shows the connection state in voltage application current measurement mode. In other words, in FIG. 3, 200 is a DA converter, 300 is a voltage generation circuit that applies a predetermined voltage to the IC under test 101, and 400 is the voltage generation circuit 30.
2 shows an AD converter for AD converting the current value flowing from 0 to the IC under test 101.
DA変換部200は制御器500から与えられ
るデイジタル信号を変換し、そのDA変換出力を
電圧発生回路300に与える。電圧発生回路30
0は増幅器301と、この増幅器301の帰還回
路に接続したバツフア増幅器302と、共通電位
点CMの電位を決めるバツフア増幅器303と、
増幅器301から流出する電流値を検出する電流
検出用抵抗器304とによつて構成される。 The DA conversion section 200 converts the digital signal given from the controller 500 and gives the DA conversion output to the voltage generation circuit 300. Voltage generation circuit 30
0 is an amplifier 301, a buffer amplifier 302 connected to the feedback circuit of this amplifier 301, a buffer amplifier 303 that determines the potential of the common potential point CM,
A current detection resistor 304 detects the current value flowing out from the amplifier 301.
増幅器301は電流検出用抵抗器304を介し
て端子T1とT2間に所定の電圧を印加する。端子
T1とT2に印加された電圧はケーブル600を通
じてパフオーマンスボード100に与えられる。
バツフア増幅器302は端子T2とT3の間に発生
した電圧を高インピーダンスで取り出して増幅器
301の反転入力端子に帰還し、増幅器301が
DA変換部200から与えられた電圧と対応した
電圧を正確に出力するように動作する。端子T4
は電源Eの共通電位点ECMに接続されて増幅器
301の出力電流の帰路を構成する。 Amplifier 301 applies a predetermined voltage between terminals T 1 and T 2 via current detection resistor 304 . terminal
The voltages applied to T 1 and T 2 are applied to the performance board 100 through the cable 600.
Buffer amplifier 302 extracts the voltage generated between terminals T 2 and T 3 at high impedance and returns it to the inverting input terminal of amplifier 301.
It operates to accurately output a voltage corresponding to the voltage given from the DA converter 200. Terminal T 4
is connected to the common potential point ECM of the power source E and forms a return path for the output current of the amplifier 301.
この回路において回路網の共通電位点CMの電
位は被試験IC101の一方の端子PCMと等しい
電位に保持しなければならない。ケーブル600
は比較的長くなるためそこにはわずかな線路抵抗
が存在する。このためにバツフア増幅器303に
よつて高インピーダンスで端子PCMの電位を取
り込み、ケーブルの直流抵抗に影響されることな
く回路網の共通電位点CMの電位を端子PCMの
電位と等しくなるように制御している。このよう
なバツフア増幅器は電圧発生回路300のほかに
DA変換部200及びAD変換部400にもバツ
フア増幅器201及び401として設けられてい
る。 In this circuit, the potential of the common potential point CM of the circuit network must be held at the same potential as one terminal PCM of the IC 101 under test. cable 600
Since the line is relatively long, there is a slight line resistance there. For this purpose, the buffer amplifier 303 takes in the potential of the terminal PCM at high impedance, and controls the potential of the common potential point CM of the circuit network to be equal to the potential of the terminal PCM without being affected by the DC resistance of the cable. ing. Such a buffer amplifier includes, in addition to the voltage generation circuit 300,
Buffer amplifiers 201 and 401 are also provided in the DA converter 200 and the AD converter 400.
電圧発生回路300において電流検出用抵抗器
304に発生する電圧を差動増幅器305によつ
て取出してその電圧をAD変換部400に与え
る。 The voltage generated across the current detection resistor 304 in the voltage generation circuit 300 is extracted by the differential amplifier 305 and applied to the AD conversion section 400 .
AD変換部400は入力切換スイツチ402,
403とバツフア増幅器404,405及びAD
変換器406と、オフセツトデータ取込用レジス
タ407と測定データ取込用レジスタ408と、
演算器409とから構成される。 The AD converter 400 has an input selector switch 402,
403 and buffer amplifiers 404, 405 and AD
A converter 406, an offset data import register 407, a measurement data import register 408,
It is composed of a computing unit 409.
入力切換スイツチ402はバツフア増幅器40
4の入力端子をAD変換部400の共通電位点
CMに接続するスイツチを示す。この入力切換ス
イツチ402をオンにすることによりバツフア増
幅器404に共通電位点CMの電位を与え、この
ときAD変換器406に与えられる電圧をAD変
換する。このAD変換出力はバツフア増幅器40
4,405とAD変換器406のオフセツト電圧
に相当し、そのAD変換出力をオフセツトデータ
取込用レジスタ407に収納する。 The input selector switch 402 is the buffer amplifier 40
4 input terminal to the common potential point of the AD converter 400
Shows the switch connected to the CM. By turning on this input changeover switch 402, the potential of the common potential point CM is applied to the buffer amplifier 404, and the voltage applied to the AD converter 406 at this time is AD converted. This AD conversion output is output from buffer amplifier 40.
4,405 corresponds to the offset voltage of the AD converter 406, and its AD conversion output is stored in the offset data acquisition register 407.
スイツチ402をオフにし、スイツチ403を
オンにすることによりバツフア増幅器404に電
圧発生回路300に設けた差動増幅器305の出
力電圧を与え、AD変換器406において、電流
検出用抵抗器304を流れる電流量に対応した電
圧値をAD変換し、そのAD変換出力を測定デー
タ取込用レジスタ408に収納する。 By turning off the switch 402 and turning on the switch 403, the output voltage of the differential amplifier 305 provided in the voltage generation circuit 300 is applied to the buffer amplifier 404, and the current flows through the current detection resistor 304 in the AD converter 406. The voltage value corresponding to the amount is AD-converted, and the AD-converted output is stored in the measurement data acquisition register 408.
ここで真の測定値は測定データ取込用レジスタ
408に収納したデータ値X1とオフセツトデー
タ取込用レジスタ407に収納したデータ値X2
の差の値X1−X2となる。この演算を演算器40
9によつて実行し、真の電流測定値を求める。 Here, the true measured value is the data value X 1 stored in the measurement data acquisition register 408 and the data value X 2 stored in the offset data acquisition register 407.
The value of the difference is X 1 −X 2 . This calculation is performed by the calculator 40.
9 to determine the true current measurement.
「考案が解決しようとする問題点」
上述したように各部の回路200,300,4
00はバツフア増幅器201,303,401に
よつて共通電位点CMの電位が遠隔点に位置する
被試験IC101の端子PCMの電位となるように
制御されている。"Problems that the invention attempts to solve" As mentioned above, the circuits 200, 300, 4 of each part
00 is controlled by the buffer amplifiers 201, 303, and 401 so that the potential of the common potential point CM becomes the potential of the terminal PCM of the IC 101 under test located at a remote point.
この状態において特にAD変換器406のコモ
ン端子電流ICMはAD変換出力の変化に伴なつて
変化する。この電流変化は共通電位点CMを通じ
てバツフア増幅器401に吸収され、共通電位点
CMの電位変動を抑制している。 In this state, in particular, the common terminal current ICM of the AD converter 406 changes as the AD conversion output changes. This current change is absorbed by the buffer amplifier 401 through the common potential point CM.
Suppresses CM potential fluctuations.
然し乍らコモン端子電流ICMが高速度に変化
したとするとバツフア増幅器401も高速度で変
化しなければならない。このためバツフア増幅器
401は高速応答が可能な増幅器を用いなければ
ならないが、高速応答が可能な増幅器は高価なも
のとなる。 However, if the common terminal current ICM changes at a high speed, the buffer amplifier 401 must also change at a high speed. For this reason, an amplifier capable of high-speed response must be used as the buffer amplifier 401, but an amplifier capable of high-speed response is expensive.
またオフセツト電圧の測定値を被測定電圧の測
定値から減算する場合、オフセツト電圧の測定時
点と被測定電圧の測定時点に大きな時間差が有る
と誘導ノイズ等の影響により誤差が大きく発生す
る欠点がある。 Furthermore, when subtracting the measured value of the offset voltage from the measured value of the voltage to be measured, if there is a large time difference between the measurement time of the offset voltage and the measurement time of the voltage to be measured, there is a drawback that a large error will occur due to the effects of induced noise, etc. .
つまり第4図に示すようにバツフア増幅器40
4においてオフセツト電圧に誘導ノイズNSが混
入したとすると、時点t1でオフセツト電圧を測定
し、続いて時点t2で被測定電圧を測定したとする
と、その間の測定誤差は小さい。然し乍ら時点t3
で被測定電圧を測定したとすると大きな誤差が発
生する。 In other words, as shown in FIG.
Assuming that the induced noise NS is mixed into the offset voltage in step 4, if the offset voltage is measured at time t1 and then the voltage to be measured is measured at time t2 , the measurement error between them is small. However, time t 3
If the voltage to be measured is measured using this method, a large error will occur.
このようにオフセツト電圧の測定と被測定電圧
の測定の時間差を小さくすれば誘導ノイズによる
影響を受けることなく精度よく被測定電圧をAD
変換することができる。 In this way, by reducing the time difference between measuring the offset voltage and measuring the voltage under test, it is possible to accurately measure the voltage under test without being affected by inductive noise.
can be converted.
然し乍らオフセツト電圧測定と被測定電圧測定
を短かい時間間隔で行なうにはバツフア増幅器4
01として高価な高速応答形の増幅器を用いなけ
ればならない。 However, in order to measure the offset voltage and the voltage to be measured in a short time interval, a buffer amplifier 4 is required.
01, an expensive high-speed response amplifier must be used.
「問題点を解決するための手段」
この考案においては、AD変換器のコモン端子
を電源の共通電位点に接続するとともに、それぞ
れ実用新案登録請求の範囲で示したような、第1
および第2のバツフア増幅器、スイツチ回路、ア
ナログ演算回路およびデータ処理回路を設ける。"Means for solving the problem" In this invention, the common terminal of the AD converter is connected to the common potential point of the power supply, and the first
and a second buffer amplifier, a switch circuit, an analog arithmetic circuit, and a data processing circuit.
「実施例」
第1図は、この考案のAD変換装置の一例を用
いた測定システムの一例で、この考案のAD変換
装置の一例であるAD変換部400以外は基本的
に第3図に示した従来のものと同じである。``Example'' FIG. 1 shows an example of a measurement system using an example of the AD converter of this invention, and the components other than the AD converter section 400, which is an example of the AD converter of this invention, are basically shown in FIG. It is the same as the conventional one.
AD変換部400は、バツフア増幅器401、
一対のバツフア増幅器411,412、スイツチ
回路420、アナログ演算回路430、AD変換
器440およびデータ処理回路450を備える。 The AD conversion section 400 includes a buffer amplifier 401,
It includes a pair of buffer amplifiers 411 and 412, a switch circuit 420, an analog arithmetic circuit 430, an AD converter 440, and a data processing circuit 450.
バツフア増幅器401は、第3図に示したそれ
と同様に、回路網の共通電位点CMの電位が遠隔
点に位置する被試験IC101の端子PCMの電位
と同じになるようにするものである。 The buffer amplifier 401, similar to the one shown in FIG. 3, makes the potential of the common potential point CM of the circuit network the same as the potential of the terminal PCM of the IC under test 101 located at a remote point.
バツフア増幅器411および412は、第1図
の例においては、それぞれ非反転増幅器である。 Buffer amplifiers 411 and 412 are each non-inverting amplifiers in the example of FIG.
スイツチ回路420は、バツフア増幅器41
1,412の入力側を、それぞれ回路網の共通電
位点CMに接続するスイツチ421,422と、
バツフア増幅器411の入力側を電圧発生回路3
00の差動増幅器305の出力側に接続するスイ
ツチ423と、バツフア増幅器412の入力側を
電圧発生回路300における回路網の共通電位点
CMに接続するスイツチ424とによつて構成さ
れる。 The switch circuit 420 includes a buffer amplifier 41
switches 421 and 422 that connect the input sides of the switches 1 and 412 to the common potential point CM of the circuit network;
The input side of the buffer amplifier 411 is connected to the voltage generation circuit 3
The switch 423 connected to the output side of the differential amplifier 305 and the input side of the buffer amplifier 412 are connected to the common potential point of the circuit network in the voltage generation circuit 300.
A switch 424 connected to the CM.
アナログ演算回路430は、第1図の例におい
ては、減算回路で、バツフア増幅器411の出力
側が抵抗431を介して差動増幅器433の反転
入力端子に接続され、バツフア増幅器412の出
力側が抵抗432を介して差動増幅器433の非
反転入力端子に接続されて構成される。なお、差
動増幅器433の非反転入力端子側は電源Eの共
通電位点ECMに接続される。 In the example of FIG. 1, the analog arithmetic circuit 430 is a subtraction circuit, in which the output side of the buffer amplifier 411 is connected to the inverting input terminal of the differential amplifier 433 via the resistor 431, and the output side of the buffer amplifier 412 is connected to the inverting input terminal of the differential amplifier 433 via the resistor 431. It is connected to the non-inverting input terminal of the differential amplifier 433 via the differential amplifier 433. Note that the non-inverting input terminal side of the differential amplifier 433 is connected to the common potential point ECM of the power source E.
AD変換器440は、アナログ演算回路430
の差動増幅器433の出力電圧をAD変換するも
ので、そのコモン端子を電源Eの共通電位点
ECMに接続する。 The AD converter 440 is an analog calculation circuit 430
The output voltage of the differential amplifier 433 is AD converted, and its common terminal is connected to the common potential point of the power supply E.
Connect to ECM.
データ処理回路450は、後述するオフセツト
データと測定データとの差を求めるもので、オフ
セツトデータ取込用レジスタ457、測定データ
取込用レジスタ458および演算器459によつ
て構成される。 The data processing circuit 450 determines the difference between offset data and measurement data, which will be described later, and is composed of an offset data acquisition register 457, a measurement data acquisition register 458, and an arithmetic unit 459.
以上の構成において、最初に、スイツチ421
および422がオンにされ、スイツチ423およ
び424がオフにされて、バツフア増幅器411
および412に、それぞれ回路網の共通電位点
CMの電位が供給され、AD変換器440から、
バツフア増幅器411,412、差動増幅器43
3およびAD変換器440のオフセツト電圧が
AD変換されたオフセツトデータが得られて、そ
のオフセツトデータがオフセツトデータ取込用レ
ジスタ457に取り込まれる。 In the above configuration, first, the switch 421
and 422 are turned on, switches 423 and 424 are turned off, and buffer amplifier 411
and 412, respectively, the common potential point of the network.
The potential of CM is supplied, and from the AD converter 440,
Buffer amplifiers 411, 412, differential amplifier 43
3 and the offset voltage of AD converter 440 is
AD converted offset data is obtained, and the offset data is taken into the offset data taking register 457.
次に、スイツチ421および422がオフにさ
れ、スイツチ423および424がオンにされ
て、バツフア増幅器411とバツフア増幅器41
2との間に電圧発生回路300の差動増幅器30
5の出力側と回路網の共通電位点CMとの間に得
られる被測定電圧が供給され、AD変換器440
から、その被測定電圧に対して上述したオフセツ
ト電圧が重畳された電圧がAD変換された測定デ
ータが得られて、その測定データが測定データ取
込用レジスタ458に取り込まれる。 Next, switches 421 and 422 are turned off, and switches 423 and 424 are turned on, so that buffer amplifier 411 and buffer amplifier 41
2 and the differential amplifier 30 of the voltage generating circuit 300.
The voltage to be measured obtained between the output side of 5 and the common potential point CM of the circuit network is supplied to the AD converter 440.
From this, measurement data is obtained by AD converting the voltage obtained by superimposing the above-mentioned offset voltage on the voltage to be measured, and the measurement data is captured in the measurement data capture register 458.
その後、データ処理回路450の演算器459
において上述した測定データから上述したオフセ
ツトデータが減算されて、演算器459から上述
した被測定電圧に相当する真の測定データが得ら
れる。 After that, the arithmetic unit 459 of the data processing circuit 450
The offset data mentioned above is subtracted from the measurement data mentioned above, and true measurement data corresponding to the voltage to be measured mentioned above is obtained from the arithmetic unit 459.
第2図は、この考案のAD変換装置の他の例
で、バツフア増幅器411は非反転増幅器とされ
るが、バツフア増幅器412が反転増幅器とさ
れ、これに伴なつてアナログ演算回路430が加
算回路とされる、すなわちバツフア増幅器411
および412の出力側が抵抗435および436
を介して差動増幅器433の反転入力端子に接続
される場合である。 FIG. 2 shows another example of the AD conversion device of this invention, in which the buffer amplifier 411 is a non-inverting amplifier, but the buffer amplifier 412 is an inverting amplifier, and the analog arithmetic circuit 430 is an adder circuit. That is, the buffer amplifier 411
and the output side of 412 is resistor 435 and 436
This is the case where it is connected to the inverting input terminal of the differential amplifier 433 via the inverting input terminal of the differential amplifier 433.
「考案の効果」
この考案によれば、AD変換器440のコモン
端子を電源Eの共通電位点ECMに接続し、AD変
換器440のコモン端子電流ICMを電源Eに直
接帰路させるので、バツフア増幅器401として
高価な高速応答形のものを用いなくても、コモン
端子電流ICMを高速で変化させることができ、
AD変換器440を高速で動作させることができ
る。したがつて、オフセツト電圧の測定と被測定
電圧の測定を短かい時間間隔で行うことができ、
誘導ノイズNSの影響を受けない高精度の測定結
果を得ることができる。"Effect of the invention" According to this invention, the common terminal of the AD converter 440 is connected to the common potential point ECM of the power supply E, and the common terminal current ICM of the AD converter 440 is directly returned to the power supply E. It is possible to change the common terminal current ICM at high speed without using an expensive high-speed response type as 401.
AD converter 440 can be operated at high speed. Therefore, it is possible to measure the offset voltage and the voltage to be measured in a short time interval.
It is possible to obtain highly accurate measurement results that are not affected by induced noise NS.
第1図はこの考案の一実施例を示す接続図、第
2図はこの考案の変形実施例を説明するための接
続図、第3図は従来技術を説明するための接続
図、第4図は従来技術の不都合を説明するための
波形図である。
400はAD変換部、411および412は第
1および第2のバツフア増幅器、420はスイツ
チ回路、CMは回路網の共通電位点、430はア
ナログ演算回路、440はAD変換器、ECMは電
源の共通電位点、450はデータ処理回路であ
る。
Fig. 1 is a connection diagram showing one embodiment of this invention, Fig. 2 is a connection diagram for explaining a modified embodiment of this invention, Fig. 3 is a connection diagram for explaining the prior art, and Fig. 4. is a waveform diagram for explaining the disadvantages of the conventional technology. 400 is an AD conversion unit, 411 and 412 are first and second buffer amplifiers, 420 is a switch circuit, CM is a common potential point of the circuit network, 430 is an analog calculation circuit, 440 is an AD converter, and ECM is a common power supply A potential point 450 is a data processing circuit.
Claims (1)
を、それぞれ回路網の共通電位点に接続する第1
の切換状態と、上記第1のバツフア増幅器の入力
側を回路網の共通電位点との間に被測定電圧が供
給される端子に接続し、かつ上記第2のバツフア
増幅器の入力側を回路網の共通電位点に接続する
第2の切換状態とをとるスイツチ回路と、 上記第1のバツフア増幅器の出力と上記第2の
バツフア増幅器の出力を、上記第1および第2の
バツフア増幅器のいずれか一方が反転増幅器であ
るか否かに応じて加算または減算するアナログ演
算回路と、 このアナログ演算回路の出力をAD変換する、
コモン端子が電源の共通電位点に接続されたAD
変換器と、 上記スイツチ回路が上記第1の切換状態をとる
ときの上記AD変換器の出力データと上記スイツ
チ回路が上記第2の切換状態をとるときの上記
AD変換器の出力データとの差を求めるデータ処
理回路と、 を備えるAD変換装置。[Claims for Utility Model Registration] First and second buffer amplifiers;
, the input side of the first buffer amplifier is connected to a terminal to which the voltage to be measured is supplied between the common potential point of the circuit network, and the input side of the second buffer amplifier is connected to the terminal where the voltage to be measured is supplied between the common potential point of the circuit network. a switch circuit that assumes a second switching state connected to a common potential point of the buffer amplifier; An analog arithmetic circuit that adds or subtracts depending on whether one side is an inverting amplifier, and an analog arithmetic circuit that AD converts the output of this analog arithmetic circuit.
AD whose common terminal is connected to the common potential point of the power supply
a converter; output data of the AD converter when the switch circuit takes the first switching state; and output data of the AD converter when the switch circuit takes the second switching state.
An AD conversion device comprising: a data processing circuit that calculates a difference between output data of an AD converter;
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984150788U JPH0136362Y2 (en) | 1984-10-05 | 1984-10-05 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984150788U JPH0136362Y2 (en) | 1984-10-05 | 1984-10-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6168533U JPS6168533U (en) | 1986-05-10 |
JPH0136362Y2 true JPH0136362Y2 (en) | 1989-11-06 |
Family
ID=30708921
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1984150788U Expired JPH0136362Y2 (en) | 1984-10-05 | 1984-10-05 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0136362Y2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0789144B2 (en) * | 1988-06-01 | 1995-09-27 | 株式会社東芝 | Integrated circuit inspection method |
US4888725A (en) * | 1988-10-13 | 1989-12-19 | Tektronix, Inc. | Subtraction of wide band signals |
US7429856B1 (en) * | 2007-11-20 | 2008-09-30 | Qualitau, Inc. | Voltage source measurement unit with minimized common mode errors |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5825717A (en) * | 1981-08-07 | 1983-02-16 | Hitachi Ltd | AD converter |
-
1984
- 1984-10-05 JP JP1984150788U patent/JPH0136362Y2/ja not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5825717A (en) * | 1981-08-07 | 1983-02-16 | Hitachi Ltd | AD converter |
Also Published As
Publication number | Publication date |
---|---|
JPS6168533U (en) | 1986-05-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH0136362Y2 (en) | ||
JPH0645909Y2 (en) | IC test equipment | |
JPH10240560A (en) | Waveform signal processor | |
CN114062764A (en) | Direct current small current measuring system and method based on standard current | |
JP3353288B2 (en) | LSI test equipment | |
JPH0438303Y2 (en) | ||
JP3461258B2 (en) | Apparatus for measuring conductivity or pH | |
JPS63190975U (en) | ||
JPH0634705Y2 (en) | IC test equipment | |
JP3495545B2 (en) | Equipment for measuring dissolved oxygen or pH | |
JP3152726B2 (en) | Temperature detector | |
JP2565866Y2 (en) | IC tester parallel connected device power supply | |
JP3690583B2 (en) | measuring device | |
JP2827233B2 (en) | Semiconductor test equipment | |
JPH0514196A (en) | Input circuit with self-diagnostic function | |
JPH1062463A (en) | Method for measuring contact resistance of biological signal measuring electrode | |
JP2996989B2 (en) | Pin current measuring circuit of IC tester and its substrate | |
JP3469369B2 (en) | Electric measuring instrument | |
JP2968380B2 (en) | Input measuring device | |
JPH0875817A (en) | Voltage applied current measuring device | |
SU1122983A1 (en) | Device for measuring transistor current gain | |
JPH0446385B2 (en) | ||
JPH0448537Y2 (en) | ||
SU1232962A1 (en) | Digital thermometer | |
JPH05870Y2 (en) |