JPH0132673B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a MOS type nonvolatile semiconductor memory device having a floating gate electrode whose stored contents can be electrically rewritten.

Various types of electrically rewritable floating gate nonvolatile semiconductor memory devices have been proposed and put into practical use. A floating gate nonvolatile memory changes the charging state of the floating gate by injecting electrons or holes into a floating gate that is electrically insulated from the outside, and stores the difference in the charging state as information. Charge injection into the floating gate is basically performed by generating a high-energy carrier in the substrate and injecting it into the floating gate by overcoming the energy barrier of the oxide film, or by injecting the charge into the floating gate by using a high electric field to overcome the energy barrier of the oxide film. This is done by making use of the so-called tunnel phenomenon that penetrates through the tunnel. When using the former method, the breakdown of the P-N junction is usually required to generate the high-energy carrier.
In order to utilize the acceleration of the carrier in the channel of a MOS transistor, it is necessary to flow a considerably large current in addition to the current injected into the floating gate, which has the disadvantage of increasing power consumption during rewriting. On the other hand, in the latter case, no current flows other than the tunnel current, making it possible to reduce power consumption. As a floating gate nonvolatile memory device that utilizes such tunneling phenomenon,
For example, 1980 IEEE International Solid−State
Circuits Conference Digest of Technical
There is an N-channel type device published in Part 152 of Papers. A cross-sectional model diagram of this device is shown in FIG. 1st
In the device shown in the figure, an insulating film 22 thin enough to partially flow a tunnel current is formed on a drain N ⁺ diffusion region 27, and a floating gate electrode 23 is extended onto the thin insulating film 24. It has a unique structure. To write to this device, a high positive voltage is applied to the control gate electrode 25 provided on the floating gate to form a high electric field from the floating gate to the drain in the thin insulating film on the drain diffusion region. , tunneling electrons from the drain to the floating gate. On the other hand, erasing is performed by applying a high positive voltage to the drain diffusion region, forming a high electric field in the thin insulating film from the drain to the floating gate, and injecting electrons from the floating gate to the drain. As described above, in this device, it is possible to inject electrons into the floating gate and emit electrons from the floating gate using only a positive unipolar voltage. However, in this type of device having a thin insulating film over a portion of the drain diffusion region, as shown in FIG. 1, it is necessary to extend the floating gate over the thin insulating film over the drain. It is not possible to use the self-aligned formation method for the source/drain gate electrode, which is a very effective means of miniaturizing MOS transistors. Furthermore, considering that the mutual overlap of the drain diffusion region, thin insulating film region, and floating gate electrode is determined with errors in conventional PR and masking techniques, the It is necessary to increase the interval margin with a sufficient margin in terms of design. As described above, the conventional device shown in FIG. 1 has the disadvantage that it is not suitable for miniaturization and is not suitable for high integration, which will be increasingly demanded in the future.

The object of the present invention is to selectively inject electrons into the floating gate and emit electrons from the floating gate using the unipolar voltage of the conventional example described above, by utilizing the tunneling phenomenon, thereby making it possible to perform the electrical operation with low power consumption. It is an object of the present invention to provide a nonvolatile semiconductor memory device having a structure that can be easily integrated to a high degree by eliminating the disadvantage of being unsuitable for miniaturization of the conventional example while maintaining excellent characteristics.

A feature of the present invention is that a floating gate electrode is formed on a semiconductor substrate via a gate insulating film, a control gate electrode is provided to cover at least a portion of the floating gate electrode, and a substrate is formed in a self-aligned manner on the floating gate electrode. It has source and drain regions of the same conductivity type as the source and drain regions and has a lower impurity concentration than the source and drain regions so as to be in contact with the entire outer periphery under the floating gate of one or both of the source and drain regions. A non-volatile semiconductor memory device includes a region.

In the device of the present invention, unlike the conventional example described above, a tunnel current is passed through the entire gate insulating film on the channel region between the source and drain without forming a thin insulating film partially on the drain region. Form it to a thickness sufficient for To write in the present invention, the source, drain, and substrate are kept at a low potential, and a high positive voltage is applied to the control gate electrode to tunnel electrons from the substrate to the floating gate across the channel region. On the other hand, to erase, the control gate is kept at a low potential and a high positive voltage is applied to the drain electrode. The drain region is formed by, for example, ion-implanting an impurity using the floating gate electrode as a mask, and then activating and pushing it through high-temperature heat treatment. At this time, the drain region serves as a mask for a distance comparable to the depth direction. It penetrates into the channel from the edge of the floating gate electrode and overlaps with the floating gate electrode in a planar structure. This overlapping part is insulated by the thin gate insulating film mentioned earlier, and the high electric field due to the high positive voltage applied to the drain during erasing is formed in the thin insulating film in this overlapping part, and flows from the floating gate to the drain. Electrons are tunnel-emitted in the opposite direction. However, simply forming a thin gate insulating film over the entire structure strengthens the electric field near the substrate surface of the drain junction, lowering the breakdown voltage, and when the voltage required for erasing is applied to the drain, the drain junction causes avalanche breakdown, resulting in a large current. This causes the inconvenience of flowing. In order to prevent this, in the present invention, a region of the same conductivity type as the drain and with a low impurity concentration is provided so as to be in contact with at least the entire region under the thin gate insulating film among the outer periphery of the drain impurity region. This is the main idea. In the case of the N-channel type device mentioned above, this means that the N ⁺ -P junction between the drain and the substrate is N ^- -
The purpose is to increase the breakdown voltage of the drain junction by converting it into a P junction. In addition, if the impurity concentration in the drain region is simply lowered uniformly, the breakdown voltage increases, but the voltage applied during erasing causes the depletion layer to move from the interface between the gate insulating film on the drain and the drain region into the drain region. spreads, weakening the erasing electric field formed in the gate insulating film on the drain, and making erasing difficult.

As explained above, according to the present invention, it is possible to form a source and a drain in a self-aligned manner with respect to a floating gate, which is very advantageous for downsizing the device.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a cross-sectional model diagram of the first embodiment based on the present invention. Surface index (100) impurity concentration 1×
A gate silicon oxide film 2 with a thickness of 200 Å is grown on a P-type conductivity type single crystal silicon substrate 1 of 10 ¹⁵ /cm ³ in a high temperature oxygen atmosphere, and then a polycrystalline silicon oxide film 2 with a thickness of about 5000 Å is grown, which will become a floating gate electrode in the future. The film 3 is formed by a normal vapor phase growth method. The polycrystalline silicon film 3 is doped with N-type by thermal diffusion of phosphorus from the gas phase. Next, the polycrystalline silicon film 3 is thermally oxidized in a high-temperature oxygen atmosphere to grow an oxide film 4 with a thickness of about 800 Å, and then a second polycrystalline silicon film 5, which will become a control gate electrode in the future, is grown in a vapor phase. It is grown to a thickness of approximately 5000 Å using a growth method. Next, a desired photoresist pattern is formed on the polycrystalline silicon film 5 by ordinary masking and PR techniques, and the photoresist pattern is used as a mask, for example.
The shape of the polycrystalline silicon control gate electrode 5 is determined by plasma etching using CF ₄ gas.
Next, using the same photoresist pattern as a mask, unnecessary portions of the silicon oxide film 4 are removed by etching, and using the same photoresist pattern as a mask, unnecessary portions of the polycrystalline silicon film 3 are removed using the aforementioned plasma etching to form the floating gate. Electrode 3
The shape of is determined. In this manner, in this embodiment, the shapes of floating gate electrode 3 and control gate electrode 5 are determined in a self-aligned manner. Next, by using normal masking and PR techniques, the upper part of the part that will become the future source region is covered with a photoresist, and this photoresist and the control gate electrode 5, that is, the floating gate electrode 3 having the same shape, are used as a mask to form the future drain region. Phosphorus, an N-type impurity, is added to the base of the part that becomes
Ion implantation is performed at an energy of 150 keV and an implantation dose of 1×10 ¹³ /cm ² . After that, the photoresist is removed, and using the control gate electrode 5 and floating gate electrode 3 as masks, arsenic, which is an N-type impurity, is injected into the substrate in the parts that will become source and drain regions in the future at an energy of 150 keV.
Ions are implanted at an implantation dose of 1×10 ¹⁶ /cm ² . At this time, the polycrystalline silicon control gate electrode 5 is also doped to N type. After that, phosphorus and arsenic, which are N-type impurities, are activated and pushed through high-temperature heat treatment, resulting in N ⁺
The source 6, drain 7 and phosphorus which are diffusion regions
N ⁻ region 8 is formed. As in this example, by ion-implanting phosphorus and arsenic into the same region with appropriate energy and dosage and performing high-temperature heat treatment, it is possible to utilize the fact that phosphorus has a larger diffusion coefficient in silicon than arsenic. , an N ⁻ region 8 of phosphorus can be automatically formed around the outer periphery of the drain region N ⁺ region 7 . The depth of the source/drain N ⁺ regions 6, 7 and the width of the phosphorus N ^- region can be set appropriately as necessary, but in this embodiment, the depth of the source/drain N ⁺ regions 6, 7 is approximately 0.5 μm, and the width of the phosphorus N ⁻ region was approximately 0.5 μm. This high-temperature heat treatment also reduces the drain N ⁺
The region is also pushed in the lateral direction at the same time to form an overlapping region 9 with the floating gate electrode. Thereafter, a silicon oxide film 10 of approximately 1 μm is grown using a normal vapor phase growth method, and then contact holes 11 and 1 are grown.
2 and 13 are made, and aluminum source wiring 14, drain wiring 15, and control gate wiring 1 are formed.
form 6. To write to the nonvolatile memory device manufactured in this way, the substrate 1, the source wiring 14, and the drain wiring 15 are kept at ground potential, and a positive high voltage pulse is applied to the control gate wiring 16. Electrons are tunnel-injected from the substrate, source, and drain into the floating gate 3 through the gate oxide film 2 of 200 Å. On the other hand, to erase, the control gate wiring 16, the substrate 1, and the source wiring 14 are kept at ground potential, and a positive high voltage pulse is applied to the drain wiring 15.
Electrons are transferred to the drain 7 through a 200 Å gate oxide film.
Emit tunnel to. At this time, since the N ^- region 8 covers the outer periphery of the drain N ⁺ region 7, the breakdown voltage of the drain junction increases, and avalanche breakdown occurs at the drain applied voltage within the range necessary for tunnel emission. The problem of large current flowing did not occur.

FIG. 3 is a cross-sectional model diagram of a second embodiment based on the present invention.

In this embodiment, in addition to the device described in Embodiment 1, a phosphorus N ^- region is also provided on the source region 6 side. This new source side phosphorus N ^-region 1
7 does not add any new features to the electrical characteristics of the device of Example 1, but simplifies the manufacturing process. That is, in Example 1, in order to provide the phosphorus N ^- region only on the drain side,
When implanting phosphorus ions to form an N ^- region, it was necessary to cover the source region with a photoresist, but if a phosphorus N ^- region is provided in contact with both the source and drain regions, the photoresist for the ion implantation described above is necessary. The masking process can be omitted.
However, in this case, the distance between the source and drain is effectively shortened, making it easier for so-called punch-through current to flow between the source and drain.
In terms of design, it was necessary to make the distance between the source and drain larger than in the first embodiment.

FIG. 4 is a cross-sectional model diagram of a third embodiment based on the present invention. In this embodiment, in addition to the device of embodiment 1, a region 18 having the same conductivity type as the substrate and having a higher impurity concentration than the substrate is provided so as to be in contact with the outer peripheral edge of the source region 6. To provide this region, in Example 1, the source region is covered with a photoresist, phosphorus ions are implanted into the drain region to form an N ^- region, the masking photoresist is removed, and then the drain region is covered with a photoresist. is covered with photoresist, and boron, which is a P-type conductivity type impurity, is ion-implanted into the source region at an energy of 50 keV and an implantation dose of 1×10 ¹² /cm ² . After that, as in Example 1, arsenic is ion-implanted into both the source and drain regions, and high-temperature heat treatment is performed to form phosphorus N ^- region 8 and boron.
A P ⁺ region is formed automatically. Here, too, the fact that boron has a larger diffusion coefficient in silicon than arsenic is utilized. Example 3 manufactured in this way
In this device, boron P ⁺ is applied only to the periphery of the source region 6.
Because of the presence of region 18, the same effect as effectively increasing the impurity concentration of the substrate can be obtained without reducing the breakdown voltage of the drain junction, and the so-called punch-through voltage between the source and drain can be reduced. This makes it possible to make it difficult to generate punch-through current due to the high voltage applied to the drain during erasing.

Although the present invention has been described above with reference to examples, each example is merely for illustrative purposes, and the present invention is not limited thereto. For example, although all of the embodiments have been described with respect to N-channel devices, the present invention can easily be applied to P-channel devices by reversing the conductivity type and voltage polarity in the text. Also,
Changes in dimensions, materials, relative positions of various parts of the device, manufacturing method, order of steps, etc. can also be changed as appropriate without departing from the gist of the present invention.

As described above, according to the present invention, it is possible to electrically rewrite the device, which is suitable for the miniaturization and high integration of semiconductor devices that will continue to progress in the future, by eliminating the disadvantages of the conventional example in terms of device miniaturization. Non-volatile memory devices can be easily realized.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional model diagram of a conventional device, and FIGS. 2 to 4 are cross-sectional model diagrams of each embodiment according to the present invention. In the figure, 1...P-type silicon single crystal base, 2...gate silicon oxide film, 3...polycrystalline silicon floating gate electrode, 4, 10...silicon oxide film, 5...polycrystalline silicon control gate Electrode, 6... N ⁺ source region, 7... N ⁺ drain region, 8, 17... N ^- region, 9... floating gate and drain overlap region, 11, 12, 13... contact hole, 14, 15, 16...Aluminum wiring, 18...P ⁺ region, 21...P type substrate, 2
2... Gate insulating film, 23... Floating gate, 24
... Thin insulating film, 25 ... Control gate, 26 ...
N ⁺ source, 27...N ⁺ drain.

Claims (1)

[Scope of Claims] 1. A floating gate electrode provided on a semiconductor substrate of one conductivity type via a gate insulating film, a control gate electrode provided so as to cover part or all of the floating gate electrode, It has a substrate and source/drain regions of opposite conductivity type that are self-aligned to the floating gate electrode, and electrons are transferred to the floating gate electrode by a tunneling phenomenon between the floating gate electrode and the gate insulating film within the semiconductor substrate. inject and
and a non-volatile semiconductor memory device in which electrons are emitted from the floating gate electrode by a tunneling phenomenon in the gate insulating film, the drain region extending below the floating gate electrode, a low concentration impurity region; The gate insulating film between the semiconductor substrate and the floating gate electrode including the source/drain region and the channel region of the source/drain region is uniform at all locations. having a film thickness, and connecting the source to the floating gate electrode.
Electrons are injected from the entire surface of the channel region between the drain regions by a tunneling phenomenon in the gate insulating film, and electrons stored in the floating gate electrode are released to the drain electrode by a tunneling phenomenon in the gate insulating film. Non-volatile semiconductor memory device. 2 The same conductivity type as the source and drain, and the source and drain.
Claim 1, characterized in that a region with an impurity concentration lower than that of the drain is further provided on the source region side, and the low impurity regions on the drain side and the source side are arranged so as not to touch each other.
The non-volatile semiconductor memory device described in 2. 3. The nonvolatile device according to claim 1, characterized in that a region of the same conductivity type as the substrate and with a higher impurity concentration than the substrate is provided so as to be in contact with the entire periphery of the source region under the floating gate. Semiconductor memory device.