JPH01318132A - Data rewriting detecting circuit - Google Patents

Abstract

PURPOSE:To detect a change in data to be written in a prescribed area of a memory without laying load upon a processor by sending an address of an area to be written to a processor bus at the time of writing data from the processor to the prescribed area, and preparing time for executing reading operation up to the instruction of writing operation to the memory. CONSTITUTION:At the time of writing data from the processor 1 to the prescribed area of the memory 2, reading data (dr) read out from the prescribed area prior to its writing are stored in a holding means 100 of a data rewriting detecting circuit 6. After reading out the reading data (dr), writing data (dw) written from the processor 1 to the memory 2 are compared with the reading data (dr) stored in the means 100 by a comparing means 200 to detect discrepancy between the reading data (dr) and the writing data (dw) by the comparing means 200. At the time of detecting the discrepancy by the means 200, the detection is informed to the processor 1 by an informing means 300 to reduce the load of the processor 1.

Description

[Detailed Description of the Invention] [Summary] Regarding a data rewriting detection circuit that detects changes in data repeatedly written by a processor to a memory, it is possible to detect changes in data written to the memory without reducing the processing performance of the processor. In order to enable rapid detection, when data is written from a processor to a predetermined area of a memory via a processor bus, a holding means for holding read data read from the predetermined area prior to writing, and a reading a comparison means for comparing the write data written from the processor to the memory after the data is read and the read data held in the holding means; and the comparison means detects a mismatch between the read data and the write data. The system is configured to include notification means for notifying the processor.

[Industrial application field]

The present invention relates to a data rewrite detection circuit that detects changes in data repeatedly written by a processor to a memory.

In an information processing system, while a processor repeatedly writes data to a predetermined area of a memory, when a change occurs in the written data, it may be required to start the next process in response to the change.

[Conventional technology]

FIG. 5 is a diagram showing an example of a conventional information processing system.

In FIG. 5, a processor 1, a memory 2, a keyboard 3 and a display 4 are interconnected via a processor bus 5.

The processor 1 includes an operating system 11 that controls all the information processing executed by the processor 1, a plurality of tasks 12 that share each information processing executed by the processor 1, and a timer 13 that notifies the passage of a predetermined time. is shown.

When the processor 1 executes a process of displaying characters entered by operating various character keys provided on the keyboard 3 on the display 4, task 12-1 executes a process of displaying characters input by operating various character keys provided on the keyboard 3 on the display 4. The operation status is periodically monitored and the data d is stored in a predetermined area 21 in the memory 2 without indicating the operation status.
The task 12-2 writes to the predetermined area 21 in the memory 2.
The data d written in the data d is read out, and the display on the display 4 is updated in accordance with changes in the data d.

In this case, each time the task 12-1 writes new data d to the predetermined area 21 in the memory 2, it requests the operating system 11 to start the task 12-2 based on the inter-task communication function.

Upon receiving the request from task 12-1, the operating system 11 uses the inter-task communication function to request task 12-2.
Start.

The activated task 12-2 is stored in a predetermined area 2 in the memory 2.
1, it is analyzed whether the data d has changed or not, and if it has changed, the display on the display 4 is updated.

[Problem to be solved by the invention]

As is clear from the above description, in a conventional information processing system, the task /'12 changes the display on the display 4 based on the data d written to the predetermined area 21 in the memory 2 by the task 12-1. -2, the inter-task communication function via the operating system 11 was used, so the operating system 11
There was a problem in that the processing time increased due to the inter-task communication function.

Note that instead of using the inter-task communication function, timer 1
It is also considered that task 12-2 periodically activates task 12-2 to monitor data d written in a predetermined area 21 in memory 2, but this would require processing associated with timer 13.
There was a fear that the processing capacity of the processor 1 would be reduced.

SUMMARY OF THE INVENTION An object of the present invention is to enable rapid detection of changes in data written to memory without reducing processing performance of a processor.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, l is a processor, 2 is a memory, and 5 is a processor bus.

6 is a data rewrite detection circuit provided according to the present invention, and 100, 200, and 300 are holding means, comparison means, and notification means provided in the data rewrite detection circuit 6, respectively.

[Effect]

When the processor 1 writes data to a predetermined area of the memory 2, after sending an address indicating the area to be written to the processor bus 5 and before instructing the memory 2 to perform the write operation,
There is a period during which the memory 2 performs a read operation, and data already written in the write target area is read out during this period.

The present invention takes advantage of a read operation that precedes such a write operation.

The holding means 100 connects the processor 1 to the processor bus 5.
When writing data to a predetermined area of memory 2 via
read data d read from a predetermined area prior to writing;
hold.

The comparison means 200 writes write data d, which is written from the processor 1 to the memory 2, after the read data d is read. and the read data d1 held in the holding means 100 are compared.

The notification means 300 notifies the processor 1 that the comparison means 200 has detected a mismatch between the read data d and the write data d8.

Therefore, it is possible to detect a change in the data written in a predetermined area of the memory without placing any burden on the processor, and promptly notify the processor.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

2 is a diagram showing an information processing system according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of the data rewriting detection circuit in FIG. 2, and FIG. 4 is a diagram showing various types of data in FIG. 3. It is a figure which illustrates a signal. Note that the same reference numerals indicate the same objects throughout the figures.

3, a read data holding circuit 61 is provided as the holding means 100 in FIG. 1, a data comparing circuit 62 is provided as the comparing means 200 in FIG. 1, and a gate is provided as the notifying means 300 in FIG. 6
3-1 to 63-m.

A decoder 64 and launch circuits 65-1 to 65-m are provided.

In FIGS. 2 to 4, in order for the processor 1 to execute the process of displaying characters input by operating various character keys provided on the keyboard 3 on the display 4,
Processor 1 connects keyboard 3 via processor bus 5.
After periodically monitoring the operation status of the above various character keys and extracting data d indicating the operation status, data is sent to the processor bus 5 in order to be written to the predetermined area 21 in the memory 2. The address a indicating the address is sent.

Note that at this stage, the write signal W sent by the processor 1 to the memory 2 via the processor bus 5 is still set to a read instruction state (for example, logic "1").

As a result, address a1 and read instruction state (logical “1”)
”), the memory 2 receives the write signal W set to
The data d written in the predetermined area 21 up to that point is then read out.

), and is sent to the processor bus 5.

Address a sent by processor l to processor bus 5
The read data d sent from the memory 2 to the processor bus 5 are also transmitted to the data rewrite detection circuit 6 via the processor bus 5.

In data rewrite detection circuit 6, address a transmitted via processor bus 5 is input to decoder 64, and read data d1 is input to read data holding circuit 61 and data comparison circuit 62.

The decoder 64 operates at predetermined addresses al to al.
When l is input, decode signals r1 to r and % (logic "l") are outputted to gates 63-1 to 63, respectively.
Enter -m. For example, when address a1 indicating a predetermined area 21 in memory 2 is input, decode signal r1
Suppose that ? is input to the gate 63-1.

On the other hand, when the timing signal c1 is input, the read data holding circuit 61 holds the input read data d7. Note that the timing signal C4 is synchronized with the access cycle T from the processor l to the memory 2.
The read data d read from the processor bus 5 is generated in the data rewrite detection circuit 6 at the same time as the read data d is determined on the processor bus 5.

The data comparison circuit 62 compares the read data d1 directly input from the processor bus 5 with the read data d1 held in the read data holding circuit 61, and when it is confirmed that the two match, it outputs a mismatch signal n. is set to logic “0”.

As a result, all the games 63-1 to 63-m to which the mismatch signal n (logic "0") is input are cut off, and regardless of the decoded signals r1 to r input from the decoder 64, The output interrupt signals il to i are set to logic "0".

On the other hand, after a predetermined period of time has elapsed since the processor 1 sent the address a to the processor bus 5, the processor 1 sends newly extracted data d (hereinafter referred to as write data d1) from the keyboard 3 to the processor bus 5. The write signal W sent to the processor bus 5 is set to a write instruction state (for example, logic "0").

As a result, the memory 2 that receives the address al, the write data d, and the write signal W set to the write instruction state (logic "0") writes the write data d1 into the predetermined area 21.

The write data d8 sent to the processor bus 5 by the processor 1 is also transmitted to the data rewrite detection circuit 6 via the processor bus 5, and is input to the read data holding circuit 61 and the data comparison circuit 62.

Since the timing signal c1 is not input while the write data d is being input, the read data holding circuit 61 continues to hold the held read data d7.

The data comparison circuit 62 compares the write data d1 inputted from the processor bus 5 and the read data d held in the read data holding circuit 61.

If no new character is input from the keyboard 3 and the character key operation status remains the same as before, the read data d and the write data d compared by the data comparison circuit 62 do not match. , the mismatch signal n is set to logic "0", but if a new character is input from the keyboard 3 and the character key operation status is different from the previous time, the data comparison circuit 62 performs a comparison. The read data dr and the write data dw do not match, and the mismatch signal n is a logic “
l”.

When the mismatch signal n is set to logic "1", the gate 63
-1 to 63-m are in a conductive state, and the gate 63-1, which receives the decode signal r set to logic "1" from the decoder 64, outputs the interrupt signal i, which is set to logic "1".
The other gates 63-2 to 63- are input with decode signals r2 to r set to logic "0".
m is the interrupt signal i! to i, are set to logic "0".

The latch circuits 65-1 to 65-m receive interrupt signals 1-63-1 to 63-m respectively. i, are held in synchronization with the input timing signal C2 and transmitted to the processor l. Note that the timing signal C2 detects data rewriting in synchronization with the access cycle T from the processor 1 to the memory 2, and coincides with the time when the write data d sent from the processor 1 is finalized on the processor bus 5. generated within circuit 6.

On the other hand, when the processor 1 detects that only the interrupt signal il among the interrupt signals i to i transmitted from the data rewrite detection circuit 6 is set to logic "1", the It is determined that a change has occurred in the write data d written in the area 21, and the process of updating the display on the display 4 is started.

As is clear from the above description, according to this embodiment, when the data rewrite detection circuit 6 detects that the write data d1 extracted from the keyboard 3 by the processor 1 has changed from the previous time, it immediately transmits the information to the processor l. The interrupt signal 11 is set to logic "1" to notify a change in write data dw. Therefore, the processor 1 can immediately start updating the display on the display 4 without analyzing whether there is a change in the write data d1.

Note that FIGS. 2 to 4 are only one embodiment of the present invention, and for example, the sending of address a, read data d7, write data d, . . . write signal W, and timing signals C1 and c. The timing is not limited to that illustrated, and many other modifications may be considered, but the effects of the present invention remain the same in any case. Furthermore, the information processing system to which the present invention is directed is not limited to one that displays characters input from the keyboard 3 shown in the figure on the display 4 (
Although many other modifications may be considered, the effects of the present invention remain the same in any case.

〔Effect of the invention〕

As described above, according to the present invention, in the information processing system, it is possible to detect a change in data written in a predetermined area of the memory without imposing any burden on the processor, and to promptly notify the processor.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an information processing system according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of the data rewriting detection circuit in FIG. FIG. 4 is a diagram illustrating various signals in FIG. 3, and FIG. 5 is a diagram illustrating an example of a conventional information processing system. In the figure, l is a processor, 2 is a memory, 3 is a keyboard, 4 is a display, 5 is a processor bus, 6 is a data rewrite detection circuit, 11 is an operating system,
12 is a task, 13 is a timer, 21 is a predetermined area, 61 is a read data holding circuit, 62 is a data comparison circuit, 63-1
63-m to 63-m are gates, 64 is a decoder, 65-1 to 65-m are latch circuits, 100 is a holding means, 200 is a comparison unit, Namu beef 2
ω shi 2 cattle 2 [shares] (Kookeru production damage police, out of stock) 3 units * 3 ward purchases;

Claims (1)

[Claims] When data is written from the processor (1) to a predetermined area of the memory (2) via the processor bus (5), read data (d_
r); write data (d_w) written from the processor (1) to the memory (2) after the read data (d_r) is read; and the holding means Comparison means (200) for comparing the read data (d_r) held in (100)
and notification means (300) for notifying the processor (1) that the comparison means (200) has detected a mismatch between the read data (d_r) and the write data (d_w).
A data rewrite detection circuit comprising: