JPH01315160A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance a device characteristic and to enhance a yield by a method wherein a groove for device isolation use is blocked by using a silicon layer and an insulating layer which have been formed selectively at the upper part of the groove and the inside of the groove is made hollow in order to relax a stress of a semiconductor substrate around the groove. CONSTITUTION:A silicon oxide film 2 is formed on a silicon substrate 1; after that, it is etched and removed selectively; a U-shaped groove 3 for device isolation use is formed. A silicon oxide film 4 is etched; the silicon substrate 1 is exposed only on side faces at the upper part of the U-shaped groove 3. A single- crystal silicon layer 7 is epitaxially grown selectively on the exposed silicon substrate 1 in order to control that an opening width of the U-shaped groove 3 is narrowed by the silicon layer 7 and that the groove is kept open. Then, a silicon oxide film 8 as an insulating layer is grown, by thermal oxidation, on the silicon layer 7; the U-shaped groove 3 is blocked by the silicon oxide film 8; the inside of the U-shaped shaped groove 3 is made hollow. By this setup, it is possible to relax a stress of the semiconductor substrate around the groove, to prevent a crystal defect from being caused, to enhance a device characteristic and to enhance a yield.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method of manufacturing a semiconductor device, and in particular to a method of forming an element isolation region of a semiconductor integrated circuit using a liquid for element isolation. The purpose of this layer is to block the element isolation liquid with a layer to make the groove hollow, thereby alleviating stress on the semiconductor substrate around the groove, improving element characteristics and yield. forming a first insulating layer on the semiconductor substrate inside the groove; and selectively removing the first insulating layer on the inside of the groove to remove the first insulating layer on the semiconductor substrate. selectively growing a silicon layer on the exposed semiconductor substrate to narrow the opening width of the trench; and growing a second silicon layer on the silicon layer.
forming an insulating layer to close the groove.

[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an element isolation region of a semiconductor integrated circuit using an element isolation solution.

In recent years, as semiconductor integrated circuits have become faster and more highly integrated,
It is required to make the element isolation region as small as possible. For this purpose, an element isolation method is used in which a region formed on a semiconductor substrate is used as an element isolation region.

[Prior Art] In a conventional method for forming an element isolation region of a semiconductor integrated circuit in which an element isolation region is formed on a semiconductor substrate, first, as shown in FIG. Form a lecture. Next, silicon oxide II! is deposited on the semiconductor substrate 21 inside this groove. 22 is formed. Subsequently, after depositing a polycrystalline silicon layer over the entire surface, this polycrystalline silicon layer is etched from above to form silicon oxide I.
I! The polycrystalline silicon layer 23 is left only in the groove above the polycrystalline silicon layer 22 (see FIG. 3(a)).

Furthermore, the exposed upper surface of this polycrystalline silicon layer 23 is camp-oxidized to form silicon oxide 11i24 (see FIG. 3(b)).

In this way, the polycrystalline silicon layer 23 is buried in the trench formed on the semiconductor substrate 21 via the silicon oxide film 22, and the upper surface of the polycrystalline silicon layer 23 is cap oxidized to form the silicon oxide film 23. Element isolation is carried out in a manner that covers the entire circuit.

[Problems to be Solved by the Invention] As described above, according to the above-described conventional method, the upper surface of the polycrystalline silicon layer 23 buried in the trench for element isolation via the silicon oxide film 22 is cap oxidized and silicon oxidized. When forming the film 24, the volumetric expansion accompanying this cap oxidation generates a large stress in the semiconductor substrate 21 around the groove shown in section A in FIG. 3(b), resulting in crystal defects.

This has caused a problem of deterioration of device characteristics and a decrease in yield.

Therefore, the present invention closes the upper part of the groove to make the inside of the groove hollow.
The purpose of this is to alleviate the stress on the semiconductor substrate around the groove, thereby improving device characteristics and yield.

Further, due to the shape of the trench for element isolation formed on the semiconductor substrate 21, the polycrystalline silicon layer 23 buried in the trench via the silicon oxide film 22 cannot completely fill the inside of the trench. As shown in FIG. 4(a), a minute cavity 25a may be formed in the polycrystalline silicon layer 23 covered by the silicon oxide film 2/1a. Such a cavity 25a moves to the upper part of the groove by heat treatment in a subsequent step and becomes a cavity 25b, impairing the flatness of the surface of the silicon oxide JI 24b covering the groove (see FIG. 4(b)). As a result, the flatness in the element isolation region is significantly deteriorated, causing a problem that the aluminum wiring layer is broken.

Therefore, an object of the present invention is to form an insulating layer with a flat surface above the element isolation trench to planarize the element isolation region and improve the yield.

[Means for Solving the Problems] The above problems include a step of forming a trench for element isolation on a semiconductor substrate, a step of forming a first insulating layer on the semiconductor substrate inside the trench, and a step of forming a first insulating layer on the semiconductor substrate inside the trench. selectively removing the first insulating layer on the inside to expose the semiconductor substrate; and selectively growing a silicon layer on the exposed semiconductor substrate to narrow the opening width of the trench. This is achieved by a method for manufacturing a semiconductor device, comprising the steps of: forming a second insulating layer on the silicon layer to close the groove.

The above-mentioned problems also include a step of forming a layer for element isolation on a semiconductor substrate, a step of forming a first insulating layer on the semiconductor substrate inside the trench, and a step of forming a first insulating layer on the semiconductor substrate on the inside of the trench. selectively removing the semiconductor substrate to expose the semiconductor substrate;
selectively growing a silicon layer on the exposed semiconductor substrate, forming a second insulating layer on the silicon layer, and forming a third insulating layer on the second insulating layer. This is achieved by a method for manufacturing a semiconductor device, which comprises the step of closing the groove by closing the groove.

[Function] That is, the present invention narrows the opening width of the trench by a silicon layer selectively formed on the top of the trench for element isolation, closes the trench with an insulating layer formed on this silicon layer, and makes the inside of the trench hollow. That is. This alleviates stress on the semiconductor substrate around the groove, prevents crystal defects from occurring, and improves device characteristics and yield.

[Example] Hereinafter, the present invention will be specifically explained with reference to illustrated embodiments.

FIG. 1 is a process diagram showing a method of forming an element isolation region of a semiconductor integrated circuit in a first embodiment of the present invention.

After forming a silicon oxide film 2 on a silicon substrate 1 serving as a semiconductor substrate, the silicon oxide film 2 at predetermined locations is selectively etched away. Using the remaining silicon oxide film 2 as a mask, for example, chlorine-based reactive ion etching (
RIE), and the thickness is about 1.2 μm and the depth is 5.0 μm.
A U clear layer 3 for element isolation is formed. Next, temperature 1
A silicon oxide film 4 having a thickness of about 3000 Å is formed as an insulating layer on the silicon substrate 1 within the U-groove 3 by thermal oxidation at 000°C (see FIG. 1 (a>)).

Next, after applying resist 5 to the entire surface, exposure and development are performed. At this time, the thickness of the exposed resist is controlled by the exposure time. That is, the resist 5 buried in the U-groove 3 is exposed to a desired depth, and the resist deeper than that is not exposed. The desired depth at this time is preferably about 3,000 depth from the surface of the silicon substrate 1 at the edge part of the U-groove 3, as shown in FIG.
b)).

The resist thus exposed is developed and removed. Furthermore, the unexposed resist 6 remains in the U-column 3 as it is (see FIG. 1(c)).

Next, using the resist 6 remaining in the U-layer 3 as a mask, the silicon oxide film 4 is etched with a hydrofluoric acid solution to expose the silicon substrate 1 only on the upper side surface of the U-layer 3. Then, the resist 6 is removed (Fig. 1(d)
)reference).

Next, a single crystal silicon layer 7 having a thickness of 400 OA is selectively epitaxially grown on the exposed silicon substrate 1 using, for example, dichlorosilane (SiH2C12) at a pressure of 80 Torr and a temperature of about 900.degree. At this time, the thickness of the silicon layer 7 is controlled so that the opening width of the U well 3 is sandwiched between the silicon layer 7 and remains open.

In the first embodiment, the film thickness is set to 0 for about 4000 people (see FIG. 1(e)).

Next, silicon oxide M8 as an insulating layer is grown on the silicon layer 7 by thermal oxidation. At this time, the silicon oxide 88 must have a thickness necessary to insulate the silicon layer 7 on both sides of the upper part of the U-groove 3, and therefore, the thickness is required to be at least about 3,000.

Furthermore, since the film must be thick enough to grow from both sides of the U-groove 3 and connect to each other, the film thickness of the silicon oxide WA8 was increased by about 4,000 in the first embodiment. In this way, the U groove 3 is closed by the silicon oxide film 8, and the inside of the U groove 3 becomes hollow (see <f> in FIG. 1).

Next, 0 boron phosphorus glass (BPSG) 9 with a thickness of about 5000 nm is deposited over the entire surface as a reflowable insulating layer. At this time, the impurity concentrations of boron (B) and phosphorus (P) in BPSG9 are each 6% by weight. In a wet atmosphere at a temperature of 900°C, 3
Heat treatment is performed for about 0 minutes to reflow the BPSG 9 and flatten the surface of the BPSG 9. Subsequently, the BPSG 9 is back-etched using a hydrofluoric acid solution to form a BPSG 9 having a flat surface and a desired thickness above the U liquid 3 (see FIG. 1(g)).

In this way, a U layer 3 for element isolation is formed on the silicon substrate 1, and a silicon layer 7 is selectively formed on the upper side surface of this U layer 3 to narrow the opening width of the U layer 3. 7
Silicon oxide [8 is formed on top of the silicon oxide M8.
The U-hole 3 is closed to make the inside of the U-hole 3 hollow, and the surface becomes flat, and PSG 9 is formed on the silicon oxide 11!8.

Therefore, according to the first embodiment, the silicon layer 7 blocking the U eraser 3 and the silicon oxide p! By controlling the thickness of A8, the stress generation can be alleviated. That is, since the thickness of the silicon oxide ylA8 formed in the U section 3-F section is thinner than in the past, the thermal oxidation step is shortened, and as a result, the stress on the silicon substrate 1 can be alleviated. .

Furthermore, by forming the PSG 9 above the U-circuit 3 so that the surface thereof is flat, the element isolation region can be flattened. Therefore, it is possible to prevent breakage of the aluminum wiring layer formed on the element isolation region and improve the yield.

Next, a second embodiment of the present invention will be described using FIG. 2.

The steps shown in FIGS. 2<a) to (d) are shown in FIGS. 1<a) to (d) in the first embodiment.

The process is the same as that performed.

Next, a single crystal silicon layer 10 is selectively epitaxially grown on the exposed silicon substrate 1 in the same manner as in the first embodiment. The silicon layer 10 narrows the opening width of the U opening 3. However, at this time, the thickness of the silicon layer 10 is made thinner than in the first embodiment. In this way, in the second embodiment, about 3,000 people
The film thickness was determined (see FIG. 2(e)).

Next, a silicon oxide film 11 as an insulating layer is grown on the silicon layer 10 by thermal oxidation. The thickness of the silicon oxide film 11 at this time is 40 mm as in the first embodiment.
About 00 people got fins. In this way, the opening width of the U groove 3 is further narrowed by this silicon oxide film 11;
The trench 3 is not closed (see FIG. 2(f)), so in the second embodiment, no stress is generated due to volume expansion during the growth of the silicon oxide film 11.

Next, BPSG12 was deposited as an insulating layer on the entire surface,
This BPSG 12 is reflowed by heat treatment to make the surface flat, and then pack etching is performed to form a BPSG 12 with a flat surface and a desired thickness above the U eraser 3. At this time, the opening width of the U-wound 3 is equal to the width of the silicon layer 1.
0 and the silicon oxide film 11, the BPSG 12 is not deposited to fill the inside of the U groove 3, but is deposited in a shape that fills the opening of the narrowed U groove 3. , make the inside of U lecture 3 hollow (Fig. 2 (
(see g)).

At this time, for example, if BPSG is deposited on the wide opening with an initial opening width of about 1.2 μm in U-section 3, the BPS
Since G has poor coverage compared to polycrystalline silicon, for example, cavities may occur within the BPSG, and the BPSG may
However, in the second embodiment, the opening width is sufficiently narrowed as described above.
43, such a problem does not occur.

In this way, the U groove 3 for element isolation is formed on the silicon substrate 1, and the silicon layer 10 is selectively formed on the upper side surface of the U groove 3 to narrow the opening width of the U groove 3. 10, silicon oxide WA11 is formed on the silicon oxide W111, the opening width of the U tube 3 is further narrowed, BPSG12 is deposited on it, the U tube 3 is closed, the inside of the U tube 3 is made hollow, and the opening width of the U tube 3 is made hollow. Make the surface flat.

Therefore, according to the second embodiment, stress can be prevented from occurring by controlling the thicknesses of the silicon layer 10 and the silicon oxide film 11, which narrow the opening width of the U-groove 3, respectively. Therefore, the device characteristics can be improved,
Yield can be improved.

Furthermore, by forming the PSG 12 above the U-circuit 3, which has a flat surface, the element isolation region can be flattened. Therefore, it is possible to prevent breakage of the aluminum wiring layer formed on the element isolation region and improve the yield.

In the first and second embodiments, the silicon layer 7.10 is made of selectively epitaxially grown monocrystalline silicon, but may be made of selectively grown polycrystalline silicon.

In addition, in order to flatten the element isolation region, BPSG9.1
2 is used, but the present invention is not limited thereto, and any insulating layer that can be reflowed may be used, for example, phosphor glass (PSG) or the like may be used.

Furthermore, the silicon oxide 11A3.11 may be an insulating film such as a silicon nitride film.

[Effects of the Invention] As described above, according to the present invention, the silicon layer and the silicon oxide film selectively formed on the upper side surface of the groove for isolating the elements of a semiconductor integrated circuit block the liquid to form a cavity. By doing so, it is possible to prevent the occurrence of stress in the semiconductor substrate around the groove, thereby improving device characteristics and yield.

In addition, the opening width of the trench is narrowed by a silicon layer and a silicon oxide film that are selectively formed on the upper side of the groove that isolates the elements of a semiconductor integrated circuit, and the narrowed opening is further closed with an insulating layer to fill the inside of the trench. By making it hollow,
It is possible to prevent the occurrence of stress in the semiconductor substrate around the groove, thereby improving device characteristics and yield.

Furthermore, by forming an insulating layer with a flat surface above the trench to flatten the element isolation region, it is possible to prevent breakage of the wiring layer formed on the element isolation region, thereby improving yield. I can do it.

[Brief explanation of the drawing]

1 is a process diagram showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention; FIG. 2 is a process diagram showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention; FIG. FIG. 4 is a process diagram showing a conventional method of manufacturing a semiconductor device and its problems. In the figure, 1... semiconductor substrate (silicon substrate), 2...
...Silicon oxide film, 3...Water for element isolation (U eraser), 4...
・Insulating layer (silicon oxide film), 5.6...Resist, 7.10...Silicon layer, 8.11...Insulating layer (silicon oxide H), 9 ．．
12...Insulating layer<BPSG).

Claims (1)

[Claims] 1. Forming a groove (3) for element isolation on a semiconductor substrate (1), and forming a first insulating layer (1) on the semiconductor substrate (1) inside the groove (3). 4), and selectively removing the first insulating layer (4) on the inside of the groove (3) to expose the semiconductor substrate (1); and the exposed semiconductor substrate (1). Silicon layer (7) on the substrate (1)
selectively growing to narrow the opening width of the groove (3); and forming a second insulating layer (8) on the silicon layer (7) to close the groove (3). A method for manufacturing a semiconductor device, comprising: 2. Forming a groove (3) for element isolation on the semiconductor substrate (1); Forming a first insulating layer (4) on the semiconductor substrate (1) inside the groove (3) selectively removing the first insulating layer (4) above the groove (3) to expose the semiconductor substrate (1); and forming a silicon layer on the exposed semiconductor substrate (1). (10
), a step of forming a second insulating layer (11) on the silicon layer (10), and a step of selectively growing a third insulating layer (12) on the second insulating layer (11). ) to close the groove (3).