JPH01311870A - High frequency inverter circuit - Google Patents

Abstract

PURPOSE:To inhibit the steep discharge from a capacitor by approachingly connecting a DC side power capacitor to bridge circuits for each phase of an inverter corresponding to the said power capacitor in dividing, and by holding the inductance portion mutually between terminals. CONSTITUTION:A DC side capacitor (power capacitor) 3 is divided into equal capacitors 3U and 3V on a U-phase side and a V-phase side. The terminals P and N of this capacitor 3U are approachingly connected to the terminals P and N of a phase-divided bridge circuit on the U-phase side respectively composed of an updown arm stack 1U and a snubber circuit 2U. The capacitor 3V is connected similarly. A distribution inductance 51 on the DC side of this inverter therefore becomes equivalent as before, so that the voltage duty of the switching transistor can be reduced. Further, the terminals P and N of each of capacitors 3U and 3V are connected respectively through a distribution inductances 52 of a suitable magnitude. The voltage rise caused by the added inductance component is absorbed by the power capacitor 3.

Description

[Detailed description of the invention] [Industrial application field]

This invention relates to a circuit on the DC side when a stack of upper and lower arms of the bridge is connected in multiple phases in a voltage source inverter circuit formed by bridge-connecting semiconductor switching means that perform high-frequency switching operations. The present invention relates to a high frequency inverter circuit that suppresses resonance during discharge of a capacitor and reduces generated noise. Note that in the following figures, the same reference numerals indicate the same or corresponding parts.

[Conventional technology]

FIG. 5 shows a circuit example of this type of inverter. In the figure, Ul, U2. Vl and V2 are switching transistors that constitute a so-called single-phase bridge circuit, and U
1 and U2 constitute the upper and lower arms of the tJ phase side, respectively, and Vl and V2 constitute the upper and lower arms of the ■ phase, respectively. These transistors 1 to 01 and U2 are each combined with a free-wheeling diode (also called FWD) D connected in antiparallel to itself to form a stack of one unit (
1 (NU), which is referred to as a phase-specific bridge circuit in the sense of an upper and lower arm stack or a half-bridge connection circuit of phase-specific switching transistors, is configured for convenience. Similarly, transistors Vl and V2 are also combined with FWDD connected in antiparallel to themselves to constitute upper and lower arm stack 1 (IV). The snubber circuit is connected between the P and N terminals, and each has a snubber capacitor C5 (C3υ, C3V). 3 is the power supply capacitor connected between the DC power supply, 4 is the upper part of the lower arm stack N, and the upper part of the IV. This is an AC load inserted between the connection points of the lower arm. In addition, 5 connects the P and N terminals of the power supply capacitor 3 to each P of the upper and lower arm stacks ItJ and IV, respectively. This is the wiring inductance as a stray inductance of the wiring connected to the N terminal. As described above, this inverter circuit has a structure in which the wiring inductance on the DC side is suppressed as much as possible, and this is a useful configuration that has the effect of satisfactorily lowering the voltage duty during operation of the switching transistor.

[Problem to be solved by the invention]

However, even in the inverter circuit shown in Fig. 5, when considering the discharge phenomenon of the overcharged snubber capacitor C8, it was found that there is an operation mode in which a larger discharge current flows, and this high-frequency discharge phenomenon is considered to be a noise source. This may adversely affect the environment around other electronic devices 3. The current path of the inverter operation that causes this is as shown in FIGS. 6 to 8. That is, FIG. 6 shows the path of the main circuit current in a mode (mode 1) in which the arms corresponding to Ul and Vl of the switching transistor serve as conductive paths. In this mode 1, the main circuit current flows in the direction of the arrow in the figure. Next, FIG. 7 shows the path of the main circuit current in mode 2 when the switching transistor U1 is turned off. In this mode 2, energy due to the wiring inductance 5 (5tlP) on the DC side through which the joint host circuit current was flowing flows into the snubber capacitor C5 (C3U), and the voltage increases. Normally, the snubber capacitor C3U starts discharging in this mode 2 state, and this capacitor voltage is balanced with the voltage value of the capacitor 3 on the DC side. However, in high frequency switching, mode 3 is a state in which the transistor V2 is turned on following the extinction of the transistor U1, that is, mode 3 is the state in which the snubber capacitor C5 is turned on due to the extinction of the transistor U1.
This occurs before U finishes discharging after charging. Figure 8 shows the operation in mode 3, where (A) shows the path of the main circuit current, and (B) shows the snubber capacitor C.
The path of the 5U discharge current is shown. That is, in this mode 3, the main circuit current flows in the direction of the arrow along the solid line path in FIG.
A short circuit current flows to extinguish the DD. When this triggers (sequentially) the discharging of the snubber capacitor CS[+ on the transistor Ul side to begin, a discharge current flows along the path shown in Figure 8 (B), resulting in a high-frequency resonant current. This causes noise interference. Therefore, an object of the present invention is to divide the power supply capacitor 3 on the DC side into two parts, the U-phase upper and lower arm stack side and the ■-phase upper and lower arm stack side, in a bridge-connected inverter circuit that performs high-frequency switching operations. By providing a method for configuring an inverter circuit that connects the P terminals and N terminals of the power supply capacitor 3 with wiring containing a significant inductance component, the inductance on the DC side that increases the voltage of the snubber capacitor during switching operation is increased. The object of the present invention is to suppress the rush current at the time of discharging the snubber capacitor 7 and prevent the above-mentioned noise interference.

[Means to solve the problem]

In order to solve the above problems, the inverter circuit of the present invention has a structure (such as IU, hereinafter referred to as upper and lower arms) formed by connecting two bridge arms in series, each including a semiconductor switching means (switching transistors Ul, U2, etc.). A snubber circuit (such as 2 [J) that includes at least a snubber capacitor (such as CSU) in parallel in a stack (called a stack)
A phase-specific bridge circuit as a parallel circuit is provided for each phase of the AC to be converted and output, and the positive (P) and negative (N) terminals as both ends of each phase-specific bridge circuit are respectively connected between the DC power sources. and extracts the AC of the phase corresponding to the upper and lower arm stacks from the connection point of the two bridge arms in each of the upper and lower arm stacks, a power supply capacitor (3) that stores the voltage of the DC power supply Such)
are provided for each of the above phases, and the positive (P) and negative (N) terminals of the power supply capacitors for each phase are connected to the positive and negative terminals of the corresponding phase-specific bridge circuit, respectively, and the □positive of each of the above power supply capacitors is It is assumed that the terminals and the negative terminals are connected to each other by a wiring including a significant inductance component (such as the wiring inductance 52).

[For use]

In this invention, the DC side power supply capacitors are arranged separately for each upper and lower arm stack, and the inductance on the DC side is minimized, and the P or N of each power supply capacitor is
The connecting wire between the terminals is configured to have enough inductance to set the maximum peak at the time of discharging the snubber capacitor to a desired value and to suppress high frequency resonance.

【Example】

Next, the present invention will be explained in detail based on FIGS. 1 to 4. FIG. 1 is a circuit diagram as an embodiment of the present invention, and corresponds to FIG. 5, and FIGS. 2 to 4 are operation explanatory diagrams of FIG. 1, and correspond to FIGS. 6 to 8, respectively. It is something. In Figure 1, the DC side capacitor (power supply capacitor)
3 is divided into the same capacitor 30°3V for each U phase and ■ phase, and the P and N terminals of this capacitor 3U are the P and N terminals of a phase bridge circuit for each U phase consisting of an upper and lower arm stack IU and a snubber circuit 2U, respectively. . Connected closely to the N terminal, and similarly connected to the P of the capacitor 3V.
, N terminals are also connected in close proximity to P and N terminals of a phase-specific bridge circuit consisting of an upper and lower arm stack IV and a snubber circuit 2v, respectively. Therefore, the wiring inductance on the DC side of this inverter (
In other words, the inductance (51) which serves as an energy source for charging the snubber capacitor C3 during operation of the switching transistor has a value equal to or less than that of the conventional example, and the voltage responsibility of the switching transistor is reduced. Further, the P terminal and N terminal of each power supply capacitor 3U, 3ν are connected to each other via a wiring inductance 52 of an appropriate size. FIGS. 2, 3, and 4A each show the same mode 1 as described above. Showing the main circuit current path in mode 2 and mode 3, in this case unlike the conventional case, the wiring inductance 52 is particularly included in the main circuit current path.
The energy stored in the wiring inductance 52 during mode switching is absorbed by the 30° 3V power supply capacitor as shown by the dotted line in Figure 4 (A), so there is no risk of increasing the voltage responsibility of the switching transistor. As described above, the voltage duty is rather reduced by reducing the DC side wiring inductance 51. In addition, in the discharge path of the snubber capacitor C3U in mode 3 shown in FIG. 4(B), the wiring inductance 52 newly included in this path is the main wiring inductance of the entire discharge path. It has a large size and can suppress high frequency resonance. Note that the wiring inductance 52 may be a stray inductance possessed by the wiring itself, or may be actively inserted as required, an acdle, or a saturable reactor. Furthermore, in the above embodiments, a so-called single-phase bridge-connected high-frequency inverter has been described, but in a multi-phase inverter connection such as a three-phase bridge inverter, the DC power supply capacitor is divided into phases, and the divided power supply capacitors are Connect the P and N terminals to the P and N terminals of each phase bridge circuit.
, and N terminals, and also connect the P terminals and N terminals of each power supply capacitor to each other with wiring having a wiring inductance 52, thereby making it possible to apply the present invention in the same manner.

【Effect of the invention】

According to this invention, the DC side power supply capacitor in a bridge-connected multiphase inverter is divided, each of the divided power supply capacitors is connected closer to each phase-specific bridge circuit of the corresponding inverter, and each of the divided power supply capacitors is Since an appropriate amount of inductance is provided between the P terminals and the N terminals of the power supply capacitor by wiring or adding a saturable reactor, steep discharge of the snubber capacitor can be suppressed. In addition, the voltage increase during switching due to the added inductance is absorbed by the power supply capacitor on the DC side, so the capacitance of the snubber capacitor does not increase.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram as an embodiment of the present invention, FIGS. 2 to 4 are current path diagrams for explaining the operation of FIG. 1, and FIG. 5 is a conventional circuit diagram corresponding to FIG. 1. 6 to 8 are current path diagrams for explaining the operation of FIG. 5, and correspond to FIGS. 2 to 4, respectively. ULU2. Vl, V2 Niswitching transistor D: Free wheeling diode (FWD), 1 (1 [
J, IV): Upper and lower arm stack, 2 (20,2ν
): Snubber circuit, csccsu, csv>'Snubber capacitor, 3 (3υ, 3V): Power supply capacitor,
4: Load, 51.52 N wiring inductance. 1. Lower arm stack rad 1 Figure 51 (5+UP) 1■ Fang Figure 5

Claims (1)

[Claims] 1) A snubber circuit including at least a snubber capacitor is connected in parallel to a structure formed by connecting two bridge arms in series (hereinafter referred to as an upper and lower arm stack) each including a semiconductor switching means, and A phase-specific bridge circuit as a parallel circuit is provided for each phase of the AC to be converted and output, and the positive and negative terminals as both ends of each phase-specific bridge circuit are respectively connected between the DC power supplies, and in each of the above upper and lower arm stacks. In a high frequency inverter circuit that extracts the alternating current of the phase corresponding to the upper and lower arm stacks from the connection point of the two bridge arms, a power supply capacitor for storing the voltage of the direct current power supply is provided for each of the phases, and a power supply capacitor for each phase is provided. The positive and negative terminals of the power supply capacitors are connected to the positive and negative terminals of the corresponding phase-separated bridge circuit, respectively, and the positive terminals and negative terminals of each of the power supply capacitors are connected to each other by wiring containing a significant inductance component, A high frequency inverter circuit characterized by: