JPH01305555A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and relates to a technique that is effective for use in, for example, a digital processing device including a static RAM (random access memory). be.

[Conventional technology]

As an example of a semiconductor integrated circuit device consisting of a memory circuit and a logic circuit, Nikkei McGraw-Hill, September 9, 1985,
"Nikkei Electronics" pages 165 to 192. This document describes a standard cell type LSI (Large-Scale Semiconductor Integrated Circuit).

[Problem to be solved by the invention]

As mentioned above, in S I, power supply voltage lines and ground lines are alternately arranged in parallel so as to be adjacent to each other,
A circuit cell is provided there. When the RAM is provided as one circuit block, high integration is possible by configuring it as one large building block.

However, when the RAM is configured integrally with the logic circuit, in other words, when the RAM is configured within the arithmetic unit so as to store information bits operated on with the arithmetic circuit or the operation results, It is necessary to place it adjacent to the RAM and logic circuit. Generally speaking, circuit cells constituting a logic circuit are required to have relatively complex circuit functions, so they are relatively large cells. Therefore, as shown in FIG. 4, the circuit cell L on the logic section I-OC side
C has a relatively large circuit scale, and the interval between the power supply voltage line Vcc and the circuit ground line GND is set accordingly. On the other hand, in the RAM section, memory cells MC are 2
・One CMOS inverter circuit and two transmission gate MOs
It is composed of a small number of elements such as a total of six MOSFETs (insulated gate field effect transistors) like SFET, and the size of each element is relatively small because it performs the function of storing information. Therefore, the interval between the power supply voltage Vcc and the ground line (7ND) becomes wider than necessary, resulting in wasted space on the semiconductor substrate.Also, when increasing the storage capacity, the distance between the power supply voltage Vcc and the ground line (7ND) is increased. The number of memory cells to be increased LT-,
, 9 ma 0゛ ・+ 目 目 市 ida ′ line 0 d° The capacitance is increased and the operating speed is slowed down.

An object of the invention is to provide a semiconductor integrated circuit device in which a RAM section and a logic section are highly integrated and are arranged in close relation to each other.

Another object of the present invention is to provide a semiconductor integrated circuit device having a RAM section that achieves high integration and high speed.

The above-mentioned and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, in an area where circuit cells with a relatively large circuit size constituting a logic section are arranged, the electric B voltage line and the ground line are alternately placed adjacent to each other at intervals corresponding to the size of the circuit cell. In the area where the memory cells constituting the RAM section are arranged in parallel, the above power supply voltage line (or ground line) is branched to have an interval half that of the adjacent ground line (or power supply voltage line). Extend it parallelly so that
A ground line (or power supply line) is placed on an extension of the branched power supply voltage line (or ground line) to the branch point, thereby halving the distance between the power supply voltage line and the ground line.

[For production]

According to the above-mentioned means, since the distance between the power supply voltage line that supplies operating voltage to the memory cells constituting the RAM section and the ground line can be reduced, the memory cells are highly integrated and arranged adjacent to the logic circuit. can do.

〔Example〕

FIG. 1 shows a layout diagram of an embodiment of a logic section and a RAM section in a semiconductor integrated circuit device according to the present invention. Although each circuit block and element in the figure is not particularly limited by known semiconductor integrated circuit manufacturing technology,
It is formed on a single semiconductor substrate such as single crystal silicon.

The logic section LOG is composed of a plurality of logic gate circuits that constitute a 1-bit arithmetic circuit, although this is not particularly limited. Therefore, the height of the circuit cells constituting the logic gate circuit is made relatively high.

Corresponding to this height, the power supply voltage line Vcc and the ground line GND are alternately arranged in parallel so as to be adjacent to each other with a relatively large interval. By configuring the circuit cell in the region sandwiched between the power supply line Vcc and the ground line GND, which are arranged in parallel in this way, the operating voltage is supplied to the circuit cell.

An R'AM section is provided corresponding to each of the arithmetic circuits described above to store the arithmetic data and results thereof.

In this embodiment, the arrangement of the ground line GND and the power supply voltage line VCC is changed as follows in order to arrange the memory cells M'C in a matrix arrangement constituting the RAM section at a high density.

Although not particularly specified, the ground line GND branches vertically at the boundary with the RAM section, and is extended parallel to the vertically adjacent power supply voltage line Vcc from a point that is half the distance shown in the figure. Ru. A power supply voltage line Vcc is placed on an extension of the branch point of the ground line GND, as will be described later. As a result, in the area where the memory cells of the RA and M sections are arranged, the power supply voltage line Vcc and the ground line GND are alternately parallel to each other so that they are adjacent to each other with half the interval of the logic section OG. will be placed in The memory cell MC is arranged in a region sandwiched between the power supply line Vcc and the ground line GN-D, which are arranged in parallel, and its operating voltage is supplied thereto.

As shown in FIG. 2, the memory cell MC includes a latch circuit consisting of a pair of CMOS inverter circuits N1 and N2 whose inputs and outputs are cross-connected to each other, a pair of inputs and outputs of this launch circuit, and a complementary data line. On the other hand, the transmission gate 1-M03FETQ5. Consists of Q6. The above CMOS inverter circuit N3. N4 are P-channel MOSFET and N-channel MOS, respectively.
It is composed of FET. Therefore, memory cell MC is
It consists of a small number of elements, six MOS FETs in total, and because it simply performs a storage operation, the element size is relatively small. As a result, the area occupied by one memory cell MC becomes smaller, and as the distance between the power supply voltage line Vcc and the ground line GND is narrowed,
It becomes possible to mount a large number of memory cells at high density.

Then, one row (bit) of the logic part LOG is
Looking at this, two rows are constructed in the RAM section. In other words, in the RAM section, memory cells are arranged in two rows iJ. Therefore, if the storage capacity is the same, R
The number of memory cells MC arranged in one row of the AM section can be reduced by half. That is, the memory array is
A configuration is adopted in which complementary data lines are arranged in the horizontal direction corresponding to the above-mentioned rows, and word lines W1 to W3, etc. are arranged in the vertical direction. In this case, the parasitic capacitance of the complementary data line can also be reduced as the number of memory cells MC coupled to the complementary data line is halved.

This reduces the parasitic capacitance that acts as a load during writing/reading, and enables high-speed writing/reading.

As described above, two rows (2 bits) of memory cells MC are arranged in the RAM section for the height of one row (1 bit) of the logic section LOG. Therefore, in order to establish a one-to-one correspondence with the logic section LOG, the write/read circuit of the memory cell MC is configured as follows.

In the figure, to explain the most significant row, the divided upper non-inverted complementary data line D11 is coupled to the read terminal RDI via the clocked inverter circuit CNI. Divided lower non-inverted complementary data line D
I2 is coupled to the read terminal RDI via a clocked inverter circuit CN2. The clocked inverter circuits CNI and CN2 are operated in a complementary manner by complementary clock pulses CK and CK generated corresponding to addresses assigned to the upper and lower complementary data lines. Depending on the noise, the upper or lower complementary data line is selected, and the memory cell whose word line has been selected is read.

A write signal supplied from the write terminal WDI is converted into a complementary write signal by inverter circuits N1 and N2. The output signal of the inverter circuit N1 is transmitted to the non-inverting complementary data line Dll on the first side via the transmission gate MOSFET QI, and to the lower non-inverting complementary data line D12 via the transmission gate MOSFET Q4. The output signal is sent to the upper inverted complementary data line Dll via transmission gate 1-M03FETQ2,
Lower inverted complementary data line D12 via OSFETQ3
can be conveyed to.

The transmission gate MOSFETs QI and Q2 are paired, and a write signal WH for selecting the upper complementary data line D11°Dll is supplied to their gates, and the transmission gate MOSFETs 1-M03F
ETQ3 and Q4 are paired and have their gates connected to lower complementary data lines D12. A write signal WL that selects D1.2 is supplied. Thereby, the write signal supplied from the write terminal WD1 is the selection signal WH or Wl.
- and the word line to be written into one memory cell MC.

The above-mentioned read circuit and write circuit are connected to the read terminals RD2 . RD3
etc., and write terminal WD2. The same applies to WD3 and the like. Such a read/write circuit connects the power supply line Vcc and the ground line GND similarly to the logic section LOG.
is formed in the area where the original spacing has been restored.

FIG. 3 shows a layout diagram showing an embodiment of the power supply voltage line Vcc, the ground line GND, and each circuit cell corresponding thereto.

In the RAM section, the power supply voltage line Vcc arranged on the extension of the branch point of the ground line GND is not particularly limited, but
The upper power supply line Vcc extends downward and is connected to the boundary between the RAM section and the logic section 50G on the right side. Then, the lower ground line GND branched at the RAM section extends upward at the boundary and is placed on the extension line before branching. As a result, the power supply voltage line Vcc on the right side of the RAM section
The distance between the ground line GND and the ground line GND can be made relatively large.

Figure 3 is effective for the process of the aluminum wiring ALI layer, but the aluminum wiring ALL layer and aluminum 1
The following method is used for a multilayer wiring process consisting of two layers of aluminum wiring AL and the like.

The ground lines GND branched off in the RAM section are merged into one line again at the logic section LOG. At this time, the power supply voltage line CC, which is placed on the extension line of the branch point of the ground line GND, is connected to the first layer by the second layer aluminum wirings A1 and 2 extending in the vertical direction shown by the dotted line in FIG. Aluminum wiring A L
1 power supply voltage line Vcc. As a result, the first
The distance between the power supply voltage Vcc of the aluminum wiring ALL of the layer and the ground line GND can be returned to the original size. In this case, the electric B voltage line V consists of the first layer aluminum wiring ALL arranged in parallel on the extension line of the grounding line GND.
Unlike the figure, cc terminates at both left and right ends.

The read/write circuit as described above consists of one circuit cell 1. of the logic section on the right side. It is configured as C.

Therefore, the RAM section should be understood as a region where memory cells forming a memory circuit are arranged. Although not shown, the word line selection circuit that forms selection signals such as words &l'l to W3 in FIG. 1 is also provided with a unit circuit consisting of relatively large circuit cells similar to the logic section LOG. .

The effects obtained from the above examples are as follows. In other words, (1) In the area where circuit cells with a relatively large circuit scale constituting the logic section are arranged, the power supply voltage line and the ground line should be adjacent to each other at intervals corresponding to the size of the circuit cell. The ground lines are arranged alternately in parallel, and in the area where the memory cells constituting the RAM section are arranged, the ground lines are branched and extended parallel to each other so as to be half the distance from the adjacent power supply voltage lines. However, by arranging the power supply line on the extension corresponding to the branch point of the branched ground line, the interval between the power supply voltage line and the ground line is halved. With this configuration, the distance between the power supply voltage line that supplies operating voltage to the memory cells constituting the RAM section and the ground line can be reduced, making it possible to arrange highly integrated memory cells adjacent to the logic circuit. You can get the effect that you can.

(2) According to (1) above, in the RAM section, memory cells are arranged in two rows, so if you want to obtain the same storage capacity as in the conventional technology as shown in Figure 4, a power supply consisting of a pair is required. The number of memory cells MC coupled to complementary data lines extending parallel to the line can be reduced by half. As a result, the parasitic capacitance of the complementary data line to which the memory cells are coupled is also reduced by half, resulting in the effect that memory access can be performed at high speed.

Although the invention made by the present inventor has been specifically explained based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the wiring to be branched may be the electric f1. A configuration may be adopted in which the voltage line Vcc is branched. That is, in FIG. 1 or 3, the power supply voltage line Vcc and the circuit ground line G
The configuration may be such that the NDs are replaced with each other.

The circuit cells constituting the logic section may be anything other than an arithmetic circuit, such as those that perform predetermined information processing operations.

Further, the memory cells constituting the RAM section may use the CMOS inverter circuit as described above, or may have a structure in which the P-channel MOSFET of the CMOS inverter circuit is replaced with a high resistance element made of a polysilicon layer.

The present invention can be widely used in semiconductor integrated circuit devices including a RAM for storing data bits processed by circuit units for various calculations, etc.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, in an area where circuit cells with a relatively large circuit scale constituting a logic section are arranged, power supply voltage lines and ground lines are arranged in parallel and adjacent to each other at intervals corresponding to the size of the circuit cells. In the area where the memory cells constituting the RAM section are arranged, the ground line is branched and extended parallel to the adjacent power supply voltage line so as to be half the distance from the adjacent power supply voltage line. By arranging the power supply line on the extension corresponding to the branch point of the branched ground line, the interval between the power supply voltage line and the ground line is halved. With this configuration, it is possible to reduce the distance between the power supply voltage line that supplies operating voltage to the memory cells that make up the RAM section and the ground line, allowing for high integration of memory cells placed adjacent to the logic circuit. become.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific embodiment of the memory cell, and FIG. 3 is an example of the arrangement of power supply voltage lines and ground lines. Layout Diagram Showing Embodiment FIG. 4 is a layout diagram illustrating an example of the prior art. LOG...logic circuit section, RAM...RAM section, MC...
・Memory cell, LC...logic circuit cell, Vcc...voltage line, GND...ground line, CN1, CN2...clocked inverter circuit, Nl-N4...CMOS inverter circuit

Claims (1)

[Scope of Claims] 1. In a region where circuit cells with a relatively large circuit size constituting a logic section are arranged, power supply voltage lines and ground lines are adjacent to each other at intervals corresponding to the size of the circuit cells. In the area where the memory cells constituting the RAM section are arranged, the power supply voltage lines or ground lines are branched at half intervals with respect to the adjacent ground lines or power supply voltage lines. The distance between the power supply voltage line and the ground line is halved by placing the ground line or power supply line on the extension of the branched power supply voltage line or ground line from the branch point. A semiconductor integrated circuit device characterized by: 2. The memory cell includes a latch circuit consisting of a pair of CMOS inverter circuits whose inputs and outputs are cross-connected to each other, and a pair of transmission gates provided between the pair of inputs and outputs and a pair of complementary data lines. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a static type memory cell composed of a MOSFET. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the logic section constitutes an arithmetic circuit, and the RAM section stores data to be processed.