JPH01303921A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent a power voltage fed externally from being applied directly between a source and a drain of an N-MOS transistor(TR) used in a bipolar MOS integrated circuit device by adding a power voltage level conversion circuit to the said integrated circuit. CONSTITUTION:A bipolar TR and a MOS TR are formed on one and same chip. Then the bipolar MOS TR circuit is connected to an external power supply via a level shift diode 3. Thus, the power voltage of 3 sets of P-MOS TRs 4-6 and N-MOS TRs 7-9 is reduced and the voltage applied between the source and drain of the N-MOS TRs 7-9 is made smaller than the power voltage VDD supplied externally. Moreover, the voltage applied between the source and drain of the N-MOS TR 10 is also decreased more than the power voltage VDD supplied externally by the level shift diode 3.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to supplying a power supply voltage to a so-called B1-MO3 integrated circuit in which a bipolar transistor and a MOS (MOS) radiator are mixed in the same chip. The present invention relates to a semiconductor integrated circuit device.

[Conventional technology]

Conventionally, many B i -MO3 integrated circuit devices of this type have been used for output buffer basic circuits, internal logic gate circuits, and the like.

FIG. 4 is an output buffer circuit diagram for explaining an example of such a conventional device.

As shown in Figure 4, this output buffer circuit outputs a low level signal to output terminal 2 when a high level signal is input to input terminal 1, and conversely, when a low level signal is input to input terminal 1. The logic of the inverter is realized in which a high level is output to the output terminal 2 when the voltage is off.

Looking at this in terms of circuit elements, when a low level signal is input to input terminal 1, P-channel MOS) transistors (hereinafter referred to as P-MOS) transistors 4 and 5 are turned off.
N-channel MOS transistor (hereinafter referred to as N-MO
S) 7.8 (referred to as transistor) turns OFF. At this time,
Since the base current is supplied to the NPN Schottky transistor 12, it is turned on. On the other hand, since the P-MO9)-rangistaro is 0FFL and the N-MO8) transistor 9.10 is turned on, the NPN Schottky transistor 11 has its base current turned on. is not supplied, so it turns OFF.

Further, since the NPN Schottky transistor 13 is not supplied with its base current, it is turned off, and a high level is output to the output terminal 2 formed by the totem pole of the NPN Schottky transistors 12 and 13. At this time, N-MO3) Langistav, 8 is ■. The P-MO transistors 4 and 5 clamp the voltage obtained by subtracting the voltage drop due to the ON resistance from the D power supply voltage, and the N-MOS transistors 9 and 10 accumulate the voltage at the bases of the NPN Schottky transistors 11 and 12, respectively. A current flows when the accumulated charge is extracted. That is, N-M
There are times when a voltage close to the power supply voltage value supplied from the outside is applied between the source and drain of the OS transistors 7.8.9.

On the other hand, when a high level signal is input to input terminal 1, P-MOS) transistor 4.5 is set to 0FFL, N-
MOS transistor 7.8 is turned on. At this time, NPN
The Schottky transistor 12 is turned off because its base current is not supplied. In addition, the P-MOS) transistor is ONL, and the N-MOS transistors 9 and 10
By turning off, the base current of the NPN Schottky transistor 11 is supplied. When this NPN Schottky transistor 11 is turned on, the NPN Schottky transistor 13 is supplied with its base current, so that the NPN Schottky transistor 12 and NP
A low level is output to the output terminal 2 which is configured as a totem pole with the N Schottky transistor 13. At this time, the N-MOS) transistor 9 changes from the VDD power supply voltage to the P
-MOS) The voltage after subtracting the voltage drop due to the ON resistance of the transistor is clamped, and the N-MOS transistors 7 and 8 are respectively connected to the P-MOS transistors 6 and N-
A current flows when drawing out the gate charge of the MOS) radiator 9 and the base charge of the NPN Schottky transistor 12. Note that the diode 23 connected between the output terminal 2 and the NPN Schottky transistor 12 is a diode for adjusting the output level. That is, there are times when a voltage close to the power supply voltage value supplied from the outside is applied between the source and drain of the N-MOS transistor.

Figure 5 shows BiCMO8$ for explaining another conventional example.
FIG. 2 is a circuit diagram of an internal logic gate used in one circuit.

As shown in FIG. 5, when a high level signal is input to the input terminal 1, this internal logic gate circuit outputs the signal to the output terminal 2.
This realizes an inverter logic in which a low level signal is output to the input terminal 1 and, conversely, a high level signal is output to the output terminal 2 when a low level signal is input to the input terminal 1.

Looking at this in terms of circuit elements, when a low level signal is input to input terminal 1, P-MOS transistor 15 is turned on and N-MOS transistors 16 and 17 are turned off.
PN) transistor 19 is turned off, and a high level is output to output terminal 2 which is configured as a totem pole with NPN transistors 18 and 19. At this time, the N-MOS transistor 16 clamps the voltage obtained by subtracting the voltage drop due to the ON resistance of the P-MOS transistor 15 from the power supply voltage VDD supplied from the outside, and the N-MOS transistor 17 clamps the voltage obtained by subtracting the voltage drop due to the ON resistance of the P-MOS transistor 15. from the power supply voltage VDD to NPN
A voltage obtained by subtracting the base-emitter forward voltage of the transistor 18 and the ON resistance of the P-MOS transistor 15 is clamped.

On the other hand, when a high level signal is input to the input terminal 1, the P-MO3 transistor 15 is turned off and the N-MOS transistor 16.17 is turned on, so the NPN transistor 18 is turned off and the NPN transistor 19 is turned on.
,,NPN) A low level is output to the output terminal 2 which is configured as a totem pole with transistors 18 and 19. At this time, a current flows between the source and drain of the N-MOS transistor 16 to draw out the base charge of the NPN transistor 18, and when a voltage close to the power supply voltage DD supplied from the outside is applied. There is.

[Problem to be solved by the invention]

The conventional B1-MOS semiconductor integrated circuit device described above is
The power supply voltage (Voo) supplied almost externally between the source and drain of the N-MOS transistor used in the circuit.
A voltage equal to is applied.

However, if the gate length and channel impurity concentration of an N-MOS transistor are reduced according to the so-called scaling law while keeping the power supply voltage constant, reliability problems such as the generation of hot electrons due to an increase in the electric field between the source and drain will occur. Also, problems such as a reduction in source-to-train breakdown voltage occur.

Therefore, reducing the power supply voltage will solve the above problem to a certain extent, but this will have the disadvantage that it will not be possible to standardize the power supply voltage with other semiconductor integrated circuit devices, and the circuit design will be dependent on the power supply voltage. There is a drawback that the output voltage level, which is large, does not match with other semiconductor integrated circuit devices, and in any case, problems arise in device design.

An object of the present invention is to provide a semiconductor integrated circuit device that can standardize power supply voltages with other semiconductor devices and easily match output voltage levels.

[Means to solve the problem]

The semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device that realizes various circuits using both bipolar transistors and MOS transistors formed on the same chip, in which a Bi-MOS transistor is used as a level shifter. The N-channel MOS transistor is connected to an external power supply via the N-channel MOS transistor, and is configured such that a voltage lower than the external power supply voltage is applied between the source and drain of the N-channel MOS transistor during any operation.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is B 1 for explaining the first embodiment of the present invention.
- It is an output buffer circuit diagram in a MOS semiconductor integrated circuit device.

As shown in FIG. 1, compared to the conventional output buffer circuit explained in FIG. 4, the output buffer circuit of this embodiment has an upper limit in circuit configuration due to the addition of level shifting diodes 3 at various locations. ing.

Regarding this output and its operating principle as a buffer circuit,
Although it is similar to the conventional output buffer circuit, by adding the level shift diode 3, the P-M
OS) - Transistor 4 and N-MOS Transistor 7, P-MOS) Transistor 5 and N-MOS) Transistor 8, P-MOS) Transistor and N-MO
The power supply voltage of the three sets of inverter circuits each composed of an S transistor is lowered, and the voltage applied between the source and drain of the N-MOS transistor is lower than the power supply voltage VDD supplied from the outside. becomes smaller. Further, the voltage applied between the source and drain of the N-MOS transistor 10 is also lower than the power supply voltage vDD supplied from the outside by the level shift diode 3.

On the other hand, NPN determines the low level potential of output terminal 2.
The voltage VBE between the base and emitter of the Schottky transistor 13 and the forward voltage VP of the Schottky diode built between the base and collector of the NPN Schottky transistor 13 determine the high level potential of the output terminal 2. is the ON state of P-MOS transistor 5
The resistor and the base of the NPN Schottky transistor 12
Since the inter-emitter forward voltage Vng and the forward voltage VF of the resistor 35 and the diode are the same, none of these levels are affected by the level shift diode 3.

FIG. 2 shows Bi-
FIG. 2 is an internal logic gate circuit diagram in a MOS semiconductor integrated circuit device.

As shown in FIG. 2, compared to the conventional internal logic gate circuit explained in FIG. 5, the internal logic gate circuit of this embodiment has a diode 3 for level shifting in its circuit configuration. ing.

That is, N-Mo used within the internal logic gate circuit.
3) A voltage lower than the externally supplied power supply voltage VD+) is applied between the source and drain of the transistors 16 and 17. Furthermore, since the output of this internal logic gate circuit is received by another similar internal logic gate or the CMOS gate of the output buffer, by inserting the level shift diode 3, the logic amplitude can be reduced by 2 to 3 μm. Even if the degree decreases, it will not be a problem.

Furthermore, since the large-scale buffer has an input level conversion circuit connected to the input of the internal logic gate circuit, the power supply voltage VH supplied from the outside is only used to power the input level conversion circuit section.
A similar effect can be achieved using .

In addition, by connecting a plurality of level shift diodes 3 in series, the source of the N-Mo3h transistor
It is also possible to adjust the voltage applied between the input terminal and the input terminal by yA.

FIG. 3 is a circuit configuration diagram in which a plurality of internal logic gate circuits are connected for explaining a third embodiment of the present invention.

As shown in FIG. 3, the internal logic gate circuit 21 is circuit-wise completely equivalent to the second embodiment described above;
The level shift diode 3 supplies a voltage lower than the externally supplied power supply voltage VDD to the power supply line (vDn) 22, and the power supply line 22 supplies a large number of internal logic gate circuits li! 821 with a voltage lower than the power supply voltage VDD.

For example, when this level shift means is applied to a Bi-MO3 semiconductor integrated circuit in which a large number of basic cells such as a gate array are arranged in an array, there is an advantage that only a small number of level shift diodes 3 are required.

Moreover, since the level shift diode 3 is not required in the basic cell, the area of the basic cell can be reduced, and there is an advantage that a B1-MO3 semiconductor integrated circuit device with a smaller chip area can be realized.

In the above explanation, the semiconductor integrated circuit that is compatible with TTL input/output levels has been mainly explained as an example, but the present invention can also be applied to semiconductor integrated logic circuits that are compatible with other input/output levels, analog integrated circuits, etc. . Moreover, although the above-mentioned example has been explained using a circuit showing inverter logic as an example, similar results can be obtained with other logics such as NAND and NOR.

〔Effect of the invention〕

As explained above, the semiconductor integrated circuit device of the present invention includes
By adding a power supply voltage level conversion circuit to the Bi-MO3 integrated circuit device, the N-M
This has the effect of preventing the power supply voltage VOO supplied from the outside from being directly applied between the source and drain of the OS transistor, and suppressing the hot electron effect and short channel effect. Therefore, according to the present invention, even if an N-Mo5)-transistor in the submicron region is used, the current standard power supply voltage of about 5 V may be used, and the input/output level may be the same as the current level.

[Brief explanation of the drawing]

FIG. 1 is an output buffer circuit diagram of a semiconductor integrated circuit device for explaining a first embodiment of the present invention, and FIG. 2 is an internal diagram of a semiconductor integrated circuit device for explaining a second embodiment of the present invention. 3 is a circuit diagram of the internal logic gate of the same device for explaining the third embodiment of the present invention, and FIG. 4 is a circuit diagram of the output buffer for explaining the conventional example. Circuit Diagram: FIG. 5 is a circuit diagram of a square internal logic gate illustrating another conventional example. 1...Input terminal, 2...Output terminal, 3...Level shift diode, 4-6, 15...P-Mo8)
-Ran resistor, 7-10, 16.17...N-Mo5
To t transistor, 11-13... NPN Schottky transistor, 14.20... resistor, 1.8.19.
... NPN transistor, 21... Internal logic gate circuit, 22... Power supply line lower than the power supply voltage. −
・l'

Claims (1)

[Claims] In a semiconductor integrated circuit device that realizes various circuits using both bipolar transistors and MOS transistors formed on the same chip, the Bi-MOS transistor circuit is connected to an external power supply via a level shift means, and when 1. A semiconductor integrated circuit device characterized in that a voltage lower than an external power supply voltage is applied between the source and drain of an N-channel MOS transistor even during operation.