JPH01295590A - Recording and reproducing system and solid-state image pickup device - Google Patents

Abstract

PURPOSE:To prevent a false color signal in the vertical direction by recording plural color signals obtained from an image pickup element onto plural adjacent tracks of a recorder and synthesizing signals obtained from the plural at reproduction so as to form a video signal. CONSTITUTION:Each picture element signal obtained by a photodetector section 201a of a CCD 201 is read in a prescribed order independently for each signal of R, G, B by a storage section 201b and a horizontal transfer resister 201c. Then a prescribed synchronizing signal Sy is added to a horizontal/vertical blanking period by adder circuits 208a, 208b, 208c. Then prescribed pre-enphasis and FM modulation or the like are applied and the result is outputted as FM-R, FM-G, FM-B signals. Thus, the resolution of a color component is high and a false color signal in the vertical direction hardly takes place.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a recording/reproducing system for recording (or transmitting) still images and a solid-state imaging device suitable for this system.

[Prior Art] A still video device (hereinafter referred to as Sv) is conventionally known as a device for recording and reproducing still images.

SV is a system in which a video signal obtained by a solid-state imaging device or the like is FM modulated, recorded on a small magnetic disk called a video floppy, and reproduced.

FIG. 12 shows the recording frequency allocation of Sv.

In FIG. 12, FM-Y is an FM-modulated luminance signal, and FM-C is an FM-modulated color-difference line sequential signal (R-
Y/B-Y). Note that the center carrier frequencies of RY and B-Y during FM modulation are different, 1.2 MHz and 1.3 MHz, respectively. Since Sv has a recording frequency allocation as shown in Figure 12,
The baseband bands of Y and RY/B-Y are limited to 4.5 MHz and I MH2, respectively.

[Problems to be Solved by the Invention] Therefore, the current Sv has drawbacks such as low resolution of color components and false colors appearing in the vertical direction due to color difference line sequential recording.

In particular, since images printed with Sv can be compared with prints of silver halide photographs, this drawback can be said to be very large. It is an object of the present invention to provide a recording/reproducing system for solving such drawbacks of Sv, and a solid-state imaging device suitable for such a system.

[Means for Solving the Problems] In order to achieve such an object, the recording and reproducing system of the first invention of the present application transmits a plurality of color signals obtained from an image sensor to a plurality of adjacent tracks of a recording device. A video signal is formed by combining the signals obtained from the plurality of tracks during recording and reproduction.

Further, a second invention of the present application is a solid-state imaging device in which pixels are arranged in row and column directions, and includes row selection means for selecting a predetermined row and selecting mutually different pixels in the selected row. have

[Operation] According to the first invention of the present application, since a plurality of color signals are recorded and reproduced, color signals in a high f range can be recorded and reproduced, and false color signals in the vertical direction can be prevented.

Further, according to the second invention of the present application, different pixels in a predetermined row can be selectively read out, so sequential recording of each color signal becomes possible, and the recording/reproducing system can be simplified.

[Embodiment] FIG. 1 shows the configuration of an RGB recording type electronic still camera (hereinafter referred to as an RGB-3V camera) according to a first embodiment of the present invention. In FIG. 1, 201 is a frame having an R-G-B stripe color filter. Transfer type ccD.

209 (a), 209 (b), and 209 (c) are recording signal processing circuits for R signal, G signal, and B signal, respectively, and 212 (a), 212 (b).

212(C) is a chi head for R signal.

ch2 head for G signal, ch3 head for B signal.

It is.

In FIG. 1, when the trigger button (not shown) is pressed, the shutter (not shown) is activated to
), photoelectric conversion is performed for a predetermined time, and each pixel signal obtained thereby is independently converted to a predetermined value for each R, G, and B signal by the storage section 201 (b) and the horizontal transfer register 201 (c). are read in this order. 206 (a)
, 206(b), and 206(c) sample and hold each of these R, G, and B pixel signals, respectively. The R-G-B signals are then converted to 207 (a) and 207 (b).

208 (C), becomes an analog signal in a predetermined band by LPF, 208 (a), 208 (b), 20
8(c), a predetermined synchronizing signal sy is added to the horizontal and vertical blanking sections. Note that the synchronization signal Sy here is obtained by counting down the internal clock fc of the CCD drive circuit 202 in the synchronization signal generation circuit 204. 209 (a), 209
(b).

209 (c), R obtained as above,
G, B, and G signals are subjected to predetermined signal emphasis and FM modulation, respectively, to produce FM-R, FM-G, and FM signals.
-B, output as a signal. 210 (a), 210
(b) and 210 (C), the reference clocks f and r (sine waves) for time axis correction during reproduction are F M
-R.

Add to each of FM-G and FM-B.

(fr is the 1/N frequency divider 203 of the aforementioned clock fc.
It is obtained by dividing the frequency by 1/N and extracting the fundamental wave component using the BPF 205. ) and FM-R, FM-G,
FM-B, respectively 211 (a) and 211 (b
), 211 (c), passes through the recording amplifier 212 (
It is recorded on a 213 video floppy by a), ch-1 head, 212(b) ah-2 head, and 212(c) ah-3 head.

Note that FIG. 2 shows the recording frequency allocation at this time.

Next, a case will be described in which an image recorded in this manner is reproduced.

FIG. 3 shows an example of the configuration of an RGB-3V reproducing device. 41
3(a) to (b) are Ch-1 head and Ch-1 head, respectively.
404 is a reproduction signal processing circuit for performing FM demodulation and predetermined de-emphasis, etc., and 408 is an image memory for three screens of R, G, and B. c of 413(a) to (c) in Figure 3
h-1, ch-2, ch-3 heads.

and FM-R recorded on video and floppy disks using preamplifiers 401 (a) to (C).

Play FM-G and FM-B. In the switch circuit S1, one type of signal is selected from among these, passes through the HPF 402, and is manually inputted to the reproduction signal processing circuit 404.

In the reproduced signal processing circuit 404, FM demodulation, predetermined de-emphasis, etc. are performed. The R, G, or B signal demodulated in this way is converted into a digital signal by an A/D converter 406, passes through a switch S2 operating in conjunction with a switch St, and is stored in an image memory 408.
is written to a predetermined address area within.

At this time, the operating clock of the A/D converter 406 is the same as the write clock input to the memory controller 409, and fr is extracted from the reproduced RF signal by the BPF 403 and this fr is sent to the write clock generator 40.
It can be obtained by entering 5. The write clock generator 405 generates a clock having a certain frequency relationship (for example, N times fr) and a certain phase relationship with the manually input signal fr using a PLL or clock injection locking method. In other words, a clock is created that follows the fluctuations in the time axis of the reproduced signal.

The R, G, B signals recorded on the video floppy 412 as described above are played back in order, and the image memory 412
Written within 08. When the above operations are completed, the memory controller 409 puts the image memory 408 into the read mode, and uses the Read clock input from the reference clock generator 407 to read the RGB image data at T.
Output according to the operating procedure of the V signal.

The digital RGB signals output in this way are
411 (a) and 411 (b), respectively.

411(c) into an analog signal and output as a reproduced RGB signal.

Furthermore, the synchronization signal generator 410 generates a synchronization signal from the reference clock manually input from the reference clock generator 407, and outputs it as a synchronization signal for the reproduced R, G, and B signals.

The RGB-3V playback device has been described above. According to such a recording and reproducing system, the resolution of color components is high, and false color signals in the vertical direction are less likely to occur.

Note that in the RGB-3V camera as described above, the order in which pixel data is read from the solid-state image sensor (frame, transfer CCD) cannot be determined freely due to the structure of the solid-state image sensor.

It is necessary to record three types of B signals simultaneously. Therefore, the RGB-3V camera of the first embodiment requires three recording signal processing circuits, three recording amplifiers, and three recording heads, as shown in FIG.

In order to improve this, a method may be adopted in which each image signal read from the solid-state image sensor is temporarily recorded in a memory, and the recording by the LCH head is repeated three times.

Next, FIG. 4 shows a configuration example of another image sensor suitable for the configuration shown in the first diagram.

This device uses an n-channel junction EET as a source.
Operates as a follower and connects the gate with capacitor C6
The structure connected to the address line is taken as one pixel, and this is arranged.

FIG. 4(a) is a top view of one pixel of this image sensor, and FIG. 4(b) is a cross-sectional view thereof. One pixel in this image sensor corresponds to one junction FET, and in FIGS. 4(a) and 4(b), 501 is the drain, 50
2 is a gate, and 503 is a source. The 505 horizontal selection polysilicon electrode covers a part of the 502 gate with the 504 silicon oxide film sandwiched therebetween.
A capacitance CO is generated between the gate 502 and the gate 502. Further, the polysilicon electrode 506 for signal readout is connected to the 503 source.

FIG. 5 shows an equivalent circuit for explaining the basic operation of this image sensor.

In FIG. 5, Ql, Q2. Q3. Q4゜Q5. Q6.
... etc. are junction type FETs each corresponding to one pixel.
It is. Junction type FE existing in the same column in Fig. 5
The sources of Q1, Q8 .T are connected by the same polysilicon electrode as shown in FIG.・
... etc. is connected to the drain. Therefore, Ql, Q
8. If a transistor such as... is ONL/Ql.

Q8. ... becomes a constant current source, and the junction type F of each pixel
ET will act as a source follower.

In addition, the gate part of the junction FET of each pixel is a in each row.
, b, c, etc. via capacitors Co.

Next, the operation shown in FIG. 5 will be explained.

First, the basic principle of this image sensor is an n-channel junction type F
When light enters the pn junction of the ET, holes among the charges generated there are accumulated in the gate, increasing the potential at the gate, and the upper layer of the potential appears at the sheath potential by the source follower. (In this case,
The electrons generated at the same time as the holes escape to the power source VOD through the drain. ) Therefore, in FIG. 5, for example, Ql to which the horizontal selection electrode of a is connected.

Q2. When reading out received light signals such as
A negative voltage VL is applied to horizontal selection electrodes such as c.

(A voltage near Ov is applied to a.) In this way, Q3 connected to the horizontal selection electrodes other than a, such as s, c, etc.
．． Q4. Q5. Q6゜ etc. (i.e. other than row a)
All FETs are OFF and Ql, Q2 . etc. act as source followers. However, this is Q
Horizontal selection electrodes a, b, c, etc. and capacitor C
They are bonded via O.

Next, the operation shown in FIG. 5 will be explained.

First, the basic principle of this image sensor is an n-channel junction type F
When light enters the pn junction of the ET, holes among the charges generated are accumulated in the gate, increasing the potential at the gate, and the upper layer of the potential appears at the source potential by the source follower. (In this case,
The electrons generated at the same time as the holes escape to the 10th power supply ■DD through the drain. ) Therefore, in FIG. 5, for example, Ql to which the horizontal selection electrode of a is connected.

Q2. When reading out received light signals such as
A negative voltage VL is applied to horizontal selection electrodes such as c.

(A voltage near Ov is applied to a.) In this way, Q3 connected to the horizontal selection electrodes other than a, such as s, c, etc.
．． Q4. Q5. Q6゜ etc. (i.e. other than row a)
All FETs are OFF and Ql, Q2 . etc. act as source followers. However, this is Q
This is only when the constant current sources such as Ql, Q89, etc. are ONL, and Ql, Q8. When a constant current source such as the above is OFF, the light reception signal cannot be read out.

As described above, it becomes possible to read out the received light of any row.

Note that constant current source Q7. Q8. etc., the signal readability is O.
Power consumption can be reduced by FF.

In FGA, the signal charge generated when receiving light is transferred to a junction FET.
The potential increase due to the charges accumulated in the gate electrode of the FET is read out using the source follower configuration of the junction FET. Therefore, before the FGA receives light again, it is necessary to discharge the signal charge once, that is, to perform presetting. For this purpose, the horizontal selection electrode a in FIG.
, b.

It is sufficient to apply a positive voltage VH to all of C9, etc., and turn on the junction FETs of all pixels.

Further, the signals for one line read out in FIG. 5 are manually input to a horizontal transfer register section (not shown), and can be read out in order by the horizontal transfer register.

FIG. 6 shows a drive timing chart of the operation of the image sensor described above.

As for the detailed explanation of FIG. 6, it is clear from the above, and as mentioned above, the signals in each row are
It is output at timings such as B, C, etc. However, in reality, in order to reduce 1/f noise, the output voltage difference between the readout signal of each row and the readout signal immediately after the end of application of voltage VH to the horizontal selection electrode after readout is handled as a signal.

Further, FIG. 7 shows a diagram simulating a signal readout method when the image pickup device shown in FIG. 4 is used in the RGB-3V camera shown in FIG. 1.

The image sensor of the present invention has been described above in detail, but this image sensor has a horizontal line for reading out signals, that is,
There is a degree of freedom in that columns can be selected arbitrarily.

Therefore, in the third embodiment of the present invention, whereas the horizontal selection electrodes were provided in all the pixels at the same position in the row direction in the image sensor shown in the fourth figure, the horizontal selection electrodes were provided in each pixel. The light reception signal can be read out by providing a plurality of horizontal selection lines for each - row and arbitrarily wiring (coupling) the horizontal selection lines and the horizontal selection electrodes provided independently for each pixel. This adds more flexibility to the method.

FIGS. 8(a) to 8(C) are electrode arrangement diagrams of the third embodiment;
Figures (b) and (C) are cross sections A and B, respectively.

In the embodiments shown in FIGS. 8(a) to 8(C), 901 is the drain of an n-channel junction FET constituting one pixel;
02 is the gate 903 is the source. Further, 904 is a silicon oxide film (insulator), 908 is a signal readout line, and 90
Reference numeral 9 denotes a selection electrode provided independently in each pixel.

Also, al, a2. a3. and bl, b2. ..., etc. are horizontal selection lines, and in this case, 3 lines are selected for one row of pixels.
Each horizontal selection line is prepared separately.

This horizontal selection line is 905,906°907 in FIG.
909 provided independently for each pixel at positions such as...
wired with selective electrodes. Therefore, the horizontal selection line at (i=1.2.3) can select signals from every three pixels in any row of the image sensor.

FIG. 9 shows an example of the overall configuration of the signal readout wiring in the present invention.

According to the configuration of this embodiment, when a trigger button (not shown) is pressed, exposure is performed using the shutter for a predetermined time, and then sequentially 1
Read out line by line. At this time, when selecting and reading the horizontal selection line a1, by sequentially supplying the selection signals a, "-'a3 for each field, first, only the signals of R (red) pixels are sequentially read out row by row. Then, only the signals of G (green) pixels are sequentially read out row by row in the next field, and then only the signals of B (blue) pixels are sequentially read out row by row in the next field.

Therefore, it is also possible to combine the recording (reproduction) amplifier and the recording (reproduction) head in the configuration shown in the first figure and shift the head after sequentially recording each color signal.

In this case, the playback device plays back one track at a time, stores it in memory, then shifts to the next track and plays it back.

Next, FIG. 10 is a diagram showing a fourth embodiment of the present invention.

FIG. 10 differs from FIG. 8 in the arrangement of the selection electrode 1009. That is, the selection electrode is provided on the left side of the pixel. This makes it possible to reduce electrostatic (or coupling) capacitance between horizontal selection signal lines.

Further, FIG. 11 shows the fifth embodiment of the present invention, and the tenth embodiment shows the fifth embodiment of the present invention.
This is a further improvement on the fourth embodiment of the present invention shown in the figure.

That is, the horizontal selection signal line a3 is located below the pixel.

As a result, the interval between the horizontal selection signal lines al and a2 is
The horizontal selection signal lines al, a2. It is possible to increase the thickness of the line a3, reduce the electrostatic (or coupling) capacitance between the horizontal selection signal lines, and reduce the impedance of the selection signal lines.

According to the configurations of the third to fifth embodiments described above, not only can signals of every plural pixels be read out when reading out one row at a time, but also signals can be read out when reading out multiple rows at the same time. The combination of pixels can be changed.

Also, considering the application to the above-mentioned RGB-3V camera,
The case where signals of every three pixels in an arbitrary row of a solid-state image carrier are read out has been described. Therefore, each row of solid-state image sensors has a horizontal selection signal line.

It is not necessary to limit each row of solid-state image sensors to three, and the number may be two, four, etc., depending on the system.

Further, the connection between the selection electrode and the horizontal selection signal does not need to be three pixels apart, and is arbitrary, and the connection state may be different for each row.

Further, the number of horizontal transfer registers is not necessarily limited to three.

[Effects of the Invention] As described above, according to the recording and reproducing system of the first invention of the present application, it is possible to record and reproduce high-band still images. In addition, according to the second invention of the present application, it is possible to add more flexibility to the signal readout method of the image sensor than in the conventional case, and the scope of application is not only to RGB-3V cameras but also to other systems. also becomes very large.

In particular, when applied to RGB-3V cameras, only one recording signal processing system and at least one recording head are required, making it extremely useful for downsizing, lowering prices, and lowering power consumption of cameras. has advantages.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the configuration of an RGB-SV camera according to the first embodiment of the present invention, and FIG. 2 is a diagram for explaining the RGB-3V recording frequency allocation of the first embodiment of the present invention. FIG. 3 is a diagram for explaining the configuration of the RGB-3V reproducing apparatus according to the first embodiment of the present invention. FIGS. 4(a) and 4(b) are diagrams for explaining the structure of a solid-state image sensor according to a second embodiment of the present invention. FIG. 5 is a diagram for explaining an equivalent circuit of a second embodiment of the present invention. FIG. 6 is a diagram for explaining the drive timing of the second embodiment of the present invention. FIG. 7 is a diagram for explaining signal readout wiring of an imaging device according to a second embodiment of the present invention. FIG. 8(a) is a diagram for explaining the structure of a solid-state image sensor according to a third embodiment of the present invention, FIG. 8(b) is a cross-sectional view of A, and FIG. 8(C) is a cross-sectional view of B. FIG. 9 is a diagram for explaining a signal readout method of a solid-state image sensor according to a third embodiment of the present invention. FIG. 10(a) is a diagram for explaining the structure of a solid-state image sensor according to a fourth embodiment of the present invention, FIG. 10(b) is a cross-sectional view of A, and FIG. 10(e) is a cross-sectional view of B. FIG. 11 is a diagram for explaining the structure of a solid-state image sensor according to a fifth embodiment of the present invention. FIG. 12 is a diagram for explaining recording frequency t allocation of Sv (still video). 501.901,1001 Nidrein 502.902
, 1002: Gate 503.903, 1003: Source 506.908, 1008: Signal readout line (polysilicon) 505: Horizontal selection electrode (polysilicon) 909.100
9: Selection electrode (polysilicon) al, a2. a3. bl
, b2. b3. cl.

Claims (2)

[Claims] (1) A recording and reproducing system that records a plurality of color signals obtained from an image sensor on a plurality of adjacent tracks of a recording device, and combines the signals obtained from the plurality of tracks during reproduction to record a video signal. (2) A solid-state imaging device in which pixels are arranged in rows and columns, characterized by having selection means for selecting a predetermined row and selecting mutually different pixels in the selected row. Imaging device.