JPH01295366A - Vector processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a vector processing device, and in particular, to a vector processing device that is equipped with a storage device with a hierarchical structure and that allows data transfer between layers without any burden on programs. The present invention relates to a vector processing device.

[Conventional technology]

In the use of computers, the demand for large-scale technical calculations has become extremely large in recent years, and vector processing devices have been developed to meet this demand. The main factor determining the performance of this type of vector processing device is memory throughput, and designing a faster vector processing device requires a great deal of effort to be devoted to the logic section that controls the main memory. Ta. Additionally, in order to achieve high memory throughput, it is necessary to use high-speed storage elements in the storage section, and for this reason, the storage section of vector processing devices tends to be more expensive than that of general computers. be. In order to avoid such high cost of the storage section, vector processing devices in recent years have been configured with a storage section having a hierarchical structure. As a prior art related to a vector processing device having a storage section with this kind of hierarchical structure, for example, IEE, C.H. 2216-
0 (IEEE, CH2216-0), (1985),
The technique described on pages 301 to 309 is known.

In this type of conventional vector processing device, the storage section includes a main storage section and a local memory, and when vector data is loaded into a vector register, the data is transferred from the main storage section to the local memory. I needed to. This data transfer is defined by the program. For example, programmatically, REAL JN COMMON10NE/JN (780) REGFIL
By specifying E ONE, it is specified that array JN is allocated to a storage section different from the main storage section.

The above-mentioned method requires the user to manage the memory, which imposes a heavy programming burden. on the other hand,
Demand paging processing, which is implemented on a general-purpose computer or a relatively low-speed vector processing device, solves the above problems by controlling data transfer using hardware. However, with current technology, it is difficult to achieve a data transfer rate of more than 10 GB/Sec by paging control.

The vector processing device, which has a processing performance of several GFLOPS or more, is equipped with a hierarchical storage section, making it possible to transfer data between the layers that make up the storage section with as little programming burden as possible. There is a strong demand for the development of vector processing devices.

[Problem to be solved by the invention]

A vector processing device according to the prior art, which is equipped with a hierarchically structured storage unit and whose processing performance is on the order of several GFLOPS, requires a program to specify data transfer between storage hierarchies. The problem was that a large number of instructions had to be mixed together, making it difficult to decipher them and placing a heavy burden on the programmer.

An object of the present invention is to solve the problems of the prior art described above, and to enable hardware to detect transfer conditions and transfer data between storage hierarchies without reducing memory throughput L in a vector processing device. An object of the present invention is to provide a vector processing device that can reduce the burden on programs.

[Means to solve the problem]

According to the present invention, the above object is achieved by providing the following configuration and functions.

(1) A storage unit having a hierarchical structure including a main memory and a local memory.

(2) An instruction processing unit configured by a processing unit that executes vector processing and a processing unit that executes brief fetch processing that transfers data from the main storage unit to the local memory in advance.

(3) A synchronization control mechanism provided between the image processing sections.

(4) A function provided in a compiler that analyzes a program and adds tags that can be processed by an instruction decoder to logical divisions of the program.

The logical partitioning of the program occurs when control of the program is passed to another routine, when the amount of vector data transferred to a vector register by a vector load instruction may exceed the capacity of local memory, or
Write the data in the vector register to main memory using vector processing, and then write the same data using the vector load instruction.
This is the position when writing to the vector register. A program is separated into n logical partitions by the compiler identifying the logical partitions.

(5) A function provided in the compiler that analyzes a program divided into n parts and creates a code that acts on the prefetch processing section. In other words, vector instructions other than vector load instructions are erased or disabled, address register set-up instructions, etc. necessary for vector load instruction execution are left, and floating point arithmetic instructions, etc. that are unrelated to vector load processing are erased or disabled. function.

(6) A function to add information to the above-mentioned tag position to identify whether or not the brief fetch process can be executed unconditionally, and whether or not it is necessary to wait for the completion of the vector store process of the vector processing unit.

This additional information is processed by the instruction decoder.

(7) A function provided in the compiler that analyzes a program divided into n parts and creates a code that acts on the vector processing section.

This conversion work is similar to conventional vector code creation.

(8) A function that adds an instruction to the above-mentioned tag position to determine whether or not to release the wait state of the brief fetch processing unit.

This release information is determined and generated by checking whether the result of the vector store is being read by vector load.

[Effect]

Vector processing devices according to the prior art process vector instructions that specify vector processing and scalar instructions that specify scalar processing. Vector instructions, particularly instructions that perform set-up processing that define a main memory reference method for vector load/store instructions, are called set-up instructions and are classified as a type of scalar instruction. Vector load/store instructions operate the memory requester and control data transfer between main memory and vector registers, and the main memory reference address is explicitly specified in the instruction operand and implicitly specified. It can be divided into those that are The implicitly specified instruction is called an indexed vector load/store instruction.

In the vector processing device according to the present invention, the vector processing logic unit controls data transfer between the local memory and the vector register using a vector load instruction, and controls data transfer between the main memory and the vector register using a vector store instruction and an indexed vector load/store instruction. Controls data transfer between The brifetch processing logic processes vector load instructions and controls data transfers between main memory and local memory.

Setup instructions affect both the vector processing logic and the prefetch processing logic.

The tags and other information attached to the logical divisions of the program act on the instruction decoders of the vector processing logic and prefetch processing logic to synchronize the image processing sections. Although tags and synchronization information are means for program execution, they do not themselves participate in data processing specified by the program. Therefore, the term "instruction" will not be used hereinafter for this information.

A program is converted by a compiler into two types of object code: code for the vector processing logic and code for the brief fetch processing logic. These two types of object codes are treated as one user job by O3, and one logical space is given to the two types of object codes. When it is time to allocate CPU resources to a user job,
O8 instructs the scalar processing section of the vector processing device to start processing from the first address of the object code for brief fetch processing. This instruction is performed by rewriting the NIA area of the program status word in the scalar processing section. The scalar processing section sets up registers for addressing in the vector processing logic section and the briffetch processing logic section by processing set-up instructions in addition to scalar processing. The scalar processing section is
After these setups are completed within their respective processing logic, the prefetch processing logic is activated, followed by the vector processing logic. The image processing logic section determines whether to decode instructions or idle, based on the tag information at the beginning of each object code section, and operates accordingly. Initially, the prefetch processing logic section always enters instruction decoding processing, and the vector processing logic section determines whether to idle or not based on the information of the tag.

When a vector load instruction is detected in the brief fetch processing logic section, data is transferred from the main memory section to the local memory section. Further, when a tag is detected in the brifetch processing logic section, a release signal is generated, and the release signal causes a semaphore in the synchronization control mechanism between the vector processing logic section and the brifetch processing logic section to count up.

This semaphore is counted down when the vector processing section shifts from idling processing to instruction decoding processing.

If the tag information at the tag position of the object code for brief fetch indicates that the next brief fetch process can be executed unconditionally, the process of the next logical division of the object code is subsequently executed by the brief fetch processing unit. . At this time, the setup of the address register in the briffetch processing section must be completed by the scalar processing section. This guarantee is made by the compiler. The address register in the brief fetch processing unit may be dual-sided. If you do not have dual hardware, change the register numbers and use software to ensure that the contents of the registers referenced in the brieffetch process will not be destroyed in the setup process of the scalar process.

If the tag information at the tag position of the object code for brifetch indicates waiting for vector processing of the next brifetch process, the brifetch processing unit enters an idling state. To release this state, if there is a wait release instruction for the brief fetch processing section at the location of the object code, the vector processing section sends the instruction decoding section on the vector processing section to the instruction decoding section on the brief fetch processing section. Send a signal. The aforementioned semaphore does not operate in response to this release signal.

The vector processing of the brief fetch processing is executed in an overlapping manner in each processing unit when there is no causal relationship to the vector data to be vector loaded.

FIG. 2 is a diagram for explaining the execution status of brief fetch processing and vector processing, and this will be explained below.

In FIG. 2, P F n (n = O+ 1 +
2-------) is for briefetch processing, and also for VPn
(n=o.

1...-...-) indicates execution of vector processing.

The numerical value in the row labeled Semaphore indicates the content value of the semaphore, that is, the count value, and Δ indicates the signal propagation time between the brief fetch processing section and the vector processing section. This signal propagation time is exaggerated relative to the actual time.

Now, in FIG. 2, first the brief fetch processing PFO
is executed, and when this process is completed at the tag position, the value of the semaphore is incremented by 1. The vector processing unit tests the value of this semaphore, and if this value is a positive value, executes vector instruction decoding. After the completion of the brief fetch processing PFO, if the tag information is not waiting for a release signal from the vector processing unit, the processing of the brief fetch processing PFI is started from the next cycle. Similarly, brief fetch processing PF2
Assume that the processes up to this point have been executed, and the tag after the completion of the process PF2 is waiting for vector processing. In this case, the brief fetch processing unit shifts to a waiting state based on the tag information. When the vector processing VPO is completed, the waiting state of the above-mentioned brifetch processing unit is released, and the brifetch processing unit executes the next brifetch processing PF3,
The vector processing unit executes processing of vector processing VPI. During this time, the semaphore is +
1, and is decremented by 1 at the start of vector processing, resulting in a value as shown in FIG.

The above is the general operation of the vector processing device according to the present invention, and the present invention allows vector load processing to overlap vector calculation processing by pipeline processing of brief fetch processing and vector processing operation. The degree of overlap has been expanded from the overlap of instruction execution stages due to chaining control of vector processing devices in the prior art to the overlap of logical division units of programs.

Briefetch processing has a smaller amount of processing and shorter execution time than vector processing, so when executing multijicob,
It is possible to perform brief fetch processing for multiple jobs. Therefore, O3 needs to newly manage addresses for brief fetch processing.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a vector processing apparatus according to the present invention will be described in detail below with reference to the drawings.

In one embodiment of the present invention, the local memory has a structure similar to the vector register in the vector processing section, and the access rights to the area corresponding to the vector register are managed by the brief fetch processing section. This area becomes ``data confirmed'' when the brief fetch process is completed, data is successively outputted to this area from the vector processing unit, and becomes ``vacant j'' when data is written to the vector register.

Since brifetch processing is performed in advance of vector processing, if you try to execute a vector load instruction in the brifetch processing section, the area on the local memory where the vector data read from the main memory will be written is "data finalized". There may be cases where this is the case. At this time, the instruction decoding section in the brief fetch processing section suppresses activation of the vector load instruction. This suppression of activation is not released until the local memory is read from the vector processing unit.

As mentioned above, the embodiment of the present invention manages the local memory area in two states: "data fixed" and "vacant J", but the embodiment also manages the local memory area in two states: "data fixed" and "empty J", but the chaining method allows writing and reading to be performed simultaneously like a vector register. It can also be extended to support control.

FIG. 1 is a block diagram showing a schematic configuration of a vector processing device according to an embodiment of the present invention, FIG. 3 is a block diagram of a brief fetch processing section, and FIGS. 4 and 5 are block diagrams of a local memory state management section. , FIG. 6 is a block diagram of a data transfer processing unit that controls data transfer between a local memory and a vector register in the vector processing unit. Figures 1 and 3
In Figures to Figure 6, 1 is a brieffetch decoder, 2
is a vector instruction decoder, 3 is an instruction successive instruction logic unit for brifetch processing, 4 is a vector address generation logic unit for brifetch processing, 5 is a semaphore, 6 is a vector instruction successive logic unit, and 7 is an address generation logic unit for vector processing. , 8
1 is a data transfer processing unit between local memory and vector register, 9 is an address table for local memory access, 10 is a storage control unit, 11 is a main memory unit, 15 is a switching logic unit, 16 is a local memory, and 17 is a local memory state management section, ■8 is a vector register, 19 is a vector register state management section, 112° 123.30
6,411 is an adder, 114 is a counter, 115,40
0 is a comparison circuit, 202 is a priority circuit, and 403 is an encoder.

In FIG. 1, areas 12 to 14 on the main storage unit 11 store an instruction sequence for brief fetch processing, an instruction sequence for vector processing, and vector data, respectively.

In the vector processing device shown in FIG. 1, the instruction successive output logic unit 3 first executes instruction reading for brief fetch processing. The instruction successive logic section 3 transfers the instructions from the main memory section II to the storage control section 1.
0 is received via path 50 and sent to brieffetch decoder 1 via path 51. In this operation, the fetch address and data are transferred onto the path 50, and the instruction from the decoder 1 and the fetch data from the instruction read logic unit 3 are transferred onto the path 51. These paths 50 and 51 are each a collection of a plurality of signal lines, but are shown as one line in FIG. 1 to simplify the drawing.

When the brifetch decoder 1 detects a vector load instruction for brifetch processing as a result of decoding the aforementioned brifetch data, it activates the vector address generation logic unit 4 via the path 52 . The vector address generation logic unit 4 generates an address for reading vector data from the main storage unit 11 and sends it to the path 53, and at the same time,
The base address and incremental address for generating the same vector data are set in the address table 9 corresponding to the write destination local memory. These addresses are used by the vector processing section to read local memory 16. The storage control unit 10 reads vector data from the main storage unit 11 according to the address sent on the path 53. The read vector data is sent to the switching logic section 15. It is written to local memory 16 via path 54. The switching logic section 15 is activated by the sink information added to the address in each instruction read logic section 3, 6 and each address generation section 4.7. In this embodiment, the local memory 16 has a data arrangement structure similar to that of the vector register 18, but is not particularly limited to this structure. The state management unit 17 of the local memory 16
It is composed of a set of flip-flops that manage the status of data in each area of the local memory 16. These flip-flops are set when data is determined in the corresponding area, and reset when the data area is released by access from the vector processing section. The state management unit 17 then controls the local memory 1
If data has been written to all the areas on 6 and additional writing is not possible, an inhibition signal is sent to the vector address generation logic unit 4 for briefetch processing via path 55.

The vector address generation logic unit 4 reserves address generation for briefetch by this inhibition signal.

When the briefetch decoder 1 detects a tag in the briefetch instruction string, it counts up the semaphore 5 via the path 56.

Further, if the next brifetch process needs to wait for the completion of processing of a vector instruction sequence, the brifetch decoder 1 sets a flip-flop inside the brifetch decoder 1 and stops the instruction decoding process. This waiting state continues until a reset signal is sent from the vector processing address generation logic section 7 onto the path 57.

The vector instruction decoder 2 uses paths 59 and 60 and the vector instruction successive output logic section 6 to read a vector processing instruction sequence from the main storage section 11 via the storage control section 10. In this case, the determination as to whether or not the vector processing instruction sequence can be read is made in the vector instruction decoder 2 by reading the value of the semaphore 5 through the pass 5. pass 59
．． Similarly to paths 50 and 51, 60 is composed of a plurality of signal lines. When the vector instruction decoder 2 detects a vector load instruction in the read vector processing instruction sequence, it activates the data transfer processing section 8 between the local memory 16 and the vector register 20 via the path 62. Further, when the vector instruction decoder 2 detects a vector access instruction other than the vector load instruction in the vector processing instruction string, it activates the vector processing address generation unit 7 via the path 61.

The data transfer processing unit 8 accesses the address table 9 via the path 63, determines which area in the local memory 16 stores the vector data to be accessed, and at the same time accesses the vector register via the path 64. The state management unit 19 determines the busy status of the tr stray light vector register.

Furthermore, the data transfer processing unit 8 uses the local memory state management unit 17 via the path 69 to control the local memory 1
It is determined whether vector data is written in the specific area within 6. If writing to the vector register 18 is possible, the data transfer processing unit 8 accesses a specific area of the local memory 16 via the path 65 and sends out an address from which to read the vector data. Data read from local memory 16 is thereby written to vector register 18 through path 66° selector 20. The selection information of the selector 20 is transmitted to the vector instruction decoder 2.
is generated from the instruction's operation code. When the reading from the local memory 16 is completed, the data transfer processing section 8 sends out an area reset signal in the local memory via the path 67. The state of the vector register 18 is managed by a state management section 19. When a vector register 18 is used by a resource in the vector processing unit, that resource generates a register free signal, which is sent via path 68 to the vector register 18 in the vector register state management circuit 19. The flip-flops holding the state of each register area are reset. Resources in the vector processing unit are omitted and not shown in the first part.

FIG. 3 shows the briffetch decoder 1 in the vector processing device shown in FIG. 1 described above. Instruction succession logic unit for brief fetch processing 3. It is a block diagram showing details of a vector address generation logic unit 4 for brief fetch processing and an address table 9 for local memory access, and will be described below. In FIG. 3, the same reference numerals as in FIG. 1 indicate the same parts.

In FIG. 3, an instruction for brief fetch processing is sent from the instruction successive logic section 3 shown in FIG. 1 via a path 51b, and is set in the register 100.

Decoder 101 decodes the operation code portion of the instruction set in register 100.

The briefetch processing unit decodes a vector load instruction for performing a briefetch, an address register set-up instruction for the vector load instruction, and a tag. In this case, the tag is also decoded as a type of command, and these are decoded by the decoder 101.

When decoder 101 detects an address register set-up instruction, decoder 101 transmits a selection signal to switching circuit 102 through path 150. As a result, the address information in the operand of the instruction in register 100 is sent to registers 103-105. It is assumed that a vector word length, a vector base address, and a vector increment address are stored in the registers 103 to 105, respectively.

Further, although the address information is obtained directly from the operand of the instruction, it is not necessarily limited to the immediate type.

When the decoder 101 decodes the tag, it counts up the semaphore 5 via the path 56. The semaphore 5 is composed of an up/down counter. If the read tag indicates waiting for vector processing, decoder 1
01 sets flip-flop 106. The output of this flip-flop 106 is inverted by an inverter 107 and input to an AND circuit 108. Flip-flop 106 is not cleared until a reset signal is sent via path 57 from address generation logic 7 of the vector processing section.

When decoder 101 decodes the vector load instruction, decoder 101 sends an activation signal to path 152. This activation signal is sent to the register 110 as a set signal for the register 110 via an AND circuit 108 and an OR circuit 109.
given to. The activation signal via this AND circuit 108 is also applied to the selector 111 via a path 153 at the same time.

Thereby, the selector 111 sends the contents of the register 104 to the adder 112. As a result, the contents of register 104 are passed through adder 112 and stored in register 110. Selector 111 sends the information in register 105 to adder 112 when the activation signal on path 153 is turned off. On the path 53c, the storage control unit 10 shown in FIG.
A release signal is sent from This release signal indicates that the storage control unit 10 has processed the request, and is given as a set signal to the register 110 via the AND path 113 and the OR circuit 109. As a result,
Every time a release signal is sent on path 53c, the value in register 105 is added to the value in register 110, that is, the base address value in register 104 is added to the value in register 110.
The value to which the vector increment values are sequentially added is sent out on the path 53a. Signal on path 53c and path 1
The signal on 53 causes counter 114 to count up, and its output is sent to register 103 by comparison circuit 115.
It is compared with the vector word length above. The result of this comparison is “1 pass” when the two match, and “1 pass” otherwise.
0” and is sent on path 155. This path 15
The signal "1" on 5 resets the counter 114;
It becomes a set signal for the register 100, and the OR circuit 1
17. This signal is simultaneously latched by flip-flop 116, inverted by inverter 118, and input to AND circuit 113 via path 154. This interrupts vector address generation.

The above operation completes address generation for the vector load instruction, and a signal is sent on path 155 at this time. Furthermore, when decoder 101 detects an address set-up command, it sends a signal onto path 51a. The signals on these paths 155.51a are sent to OR circuit 1
After the logical sum is performed in step 17, the logical product is performed with the inverted signal of the output of the flip-flop 106 in an AND circuit 119. The output of this AND circuit 119 indicates completion of the instruction decoded by the decoder 101. However, here, the tag is not included in the instruction. The instruction completion information that is the output of the AND circuit 119 is combined with the reset signal on the path 57 and the OR circuit 12.
It is ORed with 0 and sent on path 156 as a set signal for register 121.

The register 122 stores the preset instruction word length, and the adder 123 adds the preset instruction word length in the register 122 and the value in the register 121, and calculates the value when the signal value on the path 156 is "1". It is sent onto the path 50 at the set timing. The sync information is sent to the storage control section by expanding the signal line width and sending out a predetermined extra signal value when sending signals onto the paths 50 and 53a.

4 and 5 show the local memory 16 shown in FIG. 1,
1 is a diagram showing details of a local memory state management circuit 17, a switching logic unit 15, and an address table 9,
This will be explained below. Since these figures are related to FIG. 3, there are parts where the same logic is expressed overlappingly. Also, the same paths are given the same reference numerals.

Figure 4 mainly shows the configuration that controls whether or not the local memory area is writable, and Figure 5 shows the configuration that controls writing data to the same area and reading data from the vector processing unit to the same area. It shows the configuration.

In FIG. 4, a flip-flop 200 controls the writable state of each area of the local memory 16, and "0" indicates writable. all flip flops 200
is “1”, the output of the AND circuit 201 is “1°”, and the signal value on the path 162 is “0”.The signal value “0” on this path 162 is It acts on the AND circuit 108 shown in the figure and suppresses activation of the vector load instruction.

When the values of the flip-flops 200 are "0" for a plurality of values, the priority circuit 202 determines the priority order. The determined result is encoded by encoder 203 and sent on path 250. This code information acts on the switching circuit 204 to control sending the vector base value and vector increment value in the registers 104 and 105 to the tables 9a and 9b in the address table 9. As a result, address tables 9a and 9b
A vector base value and a vector increment value are respectively set in . The code information on path 250 is simultaneously decoded by decoder 205, which sets flip-flop 200 corresponding to the local memory area to ``1'', indicating that the area is not writable. The +iF output of the local memory 16 from the vector processing unit is performed on the bus 200, and when it is no longer needed, it is reset via the path 252.The code information on the path 250 is further set in the register 206, and then
Register 303 in FIG. 5, which will be described later, via path 53b.
sent to. This information is used for switching when writing data to a local memory area.

Next, in FIG.
is stored in Similarly, sync information and advance information are sent via paths 351 and 352. The data stored in the register 300 is stored in the switching logic section 1.
The sink information is distributed to the request source destination via the register 301 acting on the request source. The path 54 is
This is the path that distributes fetch data to local memory. On the other hand, as described above, information specifying the write destination local memory area from the encoder 203 in FIG. 4 is propagated through the path 53b.

This information acts on the switching circuit 302 via the register 303 for signal delay, and controls writing of the data on the path 54 into each area of the local memory 16. In FIG. 5, each area of the local memory 16 is
It is shown that there are 0 to n.

The register 305 is initially set to ``0'', and its value is incremented by 1 by the adder 306 each time data is read from the main memory section 11.The value of this register 305 is then set to ``0'' in the local memory to be written. This value is distributed by the switching circuit 306 for accessing each area of the local memory 16.

On the path 65a, the address of the local memory to be read is sent from the vector processing section.

Similarly, on the path 65b, information used for selecting the area of the local memory 16 to be read is sent from the vector processing section. Based on this information, the vector data read from the local memory 16 is transferred to the path 6.
6 to the vector register 18.

As explained with reference to FIG. 3, a vector address generation completion signal is sent from the comparator circuit 115 onto the path 155. This completion signal is passed through the register 304 for signal delay, and is sent to the switching circuit 307.
It is stored in one of the registers 308 corresponding to each area of the local memory 16 where writing is being performed. The entire register 308 and the entire flip-flop 200 shown in FIG. 4 constitute the local memory state management section 17 shown in FIG.

FIG. 6 is a block diagram showing details of the vector processing address generation logic section 7 and data transfer processing section 8 shown in FIG. 1, and will be described below.

In FIG. 6, as already explained in FIG. 4, the vector base address is stored in register 9a.
Each vector increment address is stored in b.

On paths 450 and 451, a base address and an incremental address necessary for processing a vector instruction that refers to the main memory, which is processed by the vector processing unit, are sent. The source of these address data is address data set in a register in the vector processing section by a set-up instruction in the scalar processing section.

When the logic circuit shown in FIG. 6 is activated from the vector instruction decoder 2 shown in FIG. Find out whether or not. That is, whether or not the vector data match is checked by checking whether the base address and the incremental address match each other in the comparator circuit 400, and whether or not the two addresses match is checked by the AND circuit 401.

In the case of a vector load instruction, the output of the OR circuit 402 is “
1'', and in the case of a vector store instruction, the OR circuit 40
The output of 2 is 0''.The output of this OR circuit 402 is
It is sent to the local memory state management circuit 17 shown in FIG. 1 via a path 67a. Further, the output of the AND circuit 401 is encoded by the encoder 403, and the output of the AND circuit 401 is encoded by the encoder 403.
5b to the local memory 16 in FIG.

The sink destination of the path 65b is the selector 311 shown in FIG.
It is.

The register 404 holds the vector length. Logic circuit 405 is a counter and counts up the data in register 407 by +1 every cycle. register 4
The output of 07 is sent to the local memory 16 in FIG. 5 via a path 65a, and becomes a local memory reference address. At the same time, the value of register 404 and the value of register 407 are compared by comparison circuit 406, and the result is sent to storage control unit 10 via path 70b.

For vector store instructions, selector 410 first sets the base address on path 450 to register 412 through 1Irl multiplier 411, and then sends the vector increment address on path 451 to the adder.

The result of this addition is stored in register 412 and
a and is sent to the storage control unit 10. For indexed vector instructions, the index value on bus 455 is used instead of the vector increment value on path 451.

The operation of selector 410 is instructed by vector instruction decoder 2 shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, in vector processing, the vector data fetch operation, which contributes most to the processing performance, can be overlapped with the vector arithmetic processing for each logical division of the program.

As a result, the present invention makes it possible to overlap processing in a wider range than the overlap effect of instruction execution stages due to chaining control of vector processing devices according to the prior art. In the processing device, by duplicating vector load processing and vector calculation processing, it is possible to speed up vector data reading. Therefore, according to the present invention, it is possible to configure the main memory section of the vector processing device with relatively low-speed storage elements, and it is possible to configure the entire processing device at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a vector processing device according to an embodiment of the present invention, FIG. 2 is a diagram explaining the execution status of brifetch processing and vector processing, and FIG. 3 is a block diagram of a brifetch processing section. , FIGS. 4 and 5 are block diagrams of the local memory state management section, and FIG. 6 is a block diagram of the data transfer processing section. l-・--Briefetch decoder, 2・--1-
--Vector instruction decoder, 3---Instruction succession logic unit for brief-fetch processing, 4---Vector address generation logic unit for brief-fetch processing, 5--Semaphore, 6---Vector Instruction successive logic unit, 7-- Address generation logic unit for vector processing, 8-- Data transfer processing unit, 9-- Address table for local memory access, 10--m -Storage control unit, 1
1--Main memory unit, 15--Switching logic unit, 16--Local memory, 17--1111 Local memory state management unit, 18--Vector register, 19- -------Vector register state management section. Fig. 1 Fig. 4 Fig, 5 toscue toLM

Claims (1)

[Claims] 1. In a vector processing device, a storage section consisting of a plurality of hierarchies, a plurality of logic sections that decode vector instructions that refer to the main storage section, and a plurality of logic sections that decode the vector instructions. A vector processing device comprising: a logic unit that performs synchronization control between the units; and a data path provided between any hierarchy of the storage unit and a vector register. 2. In a vector processing device, a storage unit consisting of a plurality of hierarchies, a plurality of logic units that decode vector instructions that refer to the main memory unit, and synchronization control between the plurality of logic units that decode the vector instructions. an ethics unit that stores an index of vector data held in the storage unit; a logic unit that manages whether access to the vector data held in the storage unit is possible; 1. A vector processing device comprising: a data path provided between any one of the layers of the section and a vector register.