JPH01293692A - Mounting board of integrated circuit device - Google Patents
Mounting board of integrated circuit deviceInfo
- Publication number
- JPH01293692A JPH01293692A JP12512688A JP12512688A JPH01293692A JP H01293692 A JPH01293692 A JP H01293692A JP 12512688 A JP12512688 A JP 12512688A JP 12512688 A JP12512688 A JP 12512688A JP H01293692 A JPH01293692 A JP H01293692A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- integrated circuit
- wiring patterns
- wiring pattern
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 239000006187 pill Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は、複数個の集積回路装置を搭載し、各集積回
路装置の接続ビン間を接続する集積回路装置の実装基板
に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a mounting board for integrated circuit devices, which is equipped with a plurality of integrated circuit devices and connects connection bins of each integrated circuit device. Regarding.
（従来の技術）
従来より集積回路装置（以下ＩＣと称する）の実装基板
にあっては、多数の接続ピンを有する複数個のＩＣ間の
回路接続を、例えば２層配線パターンを形成することに
よりパターン交差部の処理を行なっている。ところが、
最近ではＩＣの集積規模が飛曜的に拡大されつつあり、
これに伴ってＩＣパッケージの入出力信号数も増え、接
続ピン数も増大している。このため、実装基板では、Ｉ
Ｃ間の配線パターンが非常に複雑化かつ高密度化してき
ており、多層配線処理が要求されている。(Prior Art) Conventionally, in mounting boards for integrated circuit devices (hereinafter referred to as ICs), circuit connections between a plurality of ICs having a large number of connection pins have been made by forming, for example, a two-layer wiring pattern. Pattern intersections are being processed. However,
Recently, the scale of IC accumulation has been expanding rapidly.
Along with this, the number of input/output signals of IC packages has increased, and the number of connection pins has also increased. Therefore, on the mounting board, I
The wiring pattern between Cs has become extremely complex and dense, and multilayer wiring processing is required.
−例として、第２図に示すような信号交換器が挙げられ
る。この信号交換器は、ｎ入力に出力（ｎＸｋ）の１次
セレクタモジュールＳ １１〜Ｓ １１によりＮ回線入
力を１（−Ｎ／ｎ）分割し、それぞれｋ （＜））回線
に縮小してに入力に出力（（Ｎ／ｎ）ｘ （Ｎ／ｎ））
の２次セレクタモジュールＳ２１〜８２にのに入力回線
に接続する。そして、各モジュール８２□〜８２ｋによ
りに出力回線を選択的にに入力ｎ出力（ｋＸｎ）の３次
セレクタモジュールＳＫＩ〜ＳＫＩのに入力回線に接続
し、各モジニールＳｌｌ〜ＳＳＳによって元のＮ回線に
選択的に拡大出力するものである。各モジュールをＩＣ
化して基板に実装すると、モジュール間の配線パターン
は図に示すように各所で交差するため、多層配線処理さ
れることになる。- An example is a signal exchanger as shown in FIG. This signal exchanger divides N line input into 1 (-N/n) by primary selector modules S11 to S11 with n inputs and outputs (nXk), and reduces each to k (<)) lines. Output to input ((N/n) x (N/n))
The input lines are connected to the secondary selector modules S21 to S82. Then, each module 82□ to 82k selectively connects the output line to the input line of the input n output (kXn) tertiary selector module SKI to SKI, and each module Sll to SSS connects the output line to the original N line. It selectively enlarges and outputs the image. IC for each module
When the modules are assembled and mounted on a board, the wiring patterns between the modules intersect at various places as shown in the figure, resulting in a multilayer wiring process.
しかしながら、上記のような配線処理では、例えば設計
変更等によって１回線の配線接続を変える場合でも、そ
のパターンのみの変更では困難であり、他の配線パター
ンの変更を余儀なくされてしまう。このような状況にお
いては、時としてＩＣそのものの実装位置の変更をも行
なわなければならなくなることがある。However, in the wiring process described above, even when changing the wiring connection of one line due to a design change, for example, it is difficult to change only that pattern, and other wiring patterns must be changed. In such a situation, it may sometimes be necessary to change the mounting position of the IC itself.
（発明が解決゛しようとする課題）
以上述べたように従来の集積回路装置の実装基板では、
実装するＩＣの接続ビンの増大により簡単な配線接続の
変更に伴って基板全体のパターンを大幅に変更しなけれ
ばならない場合が多く、極めて非効率的であった。(Problem to be solved by the invention) As mentioned above, in the mounting board of the conventional integrated circuit device,
Due to the increase in the number of connection bins of ICs to be mounted, it is often necessary to drastically change the pattern of the entire board due to a simple change in wiring connections, which is extremely inefficient.
この発明は上記のような事情を考慮してなされたもので
、各ＩＣ間の接続配線に関してたとえＩＣ間接続の変更
があろうとも基本的な配線パターン及びＩＣ実装位置を
変更する必要のない、極めて効率のよい集積回路装置の
実装基板を提供することを目的とする。This invention was made in consideration of the above-mentioned circumstances, and even if there is a change in the connection between the ICs, there is no need to change the basic wiring pattern or the IC mounting position. The object of the present invention is to provide an extremely efficient mounting board for an integrated circuit device.
［発明の構成］
（課題を解決するための手段）
上記目的を達成するためにこの発明に係る集積同局装置
の実装基板は、複数の接続ビンを有する第１及び第２の
集積回路装置が搭載され、各集積回路装置の接続ビン間
を接続する配線パターンを形成してなる集積回路装置の
実装基板において、前記第１の集積回路装置の各接続ビ
ンが接続され互いに平行に同一面上に形成される第１の
配線パターンと、前記第２の集積回路装置の各接続ピン
が接続され前記第１の配線パターンと平行にかつ同一面
上に形成される第２の配線パターンと、前記第１及び第
２のパターンの形成面とは異なる面に形成されかつ第１
及び第２の配線パターンと交差する方向に互いに平行に
形成される第３の配線パターンとを具備し、前記第１及
び第３の配線パターン、第２及び第３の配線パターンの
任意の箇所にスルーホールを形成することにより前記第
１及び第２の配線パターンを接続するようにしたことを
特徴とする。[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a mounting board for an integrated synchronization device according to the present invention is provided, in which first and second integrated circuit devices having a plurality of connection bins are mounted. In the integrated circuit device mounting board formed by forming a wiring pattern connecting the connection bins of each integrated circuit device, each connection bin of the first integrated circuit device is connected and formed parallel to each other on the same surface. a second wiring pattern connected to each connection pin of the second integrated circuit device and formed parallel to and on the same surface as the first wiring pattern; and the first pattern is formed on a surface different from the surface on which the second pattern is formed.
and a third wiring pattern formed parallel to each other in a direction intersecting the second wiring pattern, and at any location of the first and third wiring patterns and the second and third wiring patterns. The first and second wiring patterns are connected by forming a through hole.
（作用）
上記構成による集積回路装置の実装基板では、第１の集
積回路装置の各接続ピンが接続される第１の配線パター
ンと第２の集積回路装置の各接続ビンが接続される第２
の配線パターンを互いに平行にかつ同一面上に形成し、
第１及び第２のパターンの形成面とは異なる面にかつ第
１及び第２の配線パターンと交差する方向に第３の配線
パター、ンを互いに平行に形成し、第１及び第３の配線
パターン、第２及び第３の配線パターンの任意の箇所に
スルーホールを形成することにより、第１及び第２の配
線パターンを接続する。(Function) In the integrated circuit device mounting board having the above configuration, the first wiring pattern to which each connection pin of the first integrated circuit device is connected and the second wiring pattern to which each connection pin of the second integrated circuit device is connected.
wiring patterns are formed parallel to each other and on the same plane,
A third wiring pattern is formed parallel to each other on a surface different from the formation surface of the first and second patterns and in a direction intersecting the first and second wiring patterns, and The first and second wiring patterns are connected by forming through holes at arbitrary locations in the pattern and the second and third wiring patterns.
（実施例）
以下、第１図を参照してこの発明の一実施例を説明する
。(Embodiment) An embodiment of the present invention will be described below with reference to FIG.
第１図はその構成を示すもので、図中ＩＣ，、。FIG. 1 shows its configuration. In the figure, ICs, . . .
ＩＣ１２は共に８人力（Ｉｔ〜Ｉ、）８出力（０、〜０
８）セレクタモジュールである。ここではＩＣ１ｔの８
出力をＩＣＩ□の任意の入力に接続する場合について述
べる。尚、説明を容易にするため、基板自体は図示しな
い。Both IC12 have 8 human power (It~I,) 8 outputs (0, ~0
8) It is a selector module. Here, IC1t 8
The case where the output is connected to any input of ICI□ will be described. Note that for ease of explanation, the substrate itself is not shown.
′！Ｊ１図において、ＩＣ，、の出力端０、〜０８には
第１の配線パターンｐｔｔ〜Ｐｉｌｌが接続され、ＩＣ
Ｉ□の入力端１１〜！８には第２の配線パターンＰ ２
＋””’ Ｐ ２１！が接続される。これらの各パター
ンｐＨ〜Ｐ１８＋ Ｐ ２１〜Ｐ２１１はそれぞれ互
いに平行にかつ同一面上に形成される。第１及び第２の
配線パターンＰ１□〜Ｐ １８＋ Ｐ ２１〜Ｐ２８
の形成面とは異なる面には複数本（図面では８本）の第
３の配線パターンＰ３１〜Ｐ３Ｂが互いに平行に、がっ
第１及び第２の配線パターンＰ Ｉ Ｉ−Ｐ １ Ｂ＋
Ｐ ２１〜ｐｚｓとは直交する方向に形成される。′! In diagram J1, the first wiring pattern ptt~Pill is connected to the output terminals 0, ~08 of IC, ,
Input end 11 of I□! 8 has a second wiring pattern P2
+””’ P 21! is connected. These patterns pH~P18+P21~P211 are formed parallel to each other and on the same surface. First and second wiring patterns P1□~P18+ P21~P28
A plurality of third wiring patterns P31 to P3B (eight in the drawing) are arranged parallel to each other on a surface different from the formation surface of the first and second wiring patterns P I I - P 1 B+.
It is formed in a direction perpendicular to P21 to pzs.
上記構成において、第１の配線パターンｐＨ〜Ｐ１８及
び第３の配線パターンＰ３１−Ｐ３１１、第２の配線パ
ターンＰ２１〜Ｐ２８及び第３の配線パターンＰ３１〜
Ｐ３８の任意の交差部にスルーホールを形成すれば、各
パターン間を接続することができる。In the above configuration, the first wiring pattern pH~P18, the third wiring pattern P31-P311, the second wiring pattern P21-P28, and the third wiring pattern P31~
By forming a through hole at any intersection of P38, each pattern can be connected.
例えば、第１図のクロスポイントの位置にスルーホール
を形成すれば、ＩＣ０＋の０１出力はｐＨ、Ｐ ３１＋
Ｐ ２７を介してＩＣ，□の１７人力に接続され、
ｒｃ、、の０２出力はＰ、ハＰ ３２＋ Ｐ ２２を
介してＩＣ＋２のＩ２人力に接続され、ＩＣ，、の０．
出力はｐｈｉ、Ｐ ３３＋ Ｐ ２６を介してＩＣＩ２
の１６人力に接続される共にＰ ３６＋ Ｐ ２５＋
２２ｇを通じてＩＣ１□の１．、＋８に接続される。ま
た、ＩＣｚの０４出力はＰｌ４、Ｐ ３４＋ Ｐ ２１
を介してＩＣ，□のＩ、入力に接続され、ＩＣＩＩの０
５出力はＰｌ５、Ｐｌ、。For example, if a through hole is formed at the cross point in Figure 1, the 01 output of IC0+ will be the pH, P 31+
Connected to IC, □'s 17 human power via P27,
The 02 output of rc, , is connected to the I2 power of IC+2 via P, 32+ P 22, and the 0.
Output is phi, ICI2 via P33+P26
Both connected to 16 human power of P 36+ P 25+
1 of IC1□ through 22g. , +8. Also, the 04 output of ICz is Pl4, P 34 + P 21
is connected to the I, input of IC, □ through, and the 0 of ICII
5 outputs are Pl5, Pl,.
Ｐ２３を介してＩＣ＋２のＩ、入力に接続され、ＩＣ，
ユの０６，０．．０．出力はＰ Ｌ６＋ Ｐ １７＋
ｐｘｓ以降接続されない。It is connected to the I input of IC+2 through P23, and the IC,
Yu's 06,0. ．． 0. Output is P L6+ P 17+
No connection after pxs.
このように、上記のような配線パターンを形成すれば、
単にスルーホールの位置を変更するだけで容易に接続経
路を変更することができ、接続ビン数が多くなり、また
はモジュール数が多くなっても、同様に配線パターンを
形成することによって容易に拡張することができる。ま
た、第２図に示したような回路でも上記パターン形成に
よって単に２層配線で処理することができる。In this way, if the above wiring pattern is formed,
The connection route can be easily changed by simply changing the position of the through hole, and even if the number of connection bins or modules increases, it can be easily expanded by forming the same wiring pattern. be able to. Furthermore, even the circuit shown in FIG. 2 can be simply processed with two-layer wiring by forming the pattern described above.
［発明の効果］
以上のようにこの発明によれば、各ＩＣ間の接続配線に
関してたとえＩＣ間接続の変更があろうとも基本的な配
線パターン及びＩＣ実装位置を変更する必要のない、極
めて効率のよい集積回路装置の実装基板を提供すること
ができる。[Effects of the Invention] As described above, according to the present invention, even if there is a change in the connection between ICs, it is not necessary to change the basic wiring pattern or the IC mounting position, resulting in extremely high efficiency. Accordingly, it is possible to provide a mounting board for an integrated circuit device with good quality.
第１図はこの発明に係る集積回路装置の実装基板の一実
施例を示す配線図、第２図はこの発明の実施によって大
きな効果が得られる回路例を示す配線図である。
Ｓ１□〜Ｓｌｊ＋Ｓ２１〜Ｓ ２に＋ Ｓ ３１〜Ｓ
３ｊ・・・セレクタモジュール、ＩＣＩＩ、 ＩＣ＋
２・・・セレクタモジニール（集積回路装置）、Ｐ＋＋
〜Ｐｉｌ＋・・・第１の配線パターン、Ｐ２１〜Ｐ２８
・・・第２の配線パターン、Ｐ３１〜ｐｉｓ・・・第３
の配線パターン。
出願人代理人 弁理士 鈴江武彦
−（Ｎ （’Ｑ ぐ −〇 ト のｏｏ
ｏｏ ｏｏ ｏ。FIG. 1 is a wiring diagram showing an embodiment of a mounting board for an integrated circuit device according to the present invention, and FIG. 2 is a wiring diagram showing an example of a circuit in which great effects can be obtained by implementing the present invention. S1□~Slj+S21~S 2+S 31~S
3j...Selector module, ICII, IC+
2...Selecta Modineal (integrated circuit device), P++
~Pil+...first wiring pattern, P21 to P28
...Second wiring pattern, P31~pis...Third
wiring pattern. Applicant's representative Patent attorney Takehiko Suzue
oooooooo.
Claims (1)
搭載され、各集積回路装置の接続ピン間を接続する配線
パターンを形成してなる集積回路装置の実装基板におい
て、前記第１の集積回路装置の各接続ピンが接続され互
いに平行に同一面上に形成される第１の配線パターンと
、前記第２の集積回路装置の各接続ピンが接続され前記
第１の配線パターンと平行にかつ同一面上に形成される
第２の配線パターンと、前記第１及び第２のパターンの
形成面とは異なる面に形成されかつ第１及び第２の配線
パターンと交差する方向に互いに平行に形成される第３
の配線パターンとを具備し、前記第１及び第３の配線パ
ターン、第２及び第３の配線パターンの任意の箇所にス
ルーホールを形成することにより前記第１及び第２の配
線パターンを接続するようにしたことを特徴とする集積
回路装置の実装基板。In a mounting board for an integrated circuit device on which first and second integrated circuit devices each having a plurality of connection pins are mounted and a wiring pattern connecting between the connection pins of each integrated circuit device is formed, the first integrated circuit device A first wiring pattern to which each connection pin of the circuit device is connected and formed on the same plane parallel to each other, and a first wiring pattern to which each connection pin of the second integrated circuit device is connected and formed parallel to and parallel to the first wiring pattern. A second wiring pattern formed on the same surface, and a second wiring pattern formed on a different surface from the first and second wiring patterns and parallel to each other in a direction intersecting the first and second wiring patterns. 3rd to be done
a wiring pattern, and the first and second wiring patterns are connected by forming through holes at arbitrary locations of the first and third wiring patterns and the second and third wiring patterns. A mounting board for an integrated circuit device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12512688A JPH01293692A (en) | 1988-05-23 | 1988-05-23 | Mounting board of integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12512688A JPH01293692A (en) | 1988-05-23 | 1988-05-23 | Mounting board of integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01293692A true JPH01293692A (en) | 1989-11-27 |
Family
ID=14902492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12512688A Pending JPH01293692A (en) | 1988-05-23 | 1988-05-23 | Mounting board of integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01293692A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8398494B2 (en) | 2008-07-30 | 2013-03-19 | Ntn Corporation | Constant velocity universal joint |
-
1988
- 1988-05-23 JP JP12512688A patent/JPH01293692A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8398494B2 (en) | 2008-07-30 | 2013-03-19 | Ntn Corporation | Constant velocity universal joint |
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