JPH01293572A - Field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a field effect transistor having a self-alignment structure without using high resistance heat resistant metal as a gate electrode to be used as a microwave element by forming source.drain electrodes of heat resistant ohmic metal, and so forming a gate electrode in contact with an insulating film as to be smaller in diameter than the other part. CONSTITUTION:In a self-alignment type field effect transistor in which an insulating film 7 is interposed between a gate electrode 10 and source.drain electrodes 6, the electrode 10 is formed of low resistance metal, the electrodes 6 are formed of heat resistant ohmic metal, and the electrode 10 in contact with the film 7 is formed to be smaller in diameter than the other part. For example, an operation layer 2 is formed at the center to be formed in a mesa state on a GaAs board 1, and N<+> type contact layers 3 are formed at both sides thereof. The electrode 10 made of aluminum at its lower part to be smaller in diameter than the upper part is formed. The heat resistant ohmic electrodes 6 are formed on the layers 3, and the SiO2 film 7 is provided between the electrodes 6 and the lower part of the electrode 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a field effect transistor using a compound semiconductor and a method for manufacturing the same.

[Conventional technology]

Compound semiconductors are used in ultra-high frequency devices due to their physical characteristics, and the development of devices using GaAS-based materials is particularly remarkable.

Figure 5 shows, for example, the Technical Report of the Institute of Electronics, Information and Communication Engineers; 1985
Conventional Ga disclosed in F'D85-145
1 is a cross-sectional view showing the structure of an ASMESFET, and this example has a self-line structure in which the gate electrode is made of a heat-resistant metal. In the figure, reference numeral 1 shows a GaAS substrate with a mesa-shaped central part, and an active layer (channel layer) 2 is laminated on the upper surface of the mesa-shaped central part, and an n1 contact layer 3 is laminated on the upper surface of the other part. has been done. Further, a heat-resistant gate electrode 5 is formed on the upper surface of the active layer 2, and an ohmic electrode 11 serving as a source/drain electrode is formed on the upper surface of the contact layer 3.
An SiJ film 8 serving as an insulating film is interposed between the ohmic electrode 11 and the ohmic electrode 11 .

Note that the outline of the manufacturing process of the GaAS MESFET having such a configuration is as follows.

First, after forming the operating layer 2 by ion implantation, W S
A heat-resistant gate electrode 5 is formed using a heat-resistant metal such as i. Next, a St, N, film 8 is formed on the circumferential surface of the heat-resistant gate electrode 5 as a side wall thereof. Next, using the heat-resistant gate electrode 5, Si3N, and film 8 as mask materials, the n" contact layer 3 is selectively formed by ion implantation, and the active layer 2 and the n" contact layer 3 are activated by heat treatment. do.

Incidentally, the noise figure (NF) of a microwave FET is generally determined by the following equation (1).

NP=1+Kf-2nf-C,-(Rs+R,)/gm
...(1) However, C98: Gate capacitance R3: Source series resistance R9: Gate metal resistance g,: In order to improve mutual conductance, that is, noise figure (NF), source series resistance (R,), gate metal resistance Resistance (R,) and gate capacitance! <C9-> is reduced and the mutual conductance (g
, ) may be increased.

In addition, the conventional FET described above has a self-line structure and the distance between the source and gate is short, so it is possible to reduce the source series resistance (R3) and improve the noise figure (NF). .

[Problem to be solved by the invention]

However, in the conventional FET described above, since a heat-resistant metal is used as the gate electrode, the gate metal resistance (Rg) increases and the noise figure (NP) decreases, making it impossible to use it as a microwave device. be.

The present invention has been made in view of such circumstances, and after forming a gate opening in a portion where a gate electrode is to be formed,
After shortening the opening by forming an insulating film as a sidewall in the gate opening, a mushroom-shaped gate electrode with a small diameter at the opening is formed, which allows the electrode to be made of high-resistance heat-resistant metal. An object of the present invention is to provide a field effect transistor that can have a self-line structure without using it as a gate electrode and can also be used as a microwave device, and a method for manufacturing the same.

[Means to solve the problem]

The field effect transistor according to the present invention is a self-line type field effect transistor in which an insulating film is interposed between a gate electrode and a source/drain electrode, wherein the gate electrode is made of a low resistance metal, and the source/drain electrode is made of a low resistance metal. The electrode is made of a heat-resistant ohmic metal, and the gate electrode is characterized in that a portion in contact with the insulating film has a smaller diameter than other portions, and the manufacturing method thereof is a self-line type using a compound semiconductor. In the manufacturing method of a field effect transistor, after an active layer is formed on a substrate by ion implantation, a photoresist is applied to a portion where a gate electrode is to be formed, and a contact layer is ion-implanted using the photoresist as a mask material. After the implantation, there is a step of vapor depositing a heat-resistant ohmic electrode, a step of removing the heat-resistant ohmic electrode in the portion where the gate electrode is to be formed by lift-off to form a gate opening, and a step of depositing an insulating film on the gate opening. and forming a gate electrode made of a low-resistance metal so that the diameter in the gate opening is smaller than the diameter outside the gate opening.

[Effect]

Since the field effect transistor of the present invention has a self-line structure using a heat-resistant ohmic electrode, the source series resistance (R3) is small as in the conventional example, and moreover, the ion implantation when forming the active layer is The energy can be lowered and the transconductance (gl) is large. Furthermore, in the present invention, the length of the gate electrode is shortened due to the insulating sidewall formed at the gate flowering portion, so that the gate capacitance i1
(c,,) is small. Furthermore, in the present invention, since the gate electrode is finally formed after activation annealing, the material for the gate electrode can be freely selected and the gate metal resistance (R9) can be reduced. As a result, the noise figure (NF) of the microwave FET is significantly improved.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof.

FIG. 1 is a cross-sectional view of a field effect transistor according to the present invention, and numeral 1 in the figure is a GaAS substrate whose center portion is mesa-shaped. An active layer 2 is laminated on the upper surface of the mesa-shaped central portion of the GaAS substrate 1, and an n' contact layer 3 is laminated on the upper surface of the non-mesa-shaped portion of the GaAS substrate 1. A gate electrode 10 made of AI, which is a low-resistance metal, is laminated on the upper surface of the operating member N2, which has a cane-like shape in which the lower part has a smaller diameter than the upper part. Further, on the upper surface of the n' contact layer 3, a heat-resistant ohmic electrode 6 constituting a source/drain electrode is laminated, and an insulating film is formed between the heat-resistant ohmic electrode 6 and the lower part of the low abrasion resistance gate lid 10. A certain SiO□ film 7 is interposed.

The FTET of the present invention is configured as described above, and since the FET of the present invention has a self-line structure, the source series resistance (R1) is small and the mutual conductance (gl
) can be increased, and since the length of the gate electrode is short, the gate capacitance ffl (C,,) is small, and since the gate electrode is made of low resistance AI, the gate metal resistance (R9) is small. Therefore, in the present invention, The noise figure (NF) of a microwave FET is extremely small.

Further, since the low resistance gate electrode 10 and the n' contact layer 3 are only slightly separated by the sidewalls made of the SiO□ film 7, the gate breakdown voltage is good.

Next, a method for manufacturing a field effect transistor having such a structure will be explained based on FIG. 2, which schematically shows the manufacturing process.

First, as the n layer (active layer 2), the implantation energy was 30 KeV.
, selectively implant Si" ions at a dose of g 5 x l Q I Z cm-2, and pre-anneal at 50
Heat treatment is performed at 0°C (Fig. 2(a)). Next, a deep UV photoresist 9 such as PMMA (polymethylmethacrydoacide) is used as a gate electrode pattern.
．． Patterning is performed to a thickness of about 5 μm, and using this photoresist 9 as a mask material, an n-layer (n” contact layer 3) is implanted at an energy of 100 K eV and a dose of 2 x.
10′'' (Jl-2 tion was injected (Fig. 2(b)
)) After that, 5000 Ni/In/W films were applied as the heat-resistant ohmic electrode 6, and ECI? -313N by CVD method
Approximately 2,000 people were coated with a film 8 in this order (see Figure 2 (C)
)).

By lift-off of Deep UV photoresist 9,
Unnecessary portions of the Ni/In/W film and the 5iJ4 film are removed, and a gate electrode portion is opened. Then, PTA (short time lamp annealing) is performed to form the active layer 2 and the contact I.
! 3. Activate (850°C, 5 seconds) and perform ohmic alloying (Figure 2(d)).

Sin,
Form membrane 7 for 2,000 people. At this time, a little less than 2,000 SiO□ films 7 are grown on the side walls of the gate openings (see Fig. 2).
e)).

RIE using CF, +)12 (10%) gas
(activated ion etching) to remove the SiO□ film 7.
Eliminate over 000 people. In anisotropic etching by RIH, the SiO□ film is etched only in the vertical direction, so the SiO□ film formed on the top surface of the Si3N film 8
Only the film is removed, and the SiO□ film on the side wall of the gate opening remains without being etched (FIG. 2(f)). As a result, the width of the gate opening, which was previously 0.5 μm, has been reduced to 0.2~
It becomes 0.3 μm.

Next, a photoresist 9 is applied on the 5iJa film 8, and 1
．． An aperture with a width of 0 to 1.5 μm was formed overlapping the gate aperture, and an Al film was deposited by 7000 people (see Fig. 2).Finally, unnecessary portions of the AI film were removed by lift-off. After forming a low resistance gate electrode 10 using CF4 +0
Unnecessary portions of the 5fJa film 8 are removed by plasma etching using □ (15%) gas (FIG. 2(h)).

In the FET manufactured as described above, the gate electrode has a mushroom shape, and as mentioned above, the gate capacitance (C□) is small, and in this manufacturing method, the gate electrode is formed at the final stage. Therefore, it is not necessary to use a heat-resistant metal as the material for the gate electrode, and by using a low-resistance metal, the gate metal resistance (R, "
) can be made smaller.

Next, we will discuss the second embodiment of the present invention, that is, an LDD structure with a layer having a carrier concentration intermediate between the n-layer and the n-layer.
FET that forms (htly danoped danrain)
The manufacturing method will be explained based on FIG. 3, which schematically shows the process.

First, after selectively implanting ions as the n layer (active layer 2),
A 5iJ4 film 8 is laminated on the entire surface by the ECR-CVD method, and in order to selectively implant an n0 contact layer, a width of 3 μm is formed.
The photoresist 9 is patterned in the center over a certain extent (FIG. 3(a)). Then the implantation energy is 150
K eV, dose W, s XIO "am-" S
I1 ions are implanted through the Si3N film 8 to form an n++ contact I3 (FIG. 3(b)). After removing the 5iJa film 8 on the n+ contact layer layer by etching, a 50% Ni/In/W film is used as an ohmic electrode material.
The heat-resistant ohmic electrode 6 is formed by evaporation and lift-off (FIG. 3(C)).

Next, the gate electrode portion is patterned using a deep shift resist 9. Using this photoresist 9 as a mask material, the implantation energy was 100 K eV and the dose was 3.
12 x 101013a'' to form an n' layer 4 having a carrier concentration intermediate between the n layer and the n layer (FIG. 3(d)).
oo.

One Si3N4 film 8 is placed on 2,000 people (Fig. 3(e)
l).

After removing unnecessary portions of the AI film, Si3N, and film by lift-off of the photoresist 9, opening a hole in the gate electrode portion, and performing activation annealing, SiO2 is deposited on the gate electrode portion in the same manner as in the previous example. ! A side wall consisting of the film 7 is formed (FIG. 3(f)). Furthermore, after patterning the gate electrode part, depositing 7000 Ti/Pt/Au films, and forming the gate electrode 10 by lift-off, the unnecessary parts were removed.
The FET is obtained by sequentially removing the L film 12, Si, N, and films 8 (FIG. 3(g)).

FIG. 4 is a schematic diagram showing another embodiment of the manufacturing method of the present invention, specifically, steps of another method for forming a gate opening.

After ion implantation of the n layer (active layer 2), S is
iO□membrane 7 to 11! l'! It is formed by 5,000 people, and photoresist 9 is applied to the channel part (Fig. 4(a)).
).

Using the photoresist 9 as a mask material, the 5iOz film 7 is removed leaving the channel portion, and then this photoresist 9 is removed.
Using as is, the n' contact layer 3 and the heat-resistant ohmic electrode 6 are formed by lift-off (Fig. 4(b)).
. Next, the gate electrode portion is patterned using a deep UV photoresist 9, and an n' layer 4 is formed by ion implantation through the SiO□ film 7 (FIG. 4(C)).

Using this photoresist 9, a 5izN film 8 with a film thickness of about 500 mm was formed by the EcR-(:VD method.
Lift off. This allows the pattern of the gate portion to be reversed. After that, activation annealing treatment is performed (Fig. 4(d)
)). Using Si3N and film 8 as a mask material, CF4 +12
The 5in2 film 7 is removed by RIE using gas to form a gate opening (FIG. 4(e)).

After forming the gate opening, a side wall of the gate opening made of an insulating film and a gate electrode are formed in the same manner as in the first embodiment described above, thereby manufacturing an FET.

〔Effect of the invention〕

As described in detail above, according to the present invention, a field effect transistor having a self-line structure can be manufactured through easy steps.

In addition, gate capacitance can be reduced by shortening the gate length using sidewalls, and gate metal resistance can be reduced by using a low-resistance metal for the gate electrode, resulting in a microwave field-effect transistor with good noise characteristics. can.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a field effect transistor according to the present invention,
FIG. 2 is a schematic cross-sectional view showing the steps of the method for manufacturing a field effect transistor according to the present invention, FIGS. 3 and 4 are schematic cross-sectional views showing the steps of another embodiment of the manufacturing method of the present invention, Fifth
The figure is a cross-sectional view of a conventional field effect transistor. 1...GaAS substrate 2...Active layer 3...n contact layer 6...Heat-resistant ohmic electrode 7...S
iO□ film 8...Si3N, film 9...photoresist 10...low resistance gate electrode

Claims (1)

[Claims] 1. In a self-line field effect transistor in which an insulating film is interposed between a gate electrode and a source/drain electrode, the gate electrode is made of a low resistance metal, and the source/drain electrode is made of a low resistance metal. The field effect transistor is made of a heat-resistant ohmic metal, and the gate electrode has a smaller diameter at a portion in contact with the insulating film than at other portions. 2. In a method for manufacturing a self-line field effect transistor using a compound semiconductor, after forming an active layer on a substrate by ion implantation, applying a photoresist to a portion where a gate electrode is to be formed; After ion-implanting the contact layer using photoresist as a mask material, a process of vapor-depositing a heat-resistant ohmic electrode, and a process of removing the heat-resistant ohmic electrode in the area where the gate electrode is to be formed by lift-off to form a gate opening. forming a sidewall of an insulating film in the gate opening; forming a gate electrode made of a low-resistance metal so that the diameter in the gate opening is smaller than the diameter outside the gate opening; A method for manufacturing a field effect transistor, comprising the steps of: