JPH01293534A - Semiconductor integrated circuit layout method and semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve wiring efficiency between mega cells, to improve reliability in functions and to suppress an increase in the area of a chip by double disposing the input and output terminals of the cell on a plurality of sides of the cell. CONSTITUTION:The input and output terminals of a mega cell composed in combination of a plurality of standard cells are double disposed on a plurality of sides of the cell. For example, terminals for connecting the inner signal wirings ISPa ISPc of the mega cell 1 to other mega cell are double disposed on a plurality of sides of a rectangular region for defining the region of the cell 11. That is, as to the wiring ISPa, terminals Pa1 to Pa3 are provided on the three sides of the cell 1. As to signal wirings ISPc, terminals Pb1 to Pb3 are provided on the three sides of the cell 1. As to signal wirings ISPc, terminals Pc1 to Pc3 are provided on the three sides of the cell 1. As to the other cells 2, 3, input and output terminals are double disposed on a plurality of sides of the cell similarly to the cell 1.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit and its layout technology, and is a technology that is effective when applied to, for example, a building block type standard cell type semiconductor integrated circuit and its layout method. It is related to.

[Prior art]

A standard cell method for semiconductor integrated circuits is one of the means for improving the design efficiency of semiconductor integrated circuits and the versatility of basic circuit cells.

Conventionally, in this standard cell method, the minimum unit basic cells with logic functions such as simple logic gates and flip-flops are registered in advance in a library, and the basic cells registered in the library are combined according to the required specifications. This process forms semiconductor integrated circuits with various logical functions.

The inventor of the present invention particularly studied megacells with relatively large-scale logic such as LSI scale, and found that the megacells have different sizes and shapes depending on their logic scale, and that their signal terminals also vary. It is distributed on the four sides of the megacell. Therefore, megacells are laid out in a direction and arrangement that brings terminals that are logically closely related to each other to prevent increases in wiring length and wiring capacitance.
It was discovered that it is necessary to improve the reliability of the chip and reduce the chip area.

An example of a document describing the standard cell system is Nikkei Electronics JPI 65-P192, published by Nikkei McGraw-Hill on September 9, 1985.

[Problem to be solved by the invention]

However, due to the large logical scale of megacells, it is practically impossible to lay out multiple megacells with all logically related terminals close together, and some signal wiring between megacells There are quite a few things that must be routed around the circuit, which reduces the reliability of the LSI due to signal propagation delays and further increases the chip area.

An object of the present invention is to provide a semiconductor integrated circuit layout method that can improve wiring efficiency between megacells, improve functional reliability, and suppress increase in chip area. be.

Still another object of the present invention is to provide a semiconductor integrated circuit formed by the standard cell method, which has high functional reliability and suppresses increase in chip area due to unnecessarily long signal wiring.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a layout method is adopted in which the input terminals and output terminals of a megacell are overlapped on multiple sides of the megacell, as applied to the building block type star dart cell method, and in this case, the terminals overlapped on multiple sides. A semiconductor integrated circuit is formed by selectively using the terminals that provide the shortest distance between the megacells and wiring between the megacells.

[For production]

According to the above-mentioned means, in the wiring between megacells, unnecessary long signal wiring that detours around the megacells is eliminated, and in this case, the terminals between the megacells that are logically closely related are brought close to each other, and multiple megacells are connected. There is no need to pay special consideration to the layout, such as determining the orientation of the LS.
This suppresses a decrease in the reliability of I and an increase in chip area.

〔Example〕

FIG. 1 is a partial layout diagram of a semiconductor integrated circuit which is an embodiment of the present invention. The semiconductor integrated circuit shown in the figure is formed on one semiconductor substrate by a building block standard cell method, although this is not particularly limited.

FIG. 1 representatively shows three megacells 1, 2.3 formed by combining a plurality of A half cells. Each megacell 1, 2
．． 3 includes, but is not limited to, a microprocessor, a direct memory access controller, a bus controller, a memory ( RAM, ROM, EPROM, E
EPROM) LCD, A/D: 1 inverter, ○P7'/
It is considered to be a large-scale logic cell such as a loop.

For example, the megacell 1 whose internal configuration is shown in detail includes, but is not limited to, five cell blocks SBI to SB5.
including. Each cell block SBI to SB5 has an internal signal wiring line I typically shown inside the megacell 1.
They are connected by S P a = I S P c. The internal signal lines l5Pa to l5Pc are data signal lines, address signal lines, control signal lines, and the like.

In megacell 1, internal signal wiring l shown as a representative
Terminals for connecting 5Pa to I SPc with other megacells are arranged overlappingly on multiple sides of a rectangular area that defines the area of the megacell 1. According to Figure 1, the signal wiring l
For 5Pa, there are terminals Pa, ~Pa on the three sides of megacell 3.
, and for signal wiring l5Pb, megacell 3
Terminals pb□ to Pb3 are provided on three sides of the megacell 3, and for the signal wiring work SPc, terminals Pc1 to Pc1 are provided on three sides of the megacell 3.
Pc is provided.

Similarly to the megacell 1, the input terminals and output terminals of the other megacells 2 and 3 are arranged overlappingly on multiple sides of the megacell.

Wiring the signal lines in the wiring channel for interconnecting the plurality of megacells 1 to 3 having such terminal configurations according to a desired logical configuration is performed by selecting the shortest wiring from among the terminals overlapped on multiple sides of each megacell. This is done by selectively using terminals that measure distance.

For example, if the terminal Pa in the megacell 2 is to be coupled to the internal signal wiring l5Pa of the megacell 1, the terminal P
a is the terminal Pa closest to it.

join to. In addition, when terminal pb in megacell 2 should be connected to internal signal wiring l5Pb of megacell 1,
The terminal pb is coupled to the terminal Pb3 closest to it. Also, terminal Pc in megacell 3 is connected to megacell 1
When the terminal Pc is to be coupled to the internal signal wiring l5PC of the terminal Pc, the terminal Pc is coupled to the terminal Pc closest to the terminal Pc.

Suppose that the internal signal wiring IS P a - I S P c
As in the conventional case, the terminals related to P a, P bl, P c, at positions corresponding to one side of the megacell area
If this were the case, a long signal wiring would have to be formed in the signal wiring channel to bypass the megacell 1, as shown by the broken line.

According to the above embodiment, the following effects can be obtained.

(1) By arranging the input terminals and output terminals of megacells 1 to 3 overlappingly on multiple sides of the megacell, the length of signal wiring between the megacells can be easily minimized.

(2) As a result of the above effects, signal propagation delays between megacells can be minimized, and the reliability of semiconductor integrated circuits can be improved. Furthermore, since the wiring area for interconnecting the megacells is also reduced, the chip area can be reduced.

(3) According to the above-mentioned effect (2), when obtaining a semiconductor integrated circuit by the building block type standard cell method, design efficiency and wiring efficiency can be improved. Moreover, the megacell itself can be registered in the library as a standard cell, making it easier to use it for general purposes.

Although the invention made by the present inventor has been specifically explained based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof.

For example, in the above embodiment, input terminals and output terminals of the megacell are provided redundantly on three sides, but they may be provided redundantly on two or four sides depending on the size and shape of the megacell.

In the above explanation, the invention made by the present inventor was mainly applied to a building block type standard cell system, but the present invention is not limited thereto, and the present invention is not limited to this, but can also be applied to a semiconductor integrated circuit by combining megacells. The present invention, which can be applied to various semiconductor integrated circuit technologies employing design techniques, can be applied to conditions where a megacell formed by combining at least a plurality of standard cells is used as a result.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, by overlappingly arranging the input terminals and output terminals of a megacell on multiple sides of the megacell, unnecessary long signal lines that bypass the megacells can be eliminated in the wiring between the megacells.

In this case, LSI reliability can be reduced due to signal propagation delay between megacells without taking special consideration such as laying out multiple megacells in a direction that allows the terminals of megacells that are logically closely related to each other to be close to each other. This has the effect of easily suppressing an increase in chip area.

[Brief explanation of the drawing]

FIG. 1 is a partial layout diagram of a semiconductor integrated circuit which is an embodiment of the present invention. 1 to 3... Mega cell, S81 to SBS... Cell block, l5Pa to l5Pc... Internal signal wiring, Pa,
~Pa,...terminal of megacell 1, Pb2~Pb,...
・Megacell 1 terminal, Pc ~ Pc,...Megacell 1
Terminals, Pa, Pb... Terminals of Megacell 2, Pc...
・Megacell 3 terminal. Figure 1

Claims (1)

[Claims] 1. A layout method for a semiconductor integrated circuit, characterized in that input terminals and output terminals of a megacell formed by combining a plurality of standard cells are arranged overlappingly on a plurality of sides of the megacell. 2. The semiconductor integrated circuit according to claim 1, wherein wiring between megacells is performed by selectively using terminals that take the shortest distance from among terminals arranged overlappingly on a plurality of sides. layout method. 3. A semiconductor integrated circuit formed by the semiconductor integrated circuit layout method according to claim 2.