JPH01291538A - Frame synchronization device - Google Patents

Abstract

PURPOSE:To remarkably shorten an asynchronous constinuation time by constituting a device so as to provide a frame counter and a hunting counter simultaneously. CONSTITUTION:In a synchronous state, the internal state of the frame counter 112 coincides completely with that of the hunting counter 113, and they output frame synchronizing pulses at the same cycles. When an asynchronous state is generated due to an unknown factor and it is judged that the asynchronous state of a preceding protection counter 108 is generated. it is necessary to perform a hunting operation by the frame counter 112, however, the frame counter 112 performs no direct hunting of the frame synchronization pattern, and opens a gate 110, and waits until the output of a succeeding protection counter 109 goes to '1', and when the output of the gate 110 goes from '0' to '1', the internal state of the hunting counter 113 is fetched in the frame counter 112, then, frame synchronization can be secured.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a frame synchronization system, and particularly to a backbone transmission system.
The present invention relates to a frame synchronization device used in digital transmission systems such as public networks and subscriber systems.

(Prior Art) A frame synchronization device is being considered as a method for ensuring/maintaining frame synchronization in a time division multiplexed digital transmission system.

FIG. 4 is a circuit block diagram showing an example of a conventional frame synchronization device used in the digital transmission system. The figure uses a reset method as a synchronization protection circuit, and
1 is a data input line, 402 is a clock input line, 403 is a frame pattern detection circuit, 404 is a coincidence gate, 40
5 is a mismatch gate, 408 is a synchronization protection counter, 411
is a clock control gate, 412 is a frame counter, 4
18 is a frame synchronization pulse (FSYN) output line.

Here, the clock signal input from the clock input line 402 and the data signal input from the data input line 401 are as follows.
It is assumed that they have the same repetition period and that bit synchronization is ensured. Regarding this technology, see "Practical Application of 400M Multiplex Conversion Device" published by Kouhei Otake et al. in Research and Practical Application Report Volume 25, No. 1, 1978, or
“Considerations on the design method of frame synchronization protection circuits” published by Rikio Maruta in the Journal of the Institute of Electronics and Communication Engineers in 1972
'It is described in.

The frame pattern detection circuit 403 is connected to the data input line 401
Detects the frame synchronization pattern supplied from
The results are sent to match gate 404 and mismatch gate 405. The frame counter 412 counts clock signals input from the clock input line 402 via the clock control gate 411 and outputs a frame synchronization pulse in synchronization with the frame synchronization pattern. Furthermore, this frame synchronization pulse is applied to the match gate 404 and the mismatch gate 405.
supplied to The synchronization protection counter 408 is a counter for maintaining the synchronization state even if a bit error occurs in the frame pattern despite the synchronization state, and is usually called a synchronization protection counter and has forward protection and backward protection states. The figure shows an example in which the number of forward protection stages is N and the number of backward protection stages is 2M, and it is determined that an out-of-synchronization state has occurred for the first time when no matching frame pattern is detected between consecutive N frames. In the synchronous state, the output of the coincidence gate 404 becomes the reset signal for the internal state of the synchronous protection counter 408, the mismatch gate 405 becomes the clock input signal of the synchronous protection counter 408, and in the asynchronous state, the synchronous protection counter 408 becomes the output signal of the coincidence gate 404. Count. The clock control gate 411 has a clock input a402.
The clock signal input from the frame counter 412
is supplied to.

In the following, the synchronous state and the asynchronous state will be explained in this order.

In the synchronous state, the output of the coincidence gate 404 is a frame pulse, and the output of the mismatch gate 405 is '0'.

In other words, the synchronization protection counter 408 is reset every frame period, and its output becomes "0". This state is the forward protection state, and the clock control gate 41 at this time
1 is in the open state, so the clock signal input from the clock input line 402 is directly sent to the frame counter 412.
supplied to The frame counter 412 generates a frame synchronization pulse according to this input clock, and confirms that frame synchronization is maintained.

On the other hand, in the asynchronous state, even if the frame pattern detection circuit 403 detects a frame pulse, the coincidence gate 403
The output of the synchronization protection counter 408 becomes "0'', and the frame synchronization pulse is output from the mismatch gate 405. When the frame synchronization pulse is supplied N consecutive times from the mismatch gate 405, the output of the synchronization protection counter 408 becomes <1111, and the clock The control gate 411 is closed. Therefore, the clock signal from the clock input line 402 is no longer supplied to the frame counter 412. This closed state of the clock control gate 411 means that the frame pattern detection circuit 408 is used for frame synchronization. This continues until a pattern is detected.In other words, it becomes a frame synchronization pattern hunting state.When the frame pattern detection circuit 403 detects a frame synchronization pattern and its output becomes "1", the match gate is activated.

The output of 404 becomes "1", and the synchronization protection counter 408
opens the clock control gate 411. As a result, a clock signal is supplied to the frame counter 412 again, ensuring frame synchronization and entering the backward protection state. In other words, the synchronization protection counter 408 is
Start counting the frame synchronization clock supplied from In the backward protection state, when frame synchronization pulses are continuously supplied to the synchronization protection counter 408 M times, it is determined that frame synchronization is secured and the forward protection state is entered. However, if the supply of frame synchronization pulses is less than M consecutive times, immediately enters the hunting state.

As described above, it is possible to realize a frame synchronization circuit that suppresses falling into a frame synchronization state erroneously in a synchronization hunting state.

(Problems to be Solved by the Invention) In the conventional frame synchronization method shown in FIG. Hunting of one frame length is required. Furthermore, the determination of synchronization recovery is made after the backward protection counter has counted up in order to reduce the possibility of erroneously performing synchronization pull-in. For this reason, in high-speed or long-frame transmission systems, a large amount of information is lost, and a method for recovering synchronization faster is required.

An object of the present invention is to provide a frame synchronization method that solves these problems and can reduce the asynchronous duration to substantially zero.

(Means for Solving the Problems) The frame synchronization method of the first invention includes a frame pattern detection circuit that detects a frame synchronization pattern from a received signal, and a first circuit that counts received clocks and generates a frame signal.
a frame counter, a second frame counter for synchronization hunting that counts the received clock, a first frame signal output from the first frame counter, and a frame synchronization signal output from the frame pattern detection circuit. a first gate which receives the above-mentioned signals and outputs a first coincidence signal when both signals are in the same phase; and a second gate which receives the above-mentioned two signals and outputs a first mismatch signal when the two signals have different phases inputs a second frame signal output from the second frame counter and a frame synchronization signal output from the frame pattern detection circuit, and outputs a second coincidence signal when both signals are in phase. a fourth gate that receives both of the signals and outputs a second mismatch signal when the phases of the two signals are different; and a fourth gate that counts the first match signal and the first mismatch signal. a first synchronization protection counter that outputs an out-of-synchronization signal when the counted value exceeds a predetermined number; and a first synchronization protection counter that counts the second coincidence signal and the second mismatch signal and whose counted value is a predetermined number. a second synchronization protection counter that outputs a synchronization acquisition signal when the synchronization acquisition signal is exceeded; and a fifth gate that receives the outputs of the first and second synchronization protection counters; It is comprised of a sixth gate that stops the counting operation of the second frame counter, and the first frame counter stores the counted value of the second frame counter according to the fifth gate output signal. shall be.

Further, the frame synchronization device of the second invention includes a frame pattern detection circuit that detects a frame synchronization pattern from a received signal, a first frame counter that counts a received clock and generates a frame signal, and a first frame counter that counts the received clock and generates a frame signal. a second frame counter for synchronous hunting;
a first frame signal output from the first frame counter and a frame synchronization signal output from the frame pattern detection circuit; a second gate that receives both the signals as input and outputs a first mismatch signal when the phases of the two signals are different; a second frame signal output from the second frame counter and the frame pattern; A third gate receives the frame synchronization signal output from the detection circuit and outputs a second coincidence signal when both signals are in the same phase; a fourth gate that outputs a mismatch signal; and a first synchronization protection that counts the first match signal and the first mismatch signal and outputs an out-of-synchronization signal when the counted value exceeds a predetermined number. a counter; a second synchronization protection counter that counts the second coincidence signal and the second mismatch signal and outputs a synchronization acquisition signal when the counted value exceeds a predetermined number; A fifth gate receiving the synchronization protection counter output, a selection circuit outputting either the first frame signal or the second frame signal according to the output of the fifth gate, and the second mismatch signal being supplied. The first frame counter is configured to include a sixth gate that stops the counting operation of the second frame counter during the period of time, and initializes the first frame counter according to the output of the selection circuit (Embodiment) Next, the present invention will be explained with reference to FIGS. 1 to 3. FIG. 1 is a block diagram showing an embodiment of the frame synchronization device of the present invention, in which 101 is a data input line, 102 is a clock input line, 103 is a frame pattern detection circuit,
104.106 is a coincidence gate, 105.107 is a mismatch gate, 108 is a forward synchronization protection counter, 109 is a backward protection counter, 110 is a gate, 111 is a clock control gate, 112 is a frame counter, 113 is a hunting counter, 118 is a frame Synchronous pulse (FSYN
) is the output line. Here, it is assumed that the clock signal input from the clock input line 102 and the data signal input from the data input line 101 have the same repetition period and bit synchronization is ensured.

The frame pattern detection circuit 103 is connected to the data input line 101
Detects the frame synchronization pattern supplied from
The results are transmitted to the matching game (104.106) and the mismatching gate 105.107. Frame counter 112
The hunting counter 113 counts the clock signal input from the clock input line 102 via the tally control gate 111, and the hunting counter 113 counts the clock signal input from the clock input line 102 via the tally control gate 111, and counts the clock signal input from the data input line 101. A frame synchronization pulse is output for each frame synchronization pattern period inserted in the signal. The frame synchronization pulse output from the frame counter 112 is supplied to the coincidence gate 1o4 and the mismatch gate 105,
The frame synchronization pulse output from hunting counter 113 is supplied to coincidence gate 106 and mismatch gate 107. The forward synchronization protection counter 108 is a counter that maintains the synchronization state even if a bit error occurs in the frame pattern despite the synchronization state, and the backward protection counter 109 suppresses erroneous synchronization acquisition when the frame synchronization pattern is hushing. The power to do it is unta. In the figure, the operation of the frame synchronization device will be described assuming that the number of forward protection stages is N, the number of backward protection stages is M, and a reset method is adopted as the counter method.

The forward protection counter 108 counts the output signal of the mismatch gate 105 while using the output signal of the coincidence gate 104 as a reset signal, and the backward protection counter 109 counts the output signal of the mismatch gate 105.
The coincidence gate 10 uses the output signal of 07 as a reset signal.
6 output signals are counted.

In the following, the noting process will be explained in the order of synchronous state and asynchronous state.

In the synchronized state, the internal states of the frame counter 112 and the hunting counter 113 are exactly the same,
Output frame synchronization pulses at the same cycle. A frame pulse appears at the output of the match gates 104 and 106, and "0" appears at the output of the match gates 105 and 107. That is, the forward synchronization protection counter 108 is reset every frame period, and its output becomes 0''', and the backward protection counter 109, which is supplied with a pulse every frame period, counts up and outputs 111+1. This state is a forward protection state, and this state is maintained until the forward protection counter 108 is supplied with a frame synchronization pulse from the mismatch gate 105 N times in a row.

In the asynchronous state, even if the frame slam detection circuit 103 detects a frame pulse, the outputs of the coincidence gates 104 and 106 become "0", and the mismatch gate 105 outputs a frame synchronization pulse. The forward protection counter 108 continues counting until N consecutive frame synchronization pulses are supplied from the mismatch gate 105. The output of the mismatch gate 107 also changes from "(01' to par1')" due to the mismatch detection, and the clock control gate 111 is closed, so that the hunting counter 113 is no longer supplied with the clock signal from the clock input line 102. The backward protection counter 109 is reset.This clock control gate 1
The closed state of No. 11 continues until the frame pattern detection circuit 103 detects a frame synchronization pattern. This is the frame synchronization pattern hunting state.

When the frame pattern detection circuit 103 detects a frame synchronization pattern and its output becomes "1", the output of the mismatch gate 107 changes from "1" to "0"', and the clock control gate 111 is opened and hunting is started. The clock signal is supplied to the counter 113 again, and the hunting counter 113 finishes hunting for the frame synchronization pattern. At the same time, the backward protection counter 109 counts the frame synchronization pulses supplied from the coincidence gate 106, and enters the backward protection state. When the backward protection counter 109 counts up, it is determined that the hunting counter 113 has successfully captured frame synchronization,
The output is set to P1'' to open the gate 110. The forward protection counter 108 falls into an unsynchronized state for some reason.
If it is determined that the frame is in an asynchronous state, the frame counter 1
08 needs to perform a hunting operation, but the frame counter 112 does not directly perform frame synchronization pattern hunting. In other words, open the gate 110, wait for the output of the backward protection counter 109 to become 11111, and only when the output of the gate 110 changes from 0'' to 1'' will the internal state of the hunting counter 113 be imported into the frame counter 112. Ensure frame synchronization.

FIG. 2 is a block diagram showing an embodiment of the frame synchronization device of the present invention, in which 201 is a data input line, 202 is a clock input line, 203 is a frame pattern detection circuit, and 20
4.206 is a coincidence gate, 205.207 is a mismatch gate, 208 is a forward synchronization protection counter, 209 is a backward protection counter, 210 is a gate, 211 is a clock control gate, 212 is a frame counter, 213 is a hunting counter, 214 is a selector , 218 is a frame synchronization pulse (FSYN) output line. In the figure, the operation of each circuit except for the selector 214 is the same as in FIG. The frame counter 212 is initialized by selecting one of the frame synchronization pulses. In the synchronous state, the frame counter 212 initializes its internal state with the frame synchronous pulse that it outputs, and in the asynchronous state, it synchronizes by initializing it with the frame synchronous pulse that is the output of the hunting counter 213, which has already completed synchronization acquisition. return to the state.

FIG. 3 is a block diagram showing an embodiment of the frame synchronization device of the present invention, in which 301 is a data input line, 302 is a clock input line, 303 is a frame pattern detection circuit, and 30
4.306 is a layer gate, 305.307 is a mismatch gate, 308 is a forward synchronization protection counter, 309 is a backward protection counter, 310 is a gate, 311 is a clock control gate, 312.313 is a frame counter, and 315 is a divide-by-2 circuit. , 316 and 317 are 2×2 switches, and 318 is a frame synchronization pulse (FSYN) output line. In the figure, frame counters 312 and 313 alternately operate as a frame synchronization counter and a hunting counter. This switching is performed by switches 316 and 317 whose control signal is the output of a divide-by-2 circuit 315 that divides the output of the gate 310 by two.

In the embodiments shown in FIGS. 1 to 3, the case where the reset method is used as the operation method of the synchronization protection counter has been explained as an example, but the present method is limited to these configurations. Instead, for example, a configuration in which a conflict counter method is used as the operation method of the synchronization protection counter is also possible.

(Effects of the Invention) As explained above, the present invention has a configuration in which a frame counter and a hunting counter are provided at the same time. This eliminates the need to enter the hunting or rearward protection state after determining the asynchronous state, and as a result, the asynchronous duration time can be significantly shortened. Assuming that the forward protection counter = N and the backward protection counter = M, and a frame synchronization button is always inserted for each frame, the worst time required from when it becomes out of sync for some reason until it is determined to be in sync is: , effectively zero if N>M, M- if N5M
This has the effect of resulting in N+1 frames. The frame synchronizer of the present invention relates to a timing method in a digital transmission system, and is expected to be applied to digital transmission systems with higher speed and larger capacity in the future. LC and LSI can be easily achieved by using integration technology represented by .

[Brief explanation of the drawing]

1 to 3 are block diagrams showing an embodiment of the frame synchronization device of the present invention, and FIG. 4 is a circuit block diagram showing an example of a conventional frame synchronization device. In the figure, 103... frame pattern detection circuit;
104, 106... Match gate, 105.107...
- Mismatch gate, 108... Forward synchronization protection counter,
109... Backward protection counter, °110... Gate, 111... Clock control gate, 112... Frame counter, 113... Hunting counter, 2
03...Frame pattern detection times 1204, 206.
...-matching gate, 205.207...unmatching gate,
208... Said synchronization protection counter, 209... Backward protection counter, 210... Gate, 211... Clock control gate, 212... Frame counter, 21
3... Hunting counter, 214... Selector, 303... Frame pattern detection circuit, 304.3
06...-matching gate, 305.307...mismatching gate, 308...forward synchronization protection counter, 309...
- Rear protection counter, 310-0. Gate, 311 clock control gate, 312.313...frame counter, 315...2 frequency divider circuit, 316.317...2
X2 switch, 40300. Frame pattern detection circuit, 404... - match gate, 405... mismatch gate, 408... synchronization protection counter, 411... clock control gate, 412... frame counter.

Claims (2)

[Claims] (1) A frame pattern detection circuit that detects a frame synchronization pattern from a received signal, a first frame counter that counts received clocks and generates a frame signal, and a second frame for synchronization hunting that counts the received clocks. A counter receives a first frame signal outputted from the first frame counter and a frame synchronization signal outputted from the frame pattern detection circuit, and outputs a first coincidence signal when both signals are in phase. a first gate; a second gate that receives both of the signals and outputs a first mismatch signal when the phases of the two signals are different; and a second frame signal output from the second frame counter; The frame synchronization signal output from the frame pattern detection circuit is input, and when both signals are in the same phase, the second
a third gate that outputs a coincidence signal of the first coincidence signal; a fourth gate that receives both of the above signals and outputs a second mismatch signal when the phases of the two signals are different; a first synchronization protection counter that counts mismatch signals and outputs an out-of-synchronization signal when the counted value exceeds a predetermined number; a second synchronization protection counter that outputs a synchronization acquisition signal when a predetermined number is exceeded; a fifth gate that receives the outputs of the first and second synchronization protection counters; and a fifth gate that is supplied with the second mismatch signal. The second frame counter is configured with a sixth gate that stops the counting operation of the second frame counter while the count value of the second frame counter is A frame synchronization device characterized by storing. (2) A frame pattern detection circuit that detects a frame synchronization pattern from a received signal, a first frame counter that counts received clocks and generates a frame signal, and a second frame for synchronization hunting that counts the received clocks. A counter receives a first frame signal outputted from the first frame counter and a frame synchronization signal outputted from the frame pattern detection circuit, and outputs a first coincidence signal when both signals are in phase. a first gate; a second gate that receives both of the signals and outputs a first mismatch signal when the phases of the two signals are different; and a second frame signal output from the second frame counter; The frame synchronization signal output from the frame pattern detection circuit is input, and when both signals are in the same phase, the second
a third gate that outputs a coincidence signal of the first coincidence signal; a fourth gate that receives both of the above signals and outputs a second mismatch signal when the phases of the two signals are different; a first synchronization protection counter that counts mismatch signals and outputs an out-of-synchronization signal when the counted value exceeds a predetermined number; a second synchronization protection counter that outputs a synchronization acquisition signal when a predetermined number is exceeded; a fifth gate that receives the outputs of the first and second synchronization protection counters; The circuit includes a selection circuit that outputs either the first or second frame signal, and a sixth gate that stops the counting operation of the second frame counter while the second mismatch signal is supplied. , a frame synchronization device characterized in that the first frame counter is initialized according to the output of the selection circuit.