JPH01289281A - gate protection circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a protection circuit for MO, S, and type gates, and particularly to a protection circuit for gates to which voltage signals in both positive and negative directions are applied to the substrate.

<Prior Art> In a normal MO8 type circuit, the voltage signal applied to the gate is unipolar with respect to the substrate, and the construction of the protection circuit is easy. For example, in the case of an N-channel MOS gate on a P-type substrate, as shown in Figure 3, a diode (in this case Threshold value VD.), and signal line■
0, that is, (-1v<)-Vp, is achieved by connecting switching elements in parallel whose threshold value is VTo.
□kv. In the normal operating range <vTo, no static current flows and v6 -VD. Both positive and negative directions are protected against excessive currents such as and V6>voo.

In addition to the gate promoted avalanche breakdown element shown in FIG. 3, the switch elements include a punch-through transistor and a field inversion transistor.

There are many possibilities, such as an avalanche breakdown diode.

However, the voltage applied to the gate may extend in both positive and negative directions with respect to the substrate. - As an example, consider the case of a charge-coupled device (CCI), which is a type of MO3 type structure.

Recently, CCD has often used an embedded type with high transfer efficiency. In this case, the relationship between the maximum potential Itm and the gate voltage VG is as shown in FIG. Here, we will consider the case where the signal charge is an electron, and therefore the case where a transfer channel is formed by an N layer on a P substrate. From this v6=O
The potential is already a positive value at v, and VG=V
- An inversion layer (a layer in which a large number of holes are formed) is formed on the semiconductor surface, and vo decreases below this level and the mohotential does not change. When the low level voltage vL of CCD transfer lock is near fv,in, the semiconductor surface is covered with an inversion layer and becomes inactive at least during the low level period, so the generation of dark current is suppressed.Therefore, vL""pin This is often the case. In this case, it is clearly 0. On the other hand, the transfer lock high level voltage vH is often set to vH>0 because the larger the clock amplitude VH-V, the larger the maximum transfer charge amount. In this way, N on the P substrate
Even though it is a channel type MOS gate, the signal amplitude applied to the gate spans both positive and negative directions.

Conventionally, a protection circuit for such cases has not been included, or a circuit as shown in FIG. 5 has been used. That is, the main body P substrate is replaced with the first well on the N substrate, a second P well is formed separated from the IP well, and V and a lower voltage -vA are externally applied to the second P well.

The same protection circuit as the conventional one is placed on this second P-well. This ensures that v6 operates from -vA-vDo to vTo-vA.

<Problems to be Solved by the Invention> However, in this case, it does not sufficiently protect against electrostatic surge voltages and the like. This is because the -vA terminal is grounded (GND) until it is connected to an external power supply with a sufficient internal resistance.
It is open to the terminal.

At this time, a large surge voltage with respect to the GND terminal
If a surge charge is applied to the terminal, the protection circuit will not be able to release the surge charge and it will be applied directly to the gate.

The present invention has been devised in view of the above-mentioned problems, and provides a gate protection circuit that functions satisfactorily even when signal voltages in both positive and negative directions are applied to a MOS type gate with reference to a region corresponding to the substrate. It is.

Means for Solving Problems〉 According to the present invention, a first well of a second conductivity type is formed on a semiconductor substrate of a first conductivity type, and the well is connected to a ground voltage and is formed on the well. In a circuit in which a voltage signal of both positive and negative polarities is applied to a gate of a MOS type, a second well of a second conductivity type is formed on the substrate and separated from the first well, and a second well is formed on the first well. The signal line of one of the gates has a first protection circuit including a diode on the second well while reaching the pad terminal, and the signal line for applying the first well voltage (ground voltage) is also connected to the pad terminal. A gate protection circuit is configured by providing a second protection circuit including a diode on the grI2 well or on a third well electrically connected to the second well. Further, the first protection circuit includes a resistor, a first diode, and a first switch element whose threshold value when the diode is reversely polarized is higher than the gate signal voltage in the polarity, and the first
The diode and the first switch element are connected in parallel between the gate signal line and the second well, and the resistor is connected between the gate signal line and the hat terminal, and the second protection The circuit includes a second diode and a second switch element whose threshold value when the diode is in reverse polarity is higher than the gate signal voltage in the polarity,
and the second diode and the second switch element are connected to the first diode and the second switch element.
A gate protection circuit is configured by connecting in parallel between the well signal line and the second to third wells.

<Embodiment> FIG. 1 shows an embodiment in which the present invention is applied to an N-channel MOS gate (including a CCD whose charge is electrons). The gate to be protected is formed on the first P well on the N substrate, and the first well voltage is the ground voltage (
GND).

Next, a second P well is formed on the N substrate at a location separated from the IP well. A first protection circuit is formed between the gate terminal V6 and the second well. That is, when viewed from the v6 terminal, the following two elements are first connected in parallel to the second P well via the resistor R1t'. The - element is a diode DI whose forward direction is on the gate signal line e side, and the other element is a switch element T1 whose threshold value is higher than the positive gate signal voltage when the gate signal line is on the e side. Figure 1 (
In a), an example of a gate-facilitated avalanche breakdown device is shown. The second protection circuit is formed by connecting the following two elements in parallel between the first P-well voltage supply line (CGND line) and the second P-well. One element is a diode D2 whose forward direction is GND@e11111.
, the other element is a switch element T2 whose threshold value is higher than the absolute value of the negative side gate signal voltage when the GND line is set to the ■ side, and T2 is a gate-promoted avalanche breakdown element like T1 in FIG. 1(a). Here is an example. Furthermore, the second
The P-well voltage line (PW) does not need to be externally connected.

In the above circuit configuration, the gate terminal voltage v6 and the current voltage. The relationship shown in FIG. 1(b) is obtained. First, by increasing v6 in the positive direction, the threshold value vT8 of Tl and D
Sum of forward threshold value vD2 (usually less than +v) of l V□1
The current increases rapidly when it exceeds +vo2. Then in the negative direction v
As the absolute value of 6 increases, the threshold value V of T2. 2 and D
In the order of l, the direction threshold Vn1 ((1v) (7) sum v
The current increases sharply in the negative direction when T2+vD1 is exceeded. Therefore, normal operation is guaranteed between −(vT2+vD1) and V<(v11+vD2), and even if surge voltage in both positive and negative directions is applied to the v66 terminal, at gate terminal point A, the voltage is greater than or equal to (vTl+■D2) and −(vo2+vD1). ) or below, the increase in the absolute value of chisel pressure will be suppressed. In other words, it functions satisfactorily as a protection circuit.
An example of the cross-sectional configuration in case a) is shown.

In the above explanation, the case where the second protection circuit is located on the same well (second P well) as the first protection circuit is taken as an example, but it is assumed that the second protection circuit is located on the third P well, which is different from the IP well and the second P well. It is clear that the same applies even when the second P well is formed as long as it is connected to the second P well. Further, as the switching elements T+ and Tz, other than gate-promoted avalanche breakdown devices P and D, other elements such as punch-through transistors, field inversion transistors, avalanche breakdown diodes, etc. can be used.

Effect> As explained above, even when the gate signal voltage extends in both positive and negative directions with respect to the substrate equivalent region of the MO3 type gate, the threshold voltage of the switching element is adjusted to the absolute value of the gate signal voltage in both the positive and negative directions in the present invention. By appropriately setting the value to a value slightly higher than the value and sufficiently low to protect the gate, the gate can be protected against electrostatic surge voltages in both positive and negative directions.

Moreover, the circuit configuration is apparently simple, with all the protection circuits being inserted into the ground voltage line, and there is also the advantage that the second P-well voltage terminal, which was conventionally used as an external terminal, is not required.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the gate protection circuit of the present invention, (a)
is a circuit diagram, (b) is an operating characteristic diagram, Fig. 2 is a cross-sectional configuration diagram for the case of Fig. 1 (a), and Fig. 3 is a conventional gate protection circuit when the gate applied voltage is unipolar. , (a) shows the circuit diagram, (a) shows the operating characteristic diagram, Fig. 4 shows the relationship between the gate voltage and the maximum potential of a buried channel type CCD whose charge is electrons, and Fig. 5 shows the relationship between the gate voltage and the maximum potential when the gate applied voltage is bipolar. A conventional gate protection circuit diagram is shown in the case of . "l + T2: Switch element Dt + D
2: Diode. Agent Patent attorney Takeshi Sugiyama (1 other person) (a) (b
) Figure 1 Ka 2

Claims (1)

[Claims] 1. A first semiconductor substrate of a second conductivity type on a semiconductor substrate of a first conductivity type.
In a circuit in which a well is formed, the well is set to a ground voltage, and a voltage signal having both positive and negative polarities is applied to a MOS type gate formed on the well, a second conductivity type is formed on the substrate. a second well is formed separated from the first well, and the gate signal line on the first well is provided with a first protection circuit including a diode on the second well while reaching the pad terminal, and The signal line for applying the first well voltage (ground voltage) also includes a second protection circuit including a diode on the second well or on the third well electrically connected to the second well while reaching the pad terminal. A gate protection circuit characterized by: 2. The first protection circuit includes a resistor, a first diode, and a first switch element whose threshold value when the diode is reverse polarized is higher than the gate signal voltage in the polarity, and the first diode and a first switch element are connected in parallel between the gate signal line and the second well, and a resistor is connected between the gate signal line and the pad terminal, and the second protection circuit is a second diode and a second switch element whose threshold value when the diode is in reverse polarity is higher than the gate signal voltage in the polarity, and the second diode and the second switch element are connected to the first well signal Claim 1, characterized in that the wire is connected in parallel between the line and the second well to the third well.
Gate protection circuit described in section.