JPH01288007A - Master slave flip-flop circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a master-slave type flip-flop circuit having a function of setting and resetting the latch state of a signal in the circuit, and which eliminates the adjustment resistor in series with the output transistor. The master side circuit consists of a pair of differential transistors connected vertically between source buses, with the aim of providing a master-slave type flip-flop circuit that ensures set/reset functions and can operate reliably. (MST> and the slave side circuit (SLB) are connected to the output transistor (T 14.
s), and the master side circuit (MS
a circuit (SET-R, BSET) that sets and resets the signal latch state in the master side circuit (MST); and a level shift resistor (R1) that lowers the power supply voltage to the differential transistor pair in the master side circuit (MST). In a master-slave type flip-flop circuit that operates with a small amplitude logic signal, the level shift resistor (R1) is set to a value that satisfies the following relationship.

[Industrial application field]

The present invention relates to a master-slave type flip-flop circuit having a function of setting and resetting the latch state of a signal within the circuit.

The master-slave type flip-flop circuit is a flip-flop configured in two stages so that the input signal logic is not output as it is as an output signal logic change. This flip-flop circuit is composed of a master side circuit on the input side and a slave side circuit on the output side. Master-slave type flip-flops are used in various digital circuits and are used in system construction in the form of integrated circuits, but depending on the system, the flip-flops may be used for initialization after being incorporated into the system, or at the necessary timing. It is necessary to set and reset the signals within the group. Therefore, a master-slave type flip-flop circuit having a set/reset function is used.

[Conventional technology]

Figure 2 shows a conventional vertical stacking type B CL (Eiitter
An example of a master-slave type flip-flow 71 circuit using a Cou-pled Logic circuit is shown. Here,
Vertical stacking type means that the differential transistor pair is connected to the power supply bus GND -
711 is a circuit type configured in a state in which multiple stages are vertically stacked.

This master-slave type flip-flop circuit consists of a master side circuit MST and a slave side circuit SLB.

The master side circuit MST is placed at the input stage, and once latches the input signal logic, transmits it to the slave side circuit SLB at the output stage, and outputs the output terminal X of the slave side circuit SLB.
Output from X. Note that, since the present invention particularly relates to improvement of the master side circuit, a description of the slave side circuit SLB will be omitted.

The master side circuit MST described above has a small amplitude logic signal (for example, H=-0, 9V) for high-speed operation.

The voltage level of each part is set to operate at L=-1.8V).

Next, the latch operation and reset operation of the above master-slave type flip-flow 71 circuit will be explained.

When the clock CK is at the "L" level, a data signal is input to the input terminal of the transistor T4, and if the logic of the data D is higher than the reference n signal V of the transistor T5 (D, = "H"). is trer
i In transistor T4 is turned on. As a result, the current path is power supply GND → level shift resistor r1 → voltage dividing resistor r → transistor T4 → transistor T → transistor T →
It is formed by the path of the power supply vEE.

At this time, the connection point between the voltage dividing resistor (resistance that determines the amplitude of the circuit) r and the collector of the transistor T4 becomes "L" level. Conversely, the connection point between the voltage dividing resistor (resistance that determines the amplitude of the circuit) r and the transistor T5 becomes "H" level. This "H level" causes the output transistor T15 to go "H".
is transmitted, and the base of the latch transistor T9 becomes "H" level, so the latch transistor T9 is turned on. At this time, when the tarlock CK becomes "H" level, the transistor T11 is turned on. As a result, the current path is power supply GND → level shift resistor r1 → voltage dividing resistor r →
It is formed in the path of latch transistor T9 → transistor T11 → transistor T12 → power supply "EE". By forming this current bus, the "H" level of input data Din is latched, and after that, regardless of the presence or absence of input data,
The "H" level is maintained.

Next, the reset operation will be explained. When attempting to reset the “H” level signal held as described above, “
Give a reset signal R85et of "H" level.
The transistors T7 and T11 are forcibly turned on by the reset signal Re5et at the H" level. As a result, the power supply GND→level shift resistor r1→voltage dividing resistor r3→transistor T7→transistor T11→transistor TI
A current path of 2→power supply VEE is formed. In this way, the logic of the latched H level, that is, the logic at the connection point between the voltage dividing resistor r3 and the transistor T5 is reversed from "H" to "L".

Then, the output transistor T15 transmits "L" and the transistor T9 turns off. On the other hand, the output transistor T14 transmits "H".

Then, the transistor T6 is turned on to maintain the reset state. This completes the reset.

As described above, in order to reset, it is necessary to make the reset voltage vH given as the base voltage of the transistor T7 higher than the base voltage of the latch transistor T9. Therefore, the reset voltage v,1 is calculated by the following formula (1
) must be satisfied.

V><rl・■C3+VBE(T15) +11
' rs )'' (1) ■ Here, r two-level shift resistance, ■ ・Kare i
cs- Current source current, v8E (T15)
15 base-emitter voltage, I: current of output transistor T, rs: adjustment resistor. As can be seen from equation (1), in order to lower the base voltage of the transistor T9, the emitter potential of the output transistor T15 should be lower than the reset voltage vH, and the voltage drop of the level shift resistor r1 ■r1 (=r ・(2)) and the base-ICS soue-emitter voltage V of the output transistor T15 by adding the voltage drop E of the adjustment resistor r5 vr5. Therefore the voltage regulation is r4
It can be adjusted depending on the size.

Although the reset operation has been described above, the set operation is also similar.

[Problem to be solved by the invention]

The problem with the above conventional circuit is that even though the speed is increased by using a small amplitude signal, the adjustment resistor r4 inserted in the output stage
The problem is that speeding up is hindered by the presence of . That is, a series resistor r4 is connected to the emitter of the output transistor T.
This is because the insertion of the signal causes a delay in the rise and fall of the signal. However, this adjustment resistance r
Removing 4 will cause trouble in the set/reset operation.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a master-slave type flip-flop circuit that can operate reliably by eliminating the adjustment resistor connected in series with the output transistor and still ensuring the set/reset function.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a master side circuit <MST) and a slave side circuit (SLB) in which a pair of differential transistors are connected in a vertically stacked manner between power supply buses, and outputs
a circuit (SET-RESBT) which is cascade-connected via transistors (T14' T15) and sets and resets the signal latch state in the master side circuit (MST);
) and a level shift resistor (R
1) A master-slave type flip-flop circuit that operates with a small amplitude logic signal, characterized in that the level shift resistor (R1) is set to a value that satisfies the following relationship. With the configuration of the invention, the set/reset voltage Vu and the emitter of the output transistor l! The relationship with the I voltage (base voltage of the latch transistor) is determined only by the voltage drop across the level shift resistor and the base-emitter voltage of the output transistor, eliminating the need for an adjustment resistor. This is because the voltage borne by the adjustment resistor will be borne by the level shift resistor. In this way, it is possible to eliminate series resistance, and it is possible to provide a master-slave type 7-rig 70-tube circuit that has a set/reset function that can operate at high speed without impairing the high speed achieved by small amplitude logic signals. .

〔Example〕

Next, embodiments according to the present invention will be described based on the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1,
Parts that overlap with those in FIG. 2 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

The difference between FIG. 1 and FIG. 2 is that the level shift resistor R (rl in FIG. 2) is set to the value shown in equation (2) below, and the series resistance (second r , r ) in the figure is 14' 15
4 with the exception of 5, and the rest have the same connection relationships.

In this embodiment, the level shift resistor R1 is as follows (2)
Set the expression to a satisfying value.

■〉-(VR1+vBE(T14.T15))""2
) ■ Here, ■ = set/reset voltage, ■ ・HR1
Voltage drop of ゜bel shift resistor R,■ ・Output transistor I
BE' Base-emitter voltage of transistor TT 14° 1
5 By setting the value of the level shift resistor R1 in this way, the voltage drop vR1 at the level shift resistor R1 is V = V + V (or V )...(3
) R1rl T4 T5, and is expressed as the sum of the voltage drop of the conventional adjustment resistor r (t or T5) and the voltage drop of the conventional level shift resistor r1. This means that the resistance of the level shift resistor R1 of this embodiment is equal to that of the conventional adjustment resistor r4 (or rs
) means that the resistance of

Therefore, since it is possible to create the necessary relative potential difference between the base level of the latch transistors T and the emitter potential of the output transistors T and T, the settings can be adjusted to ensure that the set/reset voltage VH is high. can be conventionally adjusted resistor r (or T
5) becomes unnecessary.

Note that since the output of the master side circuit MST is differentially driven and output to the slave side circuit SLB, the level shift resistor R1 of the master side circuit MST does not need to be fixed and can be changed arbitrarily. However, since the level shift resistor r6 of the slave side circuit SLB determines the interface level to the next stage circuit, it needs to be fixed.

Although the above embodiment describes a BCL circuit, Ga A
s 5CFL (Source Coupled FE
It is also possible to apply this method to a TLogic (TLogic) circuit as well.

〔Effect of the invention〕

As described above, according to the present invention, the voltage of the set/reset signal can be made higher than the latch voltage of the latch transistor by the level shift resistor, so there is no need to provide a series adjustment resistor in the output stage of the output transistor. High speed can be ensured without losing the set/reset function.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional circuit. R1... Level shift resistor, T, T... Output transistor, GND...
Power supply, vEE...power supply, MST...master side circuit, SLB...slave side circuit, T, T9...latch transistor.

Claims (1)

[Claims] A master side circuit (MST) and a slave side circuit (S
LB) and output transistors (T_1_4, T_1_5
), and the master side circuit (MST
) and a circuit (SET/RESET) for setting and resetting the signal latch state in the master side circuit (MS
In a master-slave type flip-flop circuit that operates with a small amplitude logic signal and is equipped with a level shift resistor (R_1) that lowers the power supply voltage to the differential transistor pair in T), the level shift resistor (R_1) is expressed by the following formula: V_H>-(V_R_1+V_B_E) V_H: Voltage at high level of set or reset signal V_R_1: Voltage drop of level shift resistor (R_1) V_B_E: Output transistor (T_1_4, T_1_
5) A master-slave type flip-flop circuit characterized in that the voltage is set to a value that satisfies the base-emitter voltage relationship.