JPH01286463A - Auxiliary capacitance forming method - Google Patents

Abstract

PURPOSE:To simplify manufacturing process, and reduce manufacturing cost by forming, on a glass substrate, a first region and a second region turning to the gate electrode of a thin film transistor, and one side electrode of an auxiliary capacitance, by using the same material, and forming, thereon, the auxiliary capacitance by using a gate insulating film. CONSTITUTION:On a glass substrate 1, a gate electrode 2 is formed in a TFT region by using a gate electrode material; a first region 3 and a second region 4 are formed in a COG region by using the same gate electrode material; a gate insulating film 5, an a-Si:H film 6, and a protective film 7 are formed in order; source, drain contact holes 8, 9 are formed by selectively etching a part of only the protective film 7; an N-type a-Si:H film 10 is deposited; contact holes 11, 12 are formed; a metal film is deposited and selectively etched; thereby forming each region of a bus line 13, the facing electrode 14 of an auxiliary capacitance, a wiring 15, and a wiring 16 from a drain electrode. In the case of forming the auxiliary capacitance, it is realized also in a form wherein the protective film 7 is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention uses amorphous silicon (hereinafter referred to as a-Si) as an active layer.
The present invention relates to a method for forming an auxiliary capacitance necessary to drive a thin film transistor (hereinafter abbreviated as TPT) using a thin film transistor (abbreviated as :H) on a glass substrate during the process of forming the thin film transistor (abbreviated as TPT) on a glass substrate.

Conventional technology! Since TPT using L-8i:H can be easily formed over a large area at a relatively low temperature of around 200° C., it is being studied for application to -dimensional sensors and liquid crystal displays. Conventionally, the method of applying a drive signal to drive these semiconductor elements is to provide a lead-in electrode at the edge of the substrate, connect it to an external circuit through a flexible film, and apply the signal to the semiconductor element from this external circuit.

By the way, flexible films use expensive polyimide resin, and as they become larger and more dense, the number and area of films to be mounted increases.
Material costs are high. Furthermore, as the size increased, the number of contacts also increased, causing reliability problems. For this reason, the COG method, in which an IC chip is directly mounted on a glass substrate, has been used. On the other hand, in order to increase added value, semiconductor elements using single-crystal silicon as a substrate are being packaged at an even higher density. One-dimensional sensors and liquid crystal displays formed on glass substrates are no exception. Furthermore, by taking advantage of the characteristics of glass substrates, devices are also being made larger.

Problems to be Solved by the Invention In order to drive an IC, a large-capacity electric auxiliary capacitor is required, and the auxiliary capacitor chip is arranged on a glass substrate so as to be lined up with the ICi chip. There were limits to the miniaturization of this useless glass substrate. However, this auxiliary capacitor chip is thicker than an IC chip, and when using the COG method, there is a step in the part holding part when the chip is bonded to the substrate, and the holding jig is complicated, so the bonding accuracy is not good enough. A problem arose.

Means for Solving the Problems In order to achieve the above-mentioned objects, the method for forming an auxiliary capacitor of the present invention provides a method for forming an auxiliary capacitor on a glass substrate by forming a gate electrode of a thin film transistor, a first region that will become one electrode of the auxiliary capacitor, and a second region made of the same material.
a first step of forming a region of the gate electrode and a first region; a second step of sequentially stacking a gate insulating film, an active film, and a protective film on the second region; and a second step of laminating the gate insulating film, the active film, and the protective film located on the first region while adjusting the film thickness. a third step of etching; and the first step of etching. a fourth step of forming a contact hole for an IC chip contact reaching the second region; and a fifth step of depositing a metal film to selectively form the other electrode of the auxiliary capacitor and the source and drain electrodes of the thin film transistor. and forming an auxiliary capacitor by at least a gate insulating film located between the first region and the other electrode.

In addition, in the second method of forming an auxiliary capacitor of the present application, instead of forming an auxiliary capacitor having a sandwich structure consisting of the first region and the other electrode described above, A metal film is deposited on the gate insulating film located on the second region, and two electrodes forming a coupling capacitance are selectively formed. It is characterized in that it is electrically coupled to a line that supplies a reference potential, and an auxiliary capacitance is formed by these two electrodes and a gate insulating film located between the electrodes.

Effect: By the above-described method for forming an auxiliary capacitor, it is possible to form an auxiliary capacitor in the region below the IC chip, in addition to forming a thin film transistor, without requiring any special steps. As a result, the manufacturing process can be simplified and manufacturing costs can be reduced compared to the conventional manufacturing method in which a capacitive chip is disposed on a glass substrate and bonded.

EXAMPLES Hereinafter, examples of the auxiliary capacitance forming method of the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view for explaining a method of forming an auxiliary capacitor during the TPT manufacturing process.

First, a gate electrode 2 is formed on a glass substrate 1 using a gate electrode material in a TPT region, and a first region 3 and a second region 4 are formed in a COG region using the same gate electrode material (see FIG. (a)). The first region 3 is a region for transmitting an output signal of an IC chip mounted in a later process to the source electrode of the TPT, and the second region 4 is a region for transmitting one electrode of an auxiliary capacitor used for driving the IC chip. This is an area where wiring for configuring the IC chip and supplying power to the IC chip is connected to the IC chip.

Next, the gate insulating film 5 of TPT is
, an a-8i:H film 6, which is an active layer of TPT, and a protective film 7 are formed in this order (FIG. 1(b)). In the COC region, at least one of those formed on the second region 4
The layer becomes the dielectric material of the auxiliary capacitor of the present invention.

Next, only a portion of the protective film 7 is selectively etched, and the TP
T source and drain contact holes 8.9 are formed (FIG. 1(C)). At this time, the protective film 7 in the coe region
By etching while adjusting the film thickness, the film thickness of the dielectric material of the auxiliary capacitor can be controlled, and when the region functioning as the auxiliary capacitor is formed in the same area, the capacitance value can be controlled.

Next, an n-type a-3i:H film 10 is deposited (Fig. 1(d)).
).

Next, contact holes 11 and 12 are made in the contact area with the IC chip in the GOG region (FIG. 1(e)).

Next, a metal film containing mulch is deposited (FIG. 1(f)).

This metal film is selectively etched to form a pass line 13 for driving the IC, a counter electrode 14 of the auxiliary capacitor, a wiring 16 to the source electrode of the TPT, and a wiring 1''6 from the drain electrode. With the metal film selectively etched, the n-type a-3i:H film 1o is etched in a similar pattern.Then, the IC chip 17 is etched onto the bump 1B.
, 19 to be mounted on the glass substrate 1. bump 18
serves to connect the pass line 13 that supplies power to drive the ICi and a power input pad (not shown) installed on the IC chip 17.

The bump 19 serves to connect a signal output pad (not shown) of the IC chip 17 and the wiring 15 to the source electrode.

In this embodiment, the auxiliary capacitor includes the second region 4 of gate electrode material, the counter electrode 14 of the auxiliary capacitor, and these electrodes 4,
It is formed by at least the gate insulating film 6 located between the gate electrodes 14 and 14. Note that when forming the auxiliary capacitor, it can also be realized in a form in which the protective film 7 is removed. The auxiliary capacitor excluding the protective film 7 can be formed by selectively etching the auxiliary capacitor formation region when forming the source and drain contact holes 8 and 9 in the step 11g (C>). The capacitor has a large electric capacity per unit area, and the auxiliary capacitor with the protective film 7 installed can lower the probability of electrical short circuits caused by pinholes caused by dust, etc., and can increase the withstand voltage of the auxiliary capacitor. Note that the counter electrode 14 of the auxiliary capacitor is connected to a pad (not shown) that provides a reference potential of the IC chip 17.

The insulating material 2 is made such that the distance between the re chip 17 and the counter electrode 14 of the auxiliary capacitor is 1 μm or more and 10 μm or less.
6 to fix the IC chip 17. Note that the insulating material 26 does not fill the entire space (the distance in FIG. 1(f)) created between the IC chip 17 and the substrate on which the IC chip 17 is mounted. In other words, there is no insulation in the minute spaces created at the bonding surfaces between the bumps 18 and 19 and the IC chip 17, and at the bonding surfaces and chest circumferences between the bumps 1B and 19 and the second region of the oblique portion of the gate electrode material. sexual substance 2θ is not satisfied.

When all the spaces are filled with insulating material 26, I
This is because the C chip 17 cannot make sufficient contact with the bumps 18, 19 and the conductive material 3.4 on the substrate side.

Next, a second embodiment of the present invention will be described with reference to the drawings. In the first embodiment, a so-called sandwich type auxiliary capacitor is shown. In this embodiment, as shown in FIG. 2, an auxiliary capacitor is shown in which parallel gaps are provided on the same plane. FIG. 2(a) is a plan view of this embodiment, and FIG. 2(1)) is a sectional view taken along the line (+!L) of the same figure. Note that since the TPT manufacturing process is the same as in FIG. 1, the TPT region is omitted and only the COC region is shown.

In FIG. 2 (!L), the area 31 surrounded by broken lines is
An IC chip 17 is arranged. As described in the first embodiment, the configuration shown in FIG. 2 uses only the gate insulating film 6 without the protective film 7 as the insulating thin film of the auxiliary capacitor. Other components are the same. This will be explained by comparing FIG. 1 (w) with FIG. , 6 is an a-3i:H film, 10 is an n-type a-3i:H film, 11 and 12 are contact holes, 13 is a pass line for supplying power for driving the IC chip, and 16 is a wiring to a source electrode. With these configurations, the auxiliary capacity of this example is
A counter electrode 33 of the auxiliary capacitor extended from the ground line 32 that provides the reference potential of the IC chip 170, and a pass line 1
3 and an insulating film 6 located between the electrodes. The gate electrode material second region 4 is shown in FIG.
If selectively etched as in b), the auxiliary capacitance of the present invention can also be formed by these.

In addition, in FIG. 2 (&), the pass line extension line 34 is
A counter electrode 3 of the auxiliary capacitor which is an extension of the ground line 32
However, in consideration of circuit configuration requirements and signal stability, the ground line may be configured to surround the pass line. In that case, the ground line may be placed on a glass substrate. It may be spread out in an empty area where there is no wiring or the like. In this way, a comb-shaped auxiliary capacitor could be formed.

Note that when mounting an IC chip, the distance 25 between the IC chip and the conductive material on the substrate is set to 1, as shown in Figure 1 (0).
It was fixed with an insulating material 26 so that the thickness was 10 μm or more.

Effects of the Invention As described above, according to the present invention, an auxiliary capacitor for driving an IC chip can be formed under a COG-mounted IC chip without requiring any special process different from the process for forming a thin film transistor. can simplify the manufacturing process,
Manufacturing costs can be reduced. Further, since the auxiliary capacitor and the IC chip are stacked, it is possible to further increase the utilization efficiency of the glass substrate.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view illustrating the steps of an embodiment of the method for forming an auxiliary capacitor according to the present invention, and FIG. 2 is a plan view and a cross-sectional view showing a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Glass substrate, 2...Gate electrode, 3...Gate electrode first region, 4...Gate electrode second region, 6...・Gate insulating film, 6・
...a-8i: H film, 7...protective film, 8,
9,11.12...Contact hole, 10.
... n1a-8i: Hi, 13 ... Pass line, 14 , 33 ... Counter electrode of auxiliary capacitor, 15 ... Wiring to source electrode, 17.・・・・・・
・Engineering C chip, 1・8.19...Bump, 26
...Insulating material, 32...Earth line, 34...Pass line extension line. Name of agent: Patent attorney Toshio Nakao and 1 other person13
---Pass line/8. /9---Bump L-1-) Distance between 4 and 17 Figure 1 (Z-2) Zou 2 ゝ

Claims (2)

[Claims] (1) A first step of forming a first region and a second region that will become a gate electrode of a thin film transistor and one electrode of an auxiliary capacitor using the same material on a glass substrate; a second step of sequentially stacking a gate insulating film, an active film, and a protective film on the region, and adjusting the film thickness of the gate insulating film, active film, and protective film located above the first region; a third step of etching;
a fourth step of forming a contact hole for IC chip contact reaching the second region; and a fifth step of depositing a metal film to selectively form the other electrode of the auxiliary capacitor and the source electrode and drain electrode of the thin film transistor. A method for forming an auxiliary capacitor, comprising the step of forming an auxiliary capacitor by at least a gate insulating film located between the first region and the other electrode. (2) a first step of forming a gate electrode of a thin film transistor and first and second regions for electrically coupling an IC chip to the thin film transistor using the same material on a glass substrate; , a second step of sequentially laminating a gate insulating film, an active film, and a protective film on the second region;
a third step of etching the gate insulating film, active film, and protective film located above the first and second regions while adjusting the film thickness; and an IC chip that reaches the first and second regions. A fourth step of forming a contact hole for contact, depositing a metal film above the gate insulating film located between the contact holes and having the adjusted film thickness, and selecting two electrodes forming a coupling capacitor. electrically coupling one electrode for coupling the coupling capacitance to a ground line and the other electrode to a line supplying a reference potential of the IC chip; A method for forming an auxiliary capacitor, comprising forming an auxiliary capacitor by at least an electrode and a gate insulating film located between the electrodes.