JPH01283967A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent charges stored at a floating gate at the time of reading from leaking by designating a first selected transistor source as a memory transistor drain, and connecting a second selected transistor source to a charging region of the memory transistor. CONSTITUTION:A source 6 and a gate 4 of a first selected transistor are isolated from a source 7 and a gate 2 of a second selected transistor. Drains 1 of both transistors are connected to each other; the source 6 becomes the drain 6 of a memory transistor, and the source 7 is connected to a charging region 8 of the memory transistor. Accordingly, the drain 6 is completely electrically isolated from the charging region 8 of the memory transistor. Thus, even if a voltage for reading is applied between a control gate 9 and the drain 6, a voltage applied to a heavily doped impurity diffusion layer of the charging region 8 can be given arbitrarily, thereby reducing an electric field between a floating gate where charges are stored and another electrode at the time of reading data and thus preventing the charges from leaking.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of an electrically rewritable semiconductor nonvolatile memory.

[Prior art 1] Conventional electrically rewritable semiconductor non-volatile memories using a single layer of polycrystalline silicon, for example, are described in publicly known materials [1985lSSCCD1g, Tech, P2p,
Symp, VSLI Technology PP100-1
In the conventional example, as shown in FIG. 2, it is composed of one selection transistor and one memory transistor, the source 16 of the selection transistor becomes the drain 16 of the memory transistor, It is also connected to the loading area 17.

Here, writing, erasing, and reading data will be explained.

First, when writing or erasing data, the selection transistor shown in FIG. 2 is turned on, a voltage is applied between the drain 16 of the memory transistor and the control gate 18, and the
A Fouler layer is formed between the floating gate 19 and the high concentration impurity diffusion layer 17 in the charge injection region provided in a part of the
Nordheim Allows tunnel current to flow.

Thereby, charges are accumulated in the floating gate 19 of the memory transistor, and data is written. On the other hand, for erasing data, a voltage of the opposite polarity to that for writing is applied between the drain 16 and control gate 18 of the memory transistor, and charges are released from the floating gate 19 of the memory transistor, thereby erasing the data. Do the following.

Next, in the case of reading data, one selection transistor is made conductive so that a voltage can be applied to the train 16 of the memory transistors, and data is read depending on the magnitude of the threshold voltage of the memory transistors.

[Problem to be solved by the invention]

However, in the above-mentioned conventional technology, after writing and erasing data,
Due to the charge stored in the floating gate, an electric field is created between the diffusion layer of the charge injection region and the floating gate.

Furthermore, when the 1 selection transistor becomes conductive when reading data, the voltage necessary for reading is applied to the charge injection region provided in a part of the drain of the memory transistor. A higher electric field is applied between the diffusion layer of the charge injection region and the floating gate.

As a result, the charges accumulated in the floating gate are discharged, resulting in a problem that data cannot be read correctly at the time of reading.

Therefore, in order to prevent charge discharge, it has been considered to reduce the potential difference between the floating gate and the drain of the memory transistor.

That is, the control gate at the time of reading and
The voltage applied to the drain is lowered within the internal circuit to prevent such malfunctions during reading.

However, this method has the problem that an internal circuit for voltage reduction is required only for reading, and that the response speed of the circuit operation due to the voltage drop is accordingly low.

SUMMARY OF THE INVENTION The present invention aims to solve these problems, and its purpose is to reduce the charge accumulated in the floating gate without reducing the voltage applied to the control gate and drain during readout. The purpose of the present invention is to provide an electrically rewritable semiconductor nonvolatile memory that can suppress leakage of data.

[Means for solving the problem] Formed on a semiconductor substrate via a first gate insulating film,
and a floating gate having a charge injection region protruding toward the selection transistor side with a tunnel gate insulating film interposed between the semiconductor substrate and a second gate insulating film on or below the floating gate. In a memory cell including a memory transistor with a control gate formed through the gate and a selection transistor for selecting the memory transistor, the memory cell includes two selection transistors, and the source and gate of the first selection transistor are connected to the first selection transistor. The source and gate of the second selection transistor are separated from each other, the drain of the first selection transistor is connected to the train of the second selection transistor, and the source of the first selection transistor is separated from the source and gate of the second selection transistor.
According to the above structure of the present invention, the drain of the memory transistor is characterized in that the source of the second selection transistor is connected to the charge injection region of the memory transistor. The drain and charge injection region are completely electrically separated, and even if a read voltage is applied between the control gate and the drain, the voltage applied to the high concentration impurity diffusion layer in the charge region can be applied arbitrarily. becomes possible.

Therefore, during readout, for example, if the high concentration impurity diffusion layer in the charge injection region is placed at the same potential as the control gate or in an oven state, the electric field between the floating gate and the high concentration impurity diffusion layer in the charge injection region is It can be lowered regardless of the transistor.

[Embodiment] FIG. 1 is a plan view of an embodiment of the present invention, which will be described in detail below.

This embodiment is an electrically rewritable semiconductor non-volatile memory of a type in which a control gate is formed of a high concentration impurity diffusion layer on a silicon substrate under a floating gate.

First, as shown in FIG. 1, the first selection transistor has a drain region 1, a gate electrode 4, and a source region 6, and the source region 6 of the first selection transistor is a memory. The gate electrode 4 of the first selection transistor is connected to the train region 6 of the transistor.
is formed independently from other gate electrodes, and the drain region 1 of the first selection transistor is the same as the train region 1 of the second selection transistor. Further, the gate electrode of the second selection transistor is also formed independently of other gate electrodes, similar to the gate electrode of the first selection transistor, and the source region 7 of the second selection transistor is formed in the charge injection region 8. Connected to a highly concentrated impurity diffusion layer. The memory transistor includes a source region 11 formed independently of other diffusion layers, a floating gate 10 formed of polycrystalline silicon, and a control gate 9 formed of a high concentration impurity diffusion layer.
It is made up of.

Next, the structure of the present invention is made into an N-type memory transistor,
The operation will be explained below.

Here, erasing data is defined as injecting electrons into the floating gate 10, and emitting electrons from the floating gate 10 is defined as writing data.

Then, during writing, the control gate 9 and the P-type substrate are grounded, the source 11 of the memory transistor is opened, and the gate 2 of the second selection transistor and the second
Apply 15V to the drain of the selection transistor for 0.01 seconds. As a result, Fowle is formed between the floating gate 10 and the high concentration impurity diffusion layer 8 in the charge injection region.
An r-Nordheim tunneling phenomenon is caused and electrons are emitted from the floating gate 10. the result,
The threshold voltage of the memory transistor is -4V or less.

When erasing, the P substrate is grounded, the source 11 of the memory transistor is left open, 5V is applied to the gate 2 of the second selection transistor, the drain 1 of the second selection transistor is grounded, and the control gate 9, 0.
Apply a voltage of 20V for 01 seconds. This causes a Fowler-Nordheim tunneling phenomenon between the floating gate IO and the high concentration impurity diffusion layer 8 in the charge injection region, causing electrons to be injected into the floating gate IO.

As a result, the threshold voltage of the memory transistor is 6
It becomes V or more.

When reading, the source 1 of the memory transistor
1 and the substrate are grounded, 5V is applied to the gate 4 of the first selection transistor and the drain 1 of the first selection transistor, and the gate of the second selection transistor is grounded. Then, by setting the control gate to Ov, the threshold voltage of the memory transistor is determined depending on whether or not current flows between the source 11 and drain 6 of the memory transistor, and data is read.

In this way, since the voltages applied to the gates of the first and second selection transistors are independent during readout, the memory transistors are operated at conventional voltages and the high concentration impurities in the control gate 9 and the charge injection region are Diffusion N8
By lowering the electric field between floating gate 1
0 and the low concentration impurity diffusion layer 8 in the charge injection region can be lowered.

[Effects of the Invention] As described above, according to the present invention, the electric field between the floating gate that has accumulated charge and other electrodes is lowered even during data readout without lowering the conventional readout voltage, and the charge is reduced. Can prevent leakage.

Therefore, without adding internal circuits or reducing speed due to voltage drop, the charge accumulated in the floating gate is prevented from being lost and erroneous data is generated, and the reliability of the memory element is improved. has.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view showing an embodiment of the semiconductor device of the present invention. Figures 1(b) and (c) are AA' shown in Figure 1(a).
FIG. 2 is a cross-sectional view showing an embodiment of the semiconductor device of the present invention taken along lines BB' and BB'. FIG. 2 is a plan view of a conventional semiconductor device. 1...Drain of first and second selection transistor 2...Gate of second selection transistor 3.5.12.21.22...AI wiring 4... Gate of the first selection transistor 6... Source of the first selection transistor and drain of the memory transistor 7.... of the second selection transistor Source 8.17...Charge injection region 9.18...Control gate 10.19...
...Floating gate 11.20...Source 13 of memory transistor...Silicon substrate 14...Drain 15 of selection transistor...Gate of selection transistor 16...
... Source of selection transistor and drain of memory transistor Applicant Seiko Epson Corporation Representative Patent attorney Masaharu Kamiyanagi (1 other person) Soul 1 country Cc
L) Tame 11 yen 1 (1), 1

Claims (1)

[Claims] a floating gate formed on a semiconductor substrate via a first gate insulating film, and having a charge injection region protruding toward a selection transistor side with a tunnel gate insulating film interposed between the floating gate and the semiconductor substrate; A second layer on the floating gate or below the floating gate.
A memory transistor comprising a control gate formed through a gate insulating film;
A memory cell including a selection transistor for selecting a transistor has two selection transistors, the source and gate of the first selection transistor are separated from the source and gate of the second selection transistor, and the source and gate of the first selection transistor are separated from the source and gate of the second selection transistor. The drain of the transistor is connected to the drain of a second selection transistor, the source of the first selection transistor becomes the drain of the memory transistor, and the source of the second selection transistor is connected to the charge injection region of the memory transistor. A semiconductor device characterized in that it is connected.