JPH01281545A - Cache memory control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [II Required] Of the data in an input/output device such as a disk device, frequently referenced data is copied to a cache memory, and high-speed access is achieved by direct transfer from the cache memory. Regarding the cache memory control method, a part of the main memory is used as cache memory,
The purpose of the present invention is to provide a cache memory control method that reduces the response time during a hit by transferring data between the main memory and cache memory during a cache hit. a main body system having an adapter control unit that controls the transfer of data between the two; and a controller that is connected to an input/output device that stores data and has a management table and a cache control unit that controls the management table. The management table is searched based on access address information from the main system, and when requested data is cached in the cache memory, data is transferred between the main memory and the cache memory.

[Industrial Application Field] The present invention copies frequently referenced data among the data currently being input/outputted by a disk device to a cache memory, and enables high-speed access through direct transfer of the data to the cache memory. This article relates to a cache memory control method to be realized.

As the performance of processors (CPUs) has improved in recent years, systems that support large storage devices of gigabytes or more have been developed, and response time due to concentration of accesses has become a bottleneck in system performance.

As a countermeasure against this problem, it is common to adopt cache control with an additional cache memory.

The operating principle of the cache is to copy frequently referenced data to a cache memory added within the magnetic disk control device by taking advantage of the bias in access from hosts to data on a magnetic disk device. When accessing the copied data again, high-speed access is achieved by direct transfer from the cache memory instead of accessing the data on the magnetic disk.

The data on the cache memory is LRU (Least
(Recently Used) algorithm.

Therefore, data that is frequently accessed at that time is held in the cache memory. Access requests from the host to this data can be transferred from the cache memory, eliminating the need for mechanical operations associated with accessing the magnetic disk. This allows the I10 response time to be shortened, but in order to improve the performance of the device, it is desired to further speed up this response time.

[Prior Art] As a conventional cache memory control method of this type, there is one shown in FIG. 5, for example.

In FIG. 5, 1 is a main body system, and the main body system 1 has a main memory 2, an adapter control section 3, and the like. 4 is a controller (disk Ml adapter), and the adapter 4 has a cache memory 5 and a management table 6.
, a cache control unit 7, and the like. 8 is a disk device in which data is stored, and the disk device 8 is connected to the adapter 4.

When reading data, the management table 6 is searched for the read data requested by the main system 1 via the cache control unit 7, and a hit (data existence) or a miss (data existence) is determined. If it is a hit, the data is transferred from the cache memory 5 to the main memory 2.

On the other hand, when writing data, the management table 6 is searched for all of the requested write data, a hit or a miss is determined, and if it is a hit, the cache memory 6 is searched.
If there is a miss, the data in the disk device 8 is updated.

[Problems to be Solved by the Invention] However, in such a conventional cache memory control method, in order to obtain the cache effect, a large cache memory of megabytes or more is provided in the controller, and the cache is Since it is necessary to transfer data between the memory and the main memory in the main system via the I10 bus, there has been a problem in that the response time during a hit cannot be further shortened.

The present invention has been made in view of these conventional problems, and uses a part of the main memory as a cache memory and transfers data between the main memory and cache memory at the time of cache hit, thereby reducing the The purpose of this invention is to provide a cache memory control method that reduces response time.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 13 is a main body system having a main memory 25, a cache memory 26, and an adapter control unit 24 that controls data transfer between these memories;
A controller 11 is connected to an input/output device 17 for storing data, and has a management table 18B and a cache control unit 19 that controls the management table 18B.

[Operation] In the present invention, the cache memory conventionally provided in the controller (adapter) is eliminated, and the main system 1
3 is used as the cache memory 26, and this cache memory 26 is controlled by the adapter control unit 24 provided in the main system 13 and the controller 11, so that data transfer is difficult when cashing. is not transferred from the controller 11 to the main memory 25, but from the cache memory 26 to the main memory 25, reducing the transfer time. Therefore, the response time in the case of a hit can be further shortened.

Furthermore, when the cache memory 26 is used as a system program area whose data contents are not updated, there is no need to transfer data from the cache memory 26 to the main memory 25, which can significantly shorten response time. can.

Furthermore, when cache control is not performed, the cache memory area can be used as a program area, work area, etc., making it possible to configure a flexible system.

[Example] Hereinafter, embodiments of the present invention will be described based on screens.

FIG. 2 is a block diagram for implementing the invention.

In FIG. 2, 11 is a disk control adapter which is a controller, and a microprocessor (MPLJ) 1
2, etc., and performs command analysis processing, command execution processing, data processing, etc. from the main system 13 by executing programs.

14 is a system bus controller, I10 bus 1
5 and exchanges commands and data with the main system 13. 16 is an input/output controller;
It is connected to the disk device 17 and performs input/output control with the disk device 17.

18A is a RAM, and a management table 18B is provided in the RAM 18A, and the cache control unit 9 performs search processing, LRU processing, etc. on this management table 18B. 20 is a ROM, which stores programs executed by the MPU 12.

On the other hand, the main system 13 includes a CPU 21, a ROM 22,
system bus controller 23, adapter control section 24,
It has a main memory 25 and a cache memory 26.

The system bus controller 23 is connected to the I10 bus 15 and exchanges commands and data with the adapter 11. The ROM 22 stores programs executed by the CPU 21.

The cache memory 26 is configured as a part of the main memory 25, and has a capacity of, for example, about 4 megabytes. Cache memory 26 and main memory 25 are I10
They are connected via a memory bus 27 which is faster than the bus 15.

The adapter control unit 24 has a function of creating control information such as the address, size, and page size of the cache memory 26, and also performs data transfer processing between the cache memory 26 and the main memory 25 at the time of cache hit.

Next, the operation will be explained.

First, the process at the time of initial setting will be explained based on FIG.

At the time of initial setting, the adapter control unit 24 creates control information such as the address, size, and page size of the cache memory 26 in step S1 under instructions from the CPU 21. Then, the adapter control unit 24 performs an adapter command activation process in step S2.

In adapter 11, system bus controller 23.14
The MPU 12 receives the command via the MPU 12 and analyzes the command. The MPL 112 gives an allocation instruction to the cache control unit 19, and the cache control unit 19 recognizes the control information from the adapter control unit 19 in step S3 and sets the area of the cache memory 26 to be used.

Next, processing at the time of reading and writing will be explained based on FIG.

When the adapter control unit 24 performs the adapter command activation processing in step S11 in response to the read/write command from the CPLI 21, the command is given to the MPU 12 via the system bus controller 23.14, and the
The PU 12 analyzes the given command, and when it determines that a read or write command has been received, the cache control unit 1
9 to perform cache control.

The cache control unit 19 creates parameters for cache control based on the requested address information in step 312, and searches the management table 18B based on the parameters in step S13.

Next, the cache control unit 19 proceeds to step S14,
A hit or miss is determined, and if it is a hit, it is determined in step 315 whether the command is a write or a read.

At the time of writing, in step S16 a write process is performed from the specified area of the main memory 25 to the disk device 17, and in step 517 a request is made to the main system 13 to transfer from the specified area to the cache memory 26.

The adapter control unit 24 determines the requested process in step S18, performs a transfer process from the specified area of the main memory 25 to the cache memory 26 in step 319, and issues a completion notification to the CPU 21 when the transfer process is completed.

On the other hand, if the command is read in step 815, the process advances to step 320, and the main system 13 is notified of the address of the area where the requested data is stored.

The adapter control unit 24 of the main system 13 determines the requested processing, performs data transfer processing from the cache memory 26 to the specified area of the main memory 25 in step 321, and when the processing is completed, issues a completion notification to the CPLI 21.

Furthermore, if the determination in step 514 is a miss, it is determined in step 522 whether the command is a read or a write;
When reading, in step S23, data is read from the disk device 17 to the cache memory 26. Data read processing is performed in step S20. The process of S18, 521 is performed.

On the other hand, when the command is write in step 322, data is written from the specified area of the main memory 25 to the disk device 17 in step S24, and in step S
In step 25, no request processing is performed.

In this case, the adapter control unit 24 determines in step 318 that there is no requested processing, and issues an end notification to the CPU 21.

As described above, in the present invention, the cache memory that was conventionally provided in the adapter is eliminated, and a part of the main memory 25 in the main body system 13 is replaced with the cache memory 2.
6, and the cache memory 26 is controlled by the adapter 11 and the adapter control unit 24, so that data transfer at the time of cache hit is not to the adapter main memory but to the main memory cache memory, reducing the transfer time. Therefore, the time required for response vf at the time of a hit can be shortened.

Further, when the cache memory 26 is used as a system program area whose data contents are not updated, there is no need to transfer data to the main memory cache memory, making it possible to further shorten the response time.

In general, when cache control is not performed, the cache memory area can be used as a program area, work area, etc., and a flexible system can be constructed.

[Effects of the Invention] As explained above, according to the present invention, data is transferred from the main memory to the cache memory instead of from the adapter to the main memory, so the data transfer time can be reduced. , As a result, the response time for human response can be shortened.

Furthermore, when the cache memory is used as a system program area whose data contents are not updated, there is no need to transfer data from the main memory to the cache memory, making it possible to further (shorten) the response time.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram for implementing the invention, Fig. 3 is a flowchart showing processing at initial setting, and Fig. 4 shows processing at write/read. Flow Chart FIG. 5 is a block diagram showing a conventional example. In the figure, 11... Controller (disk control adapter), 1
2... Microprocessor, (MPIJ), 13...
・Main system, 14... System bus controller, 15... I1
0 bus, 16... Bow 10 controller, 17... Disk unit @ (input/output device), 18A...
RAM. 18B... Management table, 19... Carriage 1 control unit, 20... ROM. 21...CPU, 22.-ROM. 23... System bus controller, 24... Adapter control unit, 25... Main memory, 26... Cage 1 memory, 27... Memory bus.

Claims (1)

[Claims] a main body system (13) having a main memory (25), a cache memory (26), and an adapter control unit (24) that controls data transfer between these memories;
a controller (11) connected to an input/output device (17) for storing data and having a management table (18B) and a cache control unit (19) for controlling the management table (18B); The management table (18) is based on the access address information from the system (13).
B), and the requested data is stored in the cache memory (2).
6) When a cache hit occurs, data is transferred between the main memory (25) and the cache memory (26).
A cache memory control method characterized in that the cache memory control method is performed between.