JPH01280839A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device including a logic circuit that requires high reliability.
The present invention relates to a semiconductor integrated circuit device that includes a logic circuit with improved integration and/or high speed without impairing reliability.

[Conventional technology]

As a method to improve the reliability of logic circuits, IEE, International Solid State
Circuits Conference, Digest of Technical Pavers.

1982, pp. 54-55 (ISSCCDIG
EST OF TECHNICAL PAPER5,
pp. 54-55; Feb., 1982), they added parity pits to data to detect data errors, and also duplicated logic circuits and compared their outputs to detect errors during logic operations. A method of detection is shown.

FIG. 2 shows the error detection system according to this prior art.
Errors are detected by duplicating the gic unit (hereinafter referred to as ALU). ALUI and ALU2 have the same logical functions; data A and B are input to both, and the ALUI calculation result is output from the output terminal F, and this is sent to the comparison circuit CMP to perform the calculation of ALU2. The presence or absence of an error in the arithmetic operation is checked by comparing it with the result, and the error detection signal is outputted from the terminal. On the other hand, regarding error detection in input data, parity bits P^ and P[l corresponding to data A and B are inputted, and parity check circuits PCA and PCB perform comparison, and the results are sent to output terminal E.
^, Output from Ea. Furthermore, a parity generation circuit PG calculates a parity output based on the ALU output, and outputs it from an output terminal PF.

Next, FIG. 3 shows an example in which the above-mentioned conventional technology is applied to an arithmetic unit consisting of an ALU, a register, a preshifter, etc. The configuration of the ALU unit 16 is substantially the same as that in FIG. be. In the figure, DL1601 and DL1602 are data latches.

PL16 is a parity latch, R1501 to R15
02 is a register, and PS1501 to PS1'502 are preshifters. In this example, parity check of register output is performed by parity check circuits PCA and PCB.
The results are output from terminals E^ and Ea, respectively. In addition, two sets of duplicated preshifters PS1501 and PS1502 (shift circuits 5H1501 and ST(1
502, and shift circuits 5H1503 and S H1504
) comparator circuit CMP1601 and C:MP
1602 compares and collates each, and sends the result to terminal E16.
01°E1602 respectively.

With the configuration described above, (1) error detection in input data using parity pits, (2) error detection in calculation results by duplication of ALU and preshifter, (3)
) A parity bit can be added to the ALU operation result.

FIG. 4 shows an example of a circuit for comparing and verifying calculation results of a duplicated circuit and a diagnostic circuit for comparing and verifying circuits. In the figure, 1.301.

1302 is a redundant arithmetic circuit with the same function, EO
R13 is a FOR circuit for comparison and verification, and 1303 is a diagnostic circuit for the FOR circuit.

AND], 302 is an AND circuit. Since the duplicated arithmetic circuits 1301 and 1302 output the same arithmetic result when operating normally, it remains to be seen whether the comparison and matching circuit EOR13 is operating normally or whether its output is fixed at a normal value. cannot be determined. In this example, the comparison and verification circuit EOR13 is diagnosed by forcing the output of one arithmetic circuit to a value different from the output of the other arithmetic circuit by a diagnostic circuit 1303 consisting of an AND circuit AND13 (0, AND1302). The logic circuit 1300 with built-in error detection circuit is obtained by configuring the logic circuit 1300 with a built-in error detection circuit.In other words, T2.
T1302 is input as is to the comparison and verification circuit FORMinatoi=. Theory>w, Iay Arithmetic 11301, 1.302
If both are operating normally, 0UT1301, 0UT
Since 1302 is equal and has l and N values, the comparison and matching circuit E
The output ER13 of the OR13 is always at a low level, and it is impossible to distinguish between the normal operation of the comparing and matching circuit EOR13 and the case where the output is fixed at a low level due to a failure of this circuit. In order to be able to make this distinction when diagnosing logic circuits, for example, if the control signal T2 is set to low level, the AN
The output of D circuit ANDi301 becomes low level, and at this time, the input that causes 0UT1302 to become high level is A.
ll~D1], the comparison and matching circuit EO
If R13 is operating normally, the output ERI 3 will be at a high level, but if it is malfunctioning, it will be at a low level. In this way, the diagnostic control signal T2. The comparison and verification circuit EOR13 can be diagnosed by setting one of the T and T to low level.

[Problem to be solved by the invention]

Logic circuits having error detection capabilities as described with reference to FIGS. 2 to 4 have the following problems.

First, regarding the delay time of the ALU section, since the parity generation operation is performed using the result after the completion of the operation of the ALU section,
The problem is that the delay time is the sum of both calculation times, and is longer than when no parity bit is added. For example, in a 32-bit ALU, this amount of increase amounts to about 20% of the total delay time, which is a factor that hinders speeding up. Furthermore, by providing a diagnostic circuit for the comparison and verification circuit, the delay time of the error detection signal increases.

Next, regarding the layout area, since the logic scale is large and there are many ALUs and main wiring lines that occupy a large area, in addition to the preshifter that also occupies a large area for calculation, one more is required for checking the results. Since a parity check circuit for the register output, a comparison circuit for the ALU output and the preshifter output, and a diagnostic circuit for the same circuit are required, there is a problem in that the area increases.

Furthermore, in order to achieve higher speeds in conventional technology, it is necessary to reduce the delay time of each stage of the circuit by improving the immediate acting ability of active elements such as transistors that make up the logic circuit, or to reduce the number of circuit stages of the critical bus by improving the parallelism of logic. There are other methods, but the former requires increasing the area of the active element;
Moreover, since the latter requires an increase in the number of circuits, both of them result in an increase in layout area. Therefore, if an attempt is made to increase the speed of an arithmetic unit using the conventional technology, which originally has a large area due to error detection due to duplexing, there is a possibility that it will significantly impede higher integration of LSI.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device including a logic circuit having an error detection function with improved integration and/or high speed without impairing reliability.

[Means and effects for solving the problem] The semiconductor integrated circuit device of the present invention inputs input data to a plurality of stages of serially connected arithmetic circuits, and processes the input data into a predetermined arithmetic operation in a Buddhist shrine. A first circuit array (data operation unit) that performs the above operations and obtains output data, and by inputting an error detection code corresponding to the input data, detects errors corresponding to calculations in each arithmetic circuit in the first circuit array. A second circuit array (error detection code correction section) which connects in series error detection code correction circuits that correct the code and outputs an error detection code corresponding to the output data; It includes a logic circuit using the output of the arithmetic circuit and a corresponding error detection code.

The first circuit array and the second circuit array perform data calculation and error detection code generation in parallel, and the error detection code output corresponding to the calculation result is obtained almost simultaneously with the completion of data calculation. Therefore, the calculation time can be reduced to the same level as when no error detection code is generated. In addition, the error detection circuit performs error detection (for example, parity check) in parallel with data calculation using the output of the calculation circuit and the output of the corresponding error detection code correction circuit, and detects errors during calculation. It is possible to obtain the same level of reliability without duplicating the circuit. Furthermore, since the increase in area due to the error detection code correction circuit, error detection circuit, etc. can be made smaller than that of one arithmetic circuit, when duplicating the arithmetic circuit, the relative layout area can be made the same or less. can.

The configuration of a logic circuit using the above error detection code is as follows.

It is suitable to apply to an ALU section with a large circuit scale.

Furthermore, the configuration of a logic circuit using the above error detection code is as follows:
It is also possible to apply not only the ALU section but also the entire calculation section including the ALU section. A semiconductor integrated circuit device of the present invention includes a first circuit that performs a predetermined operation on input data and outputs output data, and a first circuit that performs a predetermined operation on an input of an error detection code corresponding to the input data and outputs the output data. A data bus is formed by a first circuit array that connects the first circuits in each arithmetic circuit. An error detection code bus is formed by a second circuit string connecting the second circuits in the arithmetic circuits that are interconnected by a bus, and the output data of the first circuit in the same arithmetic circuit and the second circuit are connected to each other by a bus. A logic circuit using an error detection code is provided, including at least one error detection circuit that checks the output of the second circuit with the error detection code. That is, the configuration is such that the error detection code output of the second circuit array is made to accompany the data output of the first circuit array. In this way, by making the error detection code output of the second circuit string accompany the data output of the first circuit string,
The number of error detection circuits for calculation results can be reduced, and the layout area can be further reduced.

The semiconductor integrated circuit device of the present invention also provides a logic circuit using the error detection code described above, a duplex arithmetic circuit having the same function and inputting the same signal, and comparing the outputs of the duplex arithmetic circuit with each other. A logic circuit with a built-in error detection function is provided by duplicating the circuit consisting of the comparator circuit. In other words, depending on the characteristics of the circuit, logic circuits using error detection codes and logic circuits with built-in error detection functions by duplicating the circuits are used, and by mixing both types of logic circuits, the overall speed and integration can be increased. At the same time. This configuration is suitable for application to a carry-lookahead type ALU. Since the ALU section has a large circuit scale, a logic circuit using an error detection code is used. On the other hand, since the carry lookahead generator section has a relatively small circuit scale, a logic circuit with a built-in error detection function configured by duplicating the circuit is used. Furthermore, the control circuit unit that generates the arithmetic control signals also uses a configuration in which error detection is performed by duplicating the control signal generation circuits.

In addition, for a logic circuit with a built-in error detection function by duplicating one circuit, the clock signal system for each duplexed arithmetic circuit is fed to the switch circuit that takes out the output signal of the logic circuit network in each arithmetic circuit to the outside. By dividing the power supply into two systems: a power supply system and a power supply system for clock signals to other switch circuits in the arithmetic circuit, the redundant arithmetic circuit itself has the diagnostic function of the error detection circuit. therefore,
The semiconductor integrated circuit device of the present invention includes a duplexed arithmetic circuit and a comparison circuit t for comparing outputs of the duplexed arithmetic circuit.
(!iI, the power supply system for the clock signal to each duplex arithmetic circuit is the power supply system for the clock signal to the switch circuit that takes out the output signal of the logic circuit network in the arithmetic circuit to the outside, and The clock signal power supply system to other switch circuits is divided into two systems.It is equipped with a logic circuit with a built-in diagnostic function for the error detection circuit.In other words, the clock power supply system to each duplexed arithmetic circuit is divided into two systems: the clock signal power supply system to other switch circuits. By dividing it into two systems and supplying it to each arithmetic circuit, the normal !FIJ
During operation, the same clock signal is supplied to the two systems and the calculation operation is performed in the same manner as in the conventional example, while during failure diagnosis, different clock signals are supplied to the two systems to power one of the duplex calculation circuits, The switch circuit that takes out the output of the logic circuit in this arithmetic circuit to the outside is made non-conductive, thereby setting the output level of one of the duplex arithmetic circuit outputs input to the comparator circuit to either high level or low level. Therefore, the outputs of both duplex wave calculation circuits can generate different signals. In other words, by changing the clock signal between normal and diagnostic times, the arithmetic circuit itself has the function of generating a comparison circuit diagnostic signal.This eliminates the need for a diagnostic circuit and reduces the number of circuits. It is possible to reduce the layout area and the delay time of the error detection signal.

This configuration is suitable for application to a domino type dynamic logic circuit. In particular, it is suitable to apply to a carry lookahead generator section in a carry lookahead type ALU. That is, as described above, the ALU section uses a logic circuit configuration using an error detection code, the carry lookahead generator section uses a logic circuit configuration with a built-in diagnostic function of a comparison circuit, and the control circuit section uses a logic circuit configuration using an error detection code. Using the configuration of a conventional logic circuit with a built-in error detection function using duplication, logic circuits having three types of error detection capabilities are mixed.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, 1 is a data calculation section corresponding to the first circuit column, 2 is an error detection section, 3 is an error detection code correction section corresponding to the second circuit column, 110 is a data input terminal, and 111 ~1
14 is a data calculation circuit, 115 is a data output terminal, 12
1 to 124 are error detection circuits, 130 is an error detection code input terminal, 131 to 134 are error detection code correction circuits, 135
is an error detection code output terminal, 141 to 144 are control signal input terminals, and E121 to E124 are error detection signal output terminals. In this embodiment, an input data signal input from the data input terminal 110 is transmitted to the control signal input terminals 141 to 144 in the process of propagating through the serially connected arithmetic circuits 111 to 114 constituting the data calculation section 1. A predetermined calculation is performed according to the input signal, and the result is output from the output terminal 115. On the other hand, error detection code correction circuits 131 to 134 respectively corresponding to the arithmetic circuits 111 to 114 in the first circuit array are provided in the error detection code correction unit 3.
Control signals input from input terminals 141 to 144 are also input in the same manner. The circuits 131 to 134 apply corrections corresponding to data operations to the error detection code input from the error detection code input terminal 130. Further, error detection circuits 121 to 124 corresponding to circuits 111 to 114 and 131 to 134 are provided in the error detection unit 2, respectively. The outputs of each stage of the data calculation unit] and the error detection code correction unit 3 are input to the error detection circuit of the corresponding stage. Error detection results that are erroneous from the calculation data and error detection codes in each stage of these circuits are output to output terminals E121 to E124, respectively. For example, when parity is used as an error detection code, the parity bit I of the input data is input to the error detection code input terminal 130, and the error detection code correction circuit 131
- 134 perform correction so that a parity determined according to the calculations in each stage of the arithmetic circuits 111 - 114 is obtained as an output, while in each of the error detection circuits 121 - 124 , each of the error detection code correction circuits 131 - 134 performs a correction. The corrected parity is compared with the parity of each calculation output of the calculation circuits 111 to 114 by a parity check, and the result is outputted to the output terminals E121 to E]24. This makes it possible to detect a 1-bit error in the output of the arithmetic circuit, similar to the duplication in the prior art.

Further, in this embodiment, data and parity pits corresponding to the data are input as described above, and calculations for the former and corrections for the latter are performed in 1) 12 columns. As a result, the parity output can be obtained almost simultaneously with the data output, reducing calculation time. Also, since the number of parity bits is smaller than the number of data bits (normally, a parity bit is added to 8 bits of data), it is necessary to add an error detection code correction unit 3, etc. in order to apply this embodiment. The scale of the circuit is smaller than that of the data calculation unit 1, and the layout area can be reduced compared to when the calculation units are duplicated.

Therefore, according to this embodiment, high speed and high integration can be achieved at the same time. In the conventional example shown in FIG. 2, the input signal is input to the parity check circuits PCA and PCB.

FIG. 5 is a block diagram showing an embodiment in which the present invention is applied to A L tJ. A0 to A in FIG.

is A input data, B0-B is B input data, 6 guns are carried manually, 80-S are calculation control signals, F.

~F is the calculation result, CO is the carry output, P^ is the parity of the 6-input data, PB is the parity of the B input data, 3
110 to 3113 are circuits forming the first stage calculation circuit 311 of the data calculation unit 1; 3120 to 3123 are circuits forming the second stage calculation circuit 312 of the data calculation unit 1;
30 to 3133 are the third stage circuits 313 of the data calculation section 1
The circuits 3140 to 3143 that constitute the data calculation unit 1
The circuits constituting the fourth stage circuit 314, DEC is a decoding circuit, and CG is a carry generation circuit. Next, the operation of this embodiment will be explained.

In Fig. 5, six input data A0 to A3, B input data B
. -B, and the calculation control signal S for the carry human CI.

-8, performs the arithmetic operation or logical operation selected by , and the operation result F. -F, and carry output C○ is obtained.

Further, in this embodiment, parity is used as an error detection code, and the parity P^ of the A input data and the parity PB of the B input data are input to the ALU together with the data, and the parity of the operation result is output to the PF. The first stage circuit 311 of the data calculation section is B CD (B 1nary C
This stage corresponds to the BCD operation, and when performing the BCD operation, 6 is added to only the B input data. Corresponding to this calculation, the first stage circuit 331 of the error detection code correction section 3 (hereinafter referred to as the correction section) corrects the parity PB. Both outputs are input to an error detection circuit 321 where a parity check is performed, and errors in the first stage and errors in the input data are detected. Subsequently, the second stage arithmetic circuit 312 of the data arithmetic unit 1 receives the arithmetic control signal S. Perform the arithmetic or logical operation selected by -8. For arithmetic operations, this stage operates as a half adder, and carry operations are performed in the next stage. The circuit 3123 consists of a carry generation signal generation circuit G1, a carry propagation signal generation circuit P3, and a NOR circuit (5PIN OR).
It has the same configuration as 3, and HA, ~HA, are half adder outputs. On the other hand, the second stage circuit 332 of the correction section 3 performs parity correction using the parity PA and the first stage output PD. These outputs are input to the error detection circuit 322,
A parity check is performed.

Similarly, the third stage performs a carry operation for arithmetic operations, and the fourth stage performs 16 operations for BCD operations, as well as parity correction and parity check. Note that the circuit 3133 consists of an exclusive OR circuit EOR3, the circuit 314 consists of a 16-circuit MP, circuits 3130 to 3132 each have the same configuration as the circuit 3133, and circuits 3140 to 3142 each have the same configuration as the circuit 3143.

In this embodiment, as in the example shown in FIG. 1, the parity output is obtained substantially simultaneously with the data output, so that the calculation time is shortened. Furthermore, in this embodiment, the data calculation unit 1 requires four circuits per stage, whereas the error detection unit 2 and the correction unit 3 each require one circuit, so when comparing the data calculation unit 1 by duplicating it, Compared to , circuits and failures can be reduced! The noise-out area is also reduced. In this embodiment, parity bits 1 to 1 are added to 4 bits of input data, but
It is common for parity bits 1 to 1 to add 1 bit to 8 bits of data, and in this case, the effect of reducing the layout area by the present invention is even greater.

It should be noted that the present invention has a structure and function different from those of the above embodiments.
LU (e.g. ALU without BCD calculation function)
It can also be implemented in the same way.

Next, FIG. 6 shows a circuit 3 constituting the first stage of each of the data calculation section 1, correction section 3, and error detection section 2 of the embodiment shown in FIG.
11, 321, and 331 are shown as examples. In the figure, ] and OO are +6 circuits.

PPB is a +6 correction circuit, 101 to 104 are output selection circuits, B0 to B3 are B input data, D0 to D are output data of the data calculation circuit 311, PD is the output parity of the correction circuit 331, and DECI is a calculation control signal. be.

The arithmetic circuit 100 performs an operation to add 6 to the B input data B, -B, and the - force selection circuits 101 to 104 select the control signal DECI from uO+ according to the control signal DECI.
In the case of +, the value after adding 6 is calculated, -D, the parity pit corresponding to that value is output to po, and the control signal D
If the ECI is II I ++, use the value without addition. - PD the parity bit corresponding to that value in B3.
Output to.

Output data D obtained by adding 6. The logic of -D can be expressed as follows.

D3=B engineering+B2+B.

D2=B,・B20B・B2 D1=B□ D0=B.

On the other hand, as a result of the above operation, the parity is inverted because of B.
B, +B1·B2·B', = 1, and this correction is performed by the correction circuit PPa.

As a result of these, if there is no error in the calculation, the output data D0~
The parity of D is equal to the output parity PD of the correction circuit PPB, and by comparing them in the error 1j detection circuit 321, a 1-bit error can be detected.

Next, FIG. 7 shows the second stage circuit 3 of the data calculation section l in FIG.
This figure shows an example of 12 functions.

The circuit performs predetermined calculations shown in the figure in response to calculation control signals Sfl to s3. In the figure, 6° (n=o to 3) is the carry generation signal generation circuit G in the circuits 3120 to 3123.

-G (However, in FIG. 5, the carry generation No. 43 generation circuit G in 3120 to 3122. -62 is not shown), and Po (n=0 to 3) is the output of the circuit 312.
Carry propagation signal generation circuit P0 to P within 0 to 31.23
, (however, the circuits P0 to P2 within 3120 to 3122 are not shown in FIG. 5). Also, HAn(
n=o-3) represents the output of circuits 3120-3122.

As shown in this figure, the parity of the output HAn is P^(An
Pn (parity of Bn), Po (parity of Dn) -PAI3 (parity of An·B), and Ps: (parity of A,·B).

FIG. 8 is an example of an error detection code correction interval vJ 332 corresponding to the arithmetic circuit 312 having the function shown in FIG.

The parity of the arithmetic circuit output is determined as parity P^+ PRI Po- and data A according to the arithmetic control signals S0 to S3.

-A, , Bo-B. In FIG. 8, 601 is a PAR generation circuit, 602 is a PAR generation circuit, and 6
03 is a parity selection circuit, and 604 to 610 are input terminals of the parity selection circuit 603. The input terminal 604 has P
1leP nQ P AB input terminal 605 has P8ΦPAB of P^, input terminal 606 has P8, input terminal 60
F'[3 of P^ is inputted to 7, Pn is inputted to the input terminal 608, PAtDPo is inputted to the input terminal 609r, and O is inputted to the terminal 610. The parity selection circuit 603 receives the control signal S. ~S.

Select the appropriate human power and output it to P332.

Now, in the embodiment shown in FIG.
]24 is provided for each stage. For example, when parity is used as an error detection code, 1 in each stage of the circuit is provided.
Bit errors can be detected.By the way, the error detection capability of the conventional example shown in FIG.
There is 1 bit in the entire circuit including U1, Ar, and U2. Therefore, in the embodiment of the present invention using parity bits, if the error detection capability is set to 1 bit for the entire circuit as in duplication, the number of error detection circuits can be reduced compared to the embodiment of FIG.

Next, an embodiment in which the number of error detection circuits is reduced will be described.

Generally, when multiple stages of circuits are connected in series such that a parity error is propagated to the output signal when a signal containing a parity error is input, a parity check is performed on the output signal of the final stage. It is possible to detect a 1-bit error that occurs in a circuit midway through the process. Therefore, when the error detection capability is set to 1 bit for the entire circuit, parity check circuits need only be provided at the output of the final stage and at the input of the circuit where parity errors are not propagated. FIGS. 9 and 10 respectively show examples of a circuit in which parity errors are not propagated and a parity check circuit for its input signal, and the following description will be made using these examples.

Figure 9 shows an example where parity degenerates.
01, 703 is a data calculation circuit, 702, 704 is a parity correction circuit, 705 is a parity check circuit, 710
~711 is an input signal of the data calculation circuit 701, 712~
713 is an input signal of the data calculation circuit 703, 720-7
23 is an output signal of the data calculation circuit 703, P2O3 is an input signal of the parity correction circuit 702, P2O3 is an output signal of the parity correction circuit 704, and P7O5 is an output signal of the parity check circuit 705. Note that the data calculation circuit 701 in FIG. 9 corresponds to one of the data calculation circuits 111 to 113 in FIG. A parity check circuit 705 is included in the correction circuit.
is a data calculation circuit 701 and a parity correction circuit 702
The data calculation circuit 703 is used as the data calculation circuit at the next stage of the circuit 701, and the parity correction circuit 704 is used as the error detection code correction circuit corresponding to the data calculation circuit 703. Each corresponds to a circuit. In the arithmetic circuit 703, a signal having the same polarity as the input signal 712 is outputted as an output signal 720, and an inverted signal is outputted as an output signal 721. Furthermore, similarly to the input signal 713, bipolar signals are output as output signals 722 and 723, respectively.

At this time, the output signals 720 to 72 of the data calculation circuit 703
The parity of 3 is always even, and the output parity P704
is always 0 (in case of even parity). In this way, the output parity P704 of the arithmetic circuit 703 is determined by the input data 712.
~713, it degenerates to an even number. Therefore, even if there is a parity error in the input signals 712-713 of the circuit 703, it is not propagated to the output signals 720-723. Therefore, the parity check circuit 70
5 to detect errors in the arithmetic circuits before 701.

Next, FIG. 1o shows an example in which a 1-bit error occurring in the arithmetic circuit becomes a 2-bit error in the output signal of the circuit, so that a normal parity check cannot detect (j4). In FIGS. 10(a) and 10(b), 801, 804, 805 are data calculation circuits, 803,
808 is a parity correction circuit, 802 and 806 are parity check circuits, 804 and 805 are logic circuits in 801,
810° 811 is the input signal of 801, 812, 813 is the output signal of 801, P2O3 is the parity input of 803,
P2O3 is the parity output of 803, and P8O2 is the output signal of 802. Note that 801 in FIG. 10(a) is the first
Data of any one of 111 to 114 in the figure) To the arithmetic circuit,
803 corresponds to one of the error detection code correction circuits 131 to 134 corresponding to 801, and 802 corresponds to 801 and 803.
These correspond to any one of the error detection circuits 121 to 124 corresponding to the error detection circuits 121 to 124, respectively.

First, in the circuit of FIG. 10(a), a 1-bit error occurring in the logic circuit 804 may become a 2-bit error in the output signal of the arithmetic circuit 801. For example, if the input signals 810 and 811 are both u l ++, the output signals when there is no error are 812 and 813, both II O#
It is. Here, when an error occurs in the logic circuit 804 and the output of the same circuit becomes u 1 ++, the output of the logic circuit 805 is also inverted, and both 812 and 813 become 111 ++. In this case, two bits of the output are inverted at the same time, so
Errors cannot be detected only by checking the parity of output a. To detect this, it is necessary to provide a parity check circuit 802 to perform a parity check. Since the input data to the parity check circuit 802 does not change by 1 pin I-L even if an error occurs in the logic circuit 804, the error can be detected by parity check.

Now, although the example of FIG. 10(a) looks like a different configuration from other embodiments (for example, FIG. 6), the arithmetic circuit 801 is
If you rewrite it by dividing it into 04 and 805, you will get Figure 10 (
As shown in b), it can be seen that the configuration is the same as the other embodiments. That is, parity correction circuits 807 and 808 correspond to arithmetic circuits 804 and 805, respectively. Furthermore, as in the above example, the parity correction circuit 808 may not be able to correct parity correctly.
It can be seen that this is because the correction data of No. 8 is taken from the input of the calculation circuit 804 instead of from the input of the calculation circuit 805.

As mentioned above, circuits in which parity errors do not propagate include (1) circuits in which the data parity is degenerated as shown in Figure 9, and (2) circuits in which a 1-bit error inside the circuit outputs as shown in Figure 10. For example, there is a circuit that changes to an even number of errors of 2 or more bits. Therefore, although it is necessary to perform a parity check on the input data in stages using such circuits, the parity check can be omitted in other stages.

FIG. 11 is an embodiment based on the embodiment shown in FIG. 1, in which the parity check circuit is omitted as described above. In the figure, OR9 is an OR circuit.

E900 is a parity error detection signal output terminal. Also, it is assumed that only 113 of the arithmetic circuits 111 to 114 corresponds to the above item (requires parity check of input data). Examples of such arithmetic circuits include arithmetic circuit 703 shown in FIG. 9 and arithmetic circuit 801 shown in FIG. 10(a). In the embodiment of FIG. 11, only parity check circuits 122 and 124 are necessary to achieve the same 1-bit detection capability as duplication. In addition,
In this embodiment, the outputs of these parity check circuits are further combined by an OR circuit R9 and output from a terminal E900. By adopting the configuration shown in this embodiment, the number of parity check circuits can be reduced.
The layout area can be reduced.

FIGS. 12 and 13 show an embodiment in which the present invention is applied to a carry lookahead type ALU. Regarding the carry look-ahead addition circuit, for example, see Keikichi Tamaru's "Fundamentals of Logic Circuits" No. 220.
It is stated on page. First, in Figure 12, 1901
is a 4-bit ALU as shown in FIG. 5 or FIG.

1902 is a carry lookahead generator section, and 1903 and 1904 are carry lookahead sections in the carry lookahead generator section 1902.
It is a generator circuit. carrie lookahead
Generator circuit 19 in generator section 1902
03 and 1904 are circuits with the same configuration, and due to this duplication, the carry lookahead generator section 19
Error detection within 02 is performed. Next, Figure 13 is 1 of Figure 12.
902. In this figure, 10
01.1002 are 4-bit ALUs, CMPlooI, CMPIOII, respectively corresponding to 1901 in FIG.
CG1002, CG1002 are comparison circuits, CG100I, CG1002 are carry lookahead generators, GPlooI.

GPIOII, GP1002. GP1012 is a carry lookahead generate/propagate signal generation circuit. In Figures 12 and 13, 19
Error detection inside the 4-bit ALU of 01, 1001, and 1.002 is performed using the same configuration as the embodiment shown in FIG.
Error detection in 02 is performed by duplicating the circuit.

That is, GPlooI and GPIOII, GP1002 and GP1012, CG], OO1 and CG1002.
Each set is a duplicated circuit pair, and CM P 1
001, CMP 1011.

CM, R1002, CG1002゜CMP 1003, CMP] Error detection is performed by the comparison circuit of ○04. The reason why the configuration of this embodiment is adopted is as follows.

(1) In the ALU section, the circuit scale is large, so error detection by duplication will increase the layout area considerably, but by adding parity pits, error detection can be performed with a relatively small detection circuit. .

(2) On the other hand, since the circuit scale of the carry lookahead generator section is relatively small, error detection by duplication is more advantageous in terms of layerer 1 area.

In this way, depending on the characteristics of the logic circuit, a logic circuit with a configuration using an error detection code such as parity and a logic circuit with a configuration using 1-overflow detection by duplication of circuits can be used, and dual plate circuits can be mixed. As a result, overall speed and integration can be increased at the same time.

Next, we will explain an embodiment in which the scope of application of the present invention is expanded not only to the ALU section but also to the entire arithmetic section including the ALU etc.@ In Fig. 14, 15 is the arithmetic circuit section, R1501, R
1502 is a register, PP1501. PP1501 is a pre-shifter.

DLL501 to D L1.503 are data latches, P
L1501 to PS1503 are parity latches, 5H15
01,5H1502 is a shift circuit, PP1501. PP
1502. PP15 is a parity pre-3111 circuit, PCl
5 is a parity check circuit, DSEL15 is a data selection circuit, PSEL1, 5 is a parity selection circuit, ALU15
is an ALU.

Here, the ALU 15 in the arithmetic circuit unit 15 is shown in FIG.
The parity prediction circuit PP15 corresponds to the data calculation section 1 in FIG. 5 or FIG. 11, the parity prediction circuit PP15 corresponds to the error detection code correction section 3, and the parity check circuit PC15 corresponds to the error detection circuit 124 or 324, respectively. That is, the parity bit I- is input to the arithmetic circuit unit 15 together with the data to be arithmetic, and the
In parallel with data calculation in LU15, parity prediction circuit PP15 performs parity prediction calculation corresponding to the calculation result. Both the calculation result and the predicted parity are outputted from the calculation circuit section 15 as outputs F and PF, respectively, while the parity check is performed by the parity check circuit PCl5 to prevent errors in the input data of the circuit section and errors during the calculation operation. Detect errors. Therefore, the operation of the arithmetic circuit section 15 is the same as in the embodiments shown in FIG. 1, FIG. 5, or FIG. 11 described above. In the embodiment shown in FIG. 14, the preshifter PS1501°PS1
Shift circuit S H1501 within 502.

The output of 5H1502 is added, and as a parity focus input, the parity prediction circuit PP1501゜PP in the preshifter PS1501゜PS1502 is added.
Add the output of 1502. With the configuration shown in this example, data latch (DL1501, DL1502) → shift circuit (SH1501゜5I11502) → ALU (
ALU15) → Data latch (DLl, 503) → Parity latch (PP1501, PP1501) → Parity prediction circuit in preshifter (PP1501.PP150
2) → Parity prediction circuit (PP15) in the arithmetic circuit section →
A parity bus consisting of a parity latch (PP1501) is formed. These two types of buses include a data latch DL1501 and a parity latch PL1501. There is a set of corresponding circuits such as a shift circuit 5H1501 and a parity prediction circuit PP1501, and errors can be detected by performing a parity check using the output data and parity bit of each set. (Note that the errors referred to here include input data errors and circuit malfunctions.) Therefore, by detecting mismatch between the data bus and the parity bus with the parity check circuit PCl5 provided in the arithmetic circuit section 15, Errors in all data buses can be detected,
This eliminates the need for an error detection circuit for ALU input data, which was required in the prior art, and it is possible to reduce the layout area and increase the integration of the LSI chip.

FIG. 15 shows the preshifter PS1501 shown in FIG.
PS1502(7) - An example is given. In the figure, A7 to Ao are data input terminals, P^ is a parity input terminal, SHI7 is a shift circuit, PP17 is a parity prediction circuit, SA7 to SA0 are data output terminals, PS^ is a parity output terminal, and DS1700 to DS1707 are data Selector, PSEL17 is parity selector, EOR1
7 is an EOR' (Exclusive-OR) circuit. This preshifter has a function of inputting 8-bit input data and parity bits and outputting the data as is without changing the data or by shifting the data by 1 bit to the left and outputting the data together with the corresponding parity bit. Here, the parity prediction circuit PP17 uses input data and input parity bits to predict parity bits for output data, and outputs the predicted parity bits from Ps^. Note that even in a preshifter having functions other than those described above, parity bits can be similarly predicted and output by changing the parity prediction circuit.

As described above, by applying the present invention to the arithmetic section on an LSI chip, duplication of arithmetic circuits becomes unnecessary and the number of error detection circuits can be reduced, so that the layout area can be reduced.

In the embodiments of FIGS. 12 and 13, the carry lookahead generator section includes a circuit (e.g.
Generate/propagate signal generation circuit GP, carry lookahead generator CG) are duplicated,
The configuration is such that the outputs of both duplicated circuits are collated by a comparison and verification circuit to detect errors, but in this configuration, as described in Figure 4, a diagnostic circuit is used to detect errors in the comparison and verification circuit. Is required. Moreover, this diagnostic circuit requires one diagnostic circuit for each bit of the output of the duplicated circuit, so a large number of diagnostic circuits are required, for example, 32 diagnostic circuits are required for a 32-bit logic circuit. It becomes necessary. In the present invention, the power supply system for clock signals to each duplexed arithmetic circuit is divided into a power supply system for clock signals to a switch circuit that takes out the output signal of a logic circuit network in the arithmetic circuit to the outside, and a power supply system for clock signals to the switch circuit that takes out the output signal of the logic circuit network in the arithmetic circuit to the outside. By dividing the power supply into two systems, the power supply system for the clock signal to the switch circuit, and the power supply system for the clock signal, the arithmetic circuit itself can have the diagnostic function of the comparison and verification circuit.As a result, the diagnostic circuit is unnecessary and the layout area is reduced. It is possible to further reduce the speed of the comparison circuit and increase the speed of the comparison and verification circuit.

FIG. 16(a) shows the configuration of an embodiment of a logic circuit using duplication as an error detection method, and FIG. 16(b) shows its operating waveform. Figure 16 (
In a), 1100 is a logic circuit with a built-in error detection circuit;
1101 is an arithmetic logic circuit, 1102 is an error detection logic circuit with the same circuit configuration as 1101, All, Bll, C1
l.

Dll is the input signal common to 1101 and 1102, ○U
TIIOI is the output signal of ]101, ○UT1102 is 1
102 output signal, EORII is a comparison circuit, ERI]
are error detection signals, P1101 to P1105 and pHll
~P1115 is PMO8FET, N1101~N110
6 and N11ll~N1.116 are NMO3FETs,
1103.1104 is an internal node of 1101, 111
3.1114 is the internal node of 1102, CIN, TC
O.

TCI is a clock signal, To, T□ are diagnostic control signals, T
C is a clock generation circuit, ANDIIIOl.

AND1102 is an AND circuit within the TC. It should be noted that Japanese Patent Laid-Open No. 62-98827 is related to the dynamic logic circuit shown in this embodiment.

In this embodiment, All to Dl in the logic circuit 11o1
FET Nll0I~N110 for l input signal
The logic circuit network No. 4 performs the calculation All.C11+B11.Dll, and the calculation result is output to 0UTIIOI via FET N1105 and a buffer circuit (consisting of FETs P1105 and N1106). On the other hand, the same operation is performed in the logic circuit 11o2, and the result is output to 0UT1102. These outputs are compared and verified by a comparison and verification circuit EORII to detect errors in the calculation results. In the conventional example shown in Fig. 4, CI
N.

While the same clock signal is applied to TCO and TCI, in this embodiment, the result of ANDing the clock signal CIN and the diagnostic control signal To is applied to the clock signal TC.
O, clock signal CIN and A of 1 diagnostic control signal T1
The circuit operation of the embodiment for using the result of the ND operation as the clock signal TCI will be explained using the operating waveforms shown in FIG. 16(b).

In FIG. 16(b), the solid line indicates the comparison circuit EO.
The waveform during RII diagnosis and the broken line indicate the waveform during normal operation. First, the normal operation indicated by the broken line will be explained. In this case, by setting the diagnostic control signals TCO and TCI to a high level, the clock signals TCO and TCI become clock signals in phase with the clock signal CIN, as in the conventional example. Note that logic circuits 1101 and 1102
Since they have the same configuration, the operation of the logic circuit 1101 will be explained below, and the explanation of the logic circuit 11o2 will be omitted. First, in order to perform a precharge operation prior to calculation, the input signals All to Dll are set to low level, and the clock signal CI
When N is set to low level, clock signal TCO becomes low level. This allows PMOS FET5 P11
01 to P1104 are on state, N M OS F E
T5N1101 to N1105 are turned off, the parasitic capacitances existing at the node 11o3 and the node 11o4 are charged, the potentials of these nodes rise to high level, and the precharge operation is completed. Next, when the clock signal CIN is set to high level to start the calculation operation,
The clock signal TCO becomes high level, and the PMOS
FET5 PIIOI to P1104 are turned off. Here, when part or all of the input signals All to Dll are set to high level so that the node 1103 and the ground are in a conductive state, the parasitic capacitance existing at the node 1103 is discharged, the potential drops, and the NMO5FET N
1105 is turned on, the potential of node 1104 also drops, and both nodes become low level. Node 1104
is PMOS FETP1105. NMO3FET N
Since it is connected to the gate of a CMOS inverter consisting of 1106, 0UTIIOI rises to a high level.

The above is normal operation.

Next, the comparison circuit E shown by the solid line in FIG. 16(b)
The operation of ORII during diagnosis will be explained. This diagnostic operation is performed by setting one of the diagnostic control signals To and Tl to a low level, thereby forcibly setting one of the outputs 0UT11.01゜0UT1102 corresponding to the diagnostic control signals To and Tl to a low level. . In the following description, a case will be described in which the diagnostic control signal TO is set to a low level.

First, the precharge operation is performed using the clock signal C as in normal operation.
This is done by setting IN to low level, and node 1
103 and node 1104 are set to high level. Next, in order to perform an arithmetic operation, the clock signal CIN is set to a high level, but if the diagnostic control signal TO is at a low level at this time, the clock signal TCO remains at a low level, unlike during normal operation.

Here, if input signals All to Dll are applied that cause conduction between the node 1103 and the ground, the node 110
3 drops to low level as in normal operation, but since the clock signal TCO is low level, NMO
3FET N1105 is not turned on. Therefore, node 1104 is kept at a high level, and the output signal 0U
The potential of TIIOI becomes low level. As described above, in this embodiment, by setting either one of the diagnostic control signals To and Tl to a low level, one of the inputs of the comparator circuit EORII can be fixed to a low level, and using this, the comparator circuit E
A diagnosis of ORII can be made. In the above explanation, T.

and T1. TCO and TCI, Pllol-P1105 and P
1111~P1115゜Nll0I~Nl 106 and N
l 111~Nl 116. Nodes 1103-1104
and 1113-1114-. 0UTIIIOI and ○UT11
If 02 is read separately, the explanation will be regarding the logic circuit 1102.

Comparing this embodiment with the conventional example shown in FIG. 4, it has the following features.

(1) The diagnostic circuit 1303, which is necessary in the conventional example to diagnose the comparison circuit EOR13, becomes unnecessary by applying the present invention. This makes it possible to reduce the layout area of the logic circuit and the delay time of the error detection signal at the same time.

(2) During normal arithmetic operation, the circuit of this embodiment performs exactly the same operation as the conventional circuit, so even if the present invention is applied, the arithmetic time does not increase.

In the embodiment shown in FIG. 16(a), the clock generation circuit T
Clock TCO for delay time of C.

Although the phase of TCI is delayed compared to clock CIH, if the former is determined before input signals All to Dll, there is no effect and the calculation time does not increase. Furthermore, by changing the clock generation circuit TC, it is possible to make the clock CIN and the clocks TCO and TCI have the same phase, and in this case, it is possible to supply exactly the same clock as in the conventional example.

In the embodiment shown in FIG. 16(a), the logic circuit 1101 is a circuit that performs the calculation 0UT1101=A11・C11+B11・Dll, but the logic circuit 1101.
NMO3FETs in 1102 N1101 to N1104
By changing the configuration of the logic circuit network section consisting of and N11ll to N1114, a logic circuit that performs operations other than those described above can be realized.

Next, Fig. 17 shows the logic circuit 1 with built-in error detection circuit shown in Fig. 16.
This shows an example in which a plurality of 101 are used. In the figure, 1201 to 1204 are respectively 1100 in Figure 16.
A logic circuit with a built-in error detection circuit having the circuit configuration shown in
1201~Al2O4 and B1201~B1204 and C1201~C1204 and D1201~ER1204
are error detection signals of the logic circuits 1201 to 1204, 0R12 is an OR circuit, and E1200 is an error detection signal. In this embodiment, there are four logic circuits 1201 to 1204.
One clock generation circuit TC is provided for each clock to supply clock signals CIN, To, and Tl. Further, in this embodiment, the error detection signals ER1'201 to ER1204 of each logic circuit are combined by an OR circuit ○R12 and outputted as an output signal E1200. In an LSI, it is common to operate a large number of logic circuits in synchronization with one clock signal to perform calculations. In this case, a configuration like the embodiment shown in FIG. 17 is adopted, and since only one clock generation circuit for multiple logic circuits needs to be provided on the same chip, the overall layout area can be reduced. can.

FIG. 18 is a diagram showing another embodiment of the dynamic logic circuit used in the present invention. 1401 is a logic circuit, P1
401~P1403 are PMO8FET, N1401~N
1407 is an NMO5FET, and 0UT1401 is an output signal of the logic circuit. This circuit 14o1 is NMO5FET
The present invention is applied to a type of dynamic logic circuit in which an NMO3FET N1405 is inserted between the logic circuit network section consisting of sN1401 to N1404 and the ground, and has the same functions as the logic circuits 1101 and 1102 in Fig. 16(a). Therefore, it is possible to provide the comparison circuit with a diagnostic function without any problems.

FIG. 19 shows a logic circuit having the three types of error detection functions described above, namely (1) a logic circuit using error detection codes such as parity (for example, the embodiments of FIGS. 1 and 11); (2)
Although the circuit is duplicated, it has a built-in error detection circuit diagnostic function.
A logic circuit with a built-in diagnostic function for an error detection circuit with a reduced number of circuits (for example, the embodiments shown in FIGS. 16 and 17) (3) A logic circuit with a built-in error detection circuit by simply duplicating the circuit (for example, the logic circuit in FIG. 4) This figure shows an example of an ALU configured by mixing logic circuits with these three types of configurations, using different types of logic circuits. In FIG. 19, CG18 is a carry lookahead generator, 1801 to 180.
6 is carry lookahead generator CG18
A logic circuit to which the configuration of (2) above is applied, EOR18
01 to EOR1803 are EOR circuits, ○R1800 is an OR circuit, CTRL is a control circuit, 180 is a control signal input terminal, T,, T are diagnostic control signals, 1807 to 1814 are control signal generation circuits, 1815 to 1818 are for diagnosis circuit,
EOR1804 to EOR1807 are EOR circuits, 0R1
801 is an OR circuit, and ER1800-ER1801 are error detection signal output terminals. In this embodiment, logic circuits having an error detection function by parity check are used in the data calculation section 1 other than the carry generator CG18 and the parity generation section 3, as in the example shown in FIG. On the other hand, carry lookahead generator CG
18 shows Fig. 16.

Similar to the example in FIG. 17, error detection is performed by duplicating the circuits 1801 to 1806, and the error detection circuit EOR18 is
A logic circuit having a built-in diagnostic function of 01 to 1803 is used. In addition, the control circuit CTRL uses error detection by duplicating circuits 1807 to 1814, as in the conventional example shown in FIG.
807 diagnostic circuits 1815 to 1818 are provided, respectively.

By properly using logic circuits with three types of error detection functions in this way, (1) The ALU section consisting of 1.3 generates parity in parallel, and uses this to perform parity check. , it is possible to increase the speed of the vapor output and reduce the circuit scale compared to the conventional duplex configuration.

(2) Carry lookahead generator C
In the G18 section, error detection is performed by duplexing, but by making use of the characteristics of the precharge circuit and incorporating the diagnostic function of the error detection circuit, it is possible to reduce the number of circuits and increase the speed of the error detection signal.

(3) The control circuit CTRL needs to be configured as a static circuit because it is necessary to hold the control signal output for two or more cycles, and since no parity pit is input to the control signal input terminal 180, Error detection uses the same logic circuit configuration as the conventional example. However, the number of locations to which the logic circuit of this configuration is applied can be kept to a minimum, and the ALU of this embodiment can achieve higher speed and higher integration as a whole.

〔Effect of the invention〕

According to the present invention, (1) the parity output can be obtained almost simultaneously with the data output of the arithmetic circuit, and when applied to a 32-bit ALU, for example, the speed can be increased by about 20%. Furthermore, a 1-bit error during calculation can be detected by the parity bit, and the same level of reliability can be obtained without duplicating the circuit. Furthermore, since the area of the parity correction circuit, parity check circuit, etc. can be made smaller than that of one conventional arithmetic circuit, when the circuits are duplicated, the comparative layout area can be made equal to or less than that.

(2) Furthermore, when the present invention is expanded and applied to the entire calculation section, the number of circuits required for error detection can be reduced.

(3) When error detection by duplication of circuits is also used, a function for diagnosing a circuit that performs comparison and verification can be incorporated into a dynamic logic circuit without impairing its high speed.

The above has the effect of increasing the speed and integration of the arithmetic unit having error detection capability.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, and is a block diagram of a logic circuit using an error detection code. FIG. 2 is a block diagram of a conventional example in which the ALU section is duplicated to detect errors. 4 is a block diagram showing an example in which error detection by duplication of circuits is applied to an arithmetic unit consisting of an ALU, a register, and a preshifter;
The figure is a block diagram showing an example of a logic circuit having a diagnostic function for an error detection circuit, FIG. 5 is a block diagram showing an embodiment in which the present invention is applied to an ALU, and FIG. 1
A diagram showing an example of the circuit in the second stage, FIG. 7 is a diagram for explaining the function of the second stage circuit of the data calculation section in the embodiment in FIG. 5, and FIG. 8 shows errors in the embodiment in FIG. 5. FIGS. 9 and 10 are diagrams showing examples of circuits in the second stage of the detection code correction section; FIGS. 11 and 11 are diagrams showing examples of circuits that require parity checks;
The figures are block diagrams of one embodiment of the present invention, Figures 12 and 13.
14 is a block diagram of an embodiment in which the present invention is applied to an arithmetic unit, and FIG. 15 is an implementation of the embodiment shown in FIG. 14. A block diagram showing an example of a preshifter used in the example, FIG. 16(a) is a logic circuit with a built-in error detection circuit according to an embodiment of the present invention, and FIG. 16(b) is a block diagram showing an example of the preshifter used in the example.
FIG. 17 is a diagram showing an example of the operation waveform of the circuit shown in FIG. FIG. 19 is a diagram showing an embodiment in which the present invention is applied to a carry lookahead generator type ALU. 7th P, F Do Fig. 4 Hoshiji J-Hito 1', tr: Aftea 8°yte Ft: Jtsu・
・1. No＼＾yti P: ρ bond 9 no 09 run FA-a: A to゛I＾98°kushi ・3: A＾゛5
9th generation? vertical 4 figure 8
/ μ HiroF PF and 75th Full Sister 7'5 #l) 7 β) f17 1st Otsu Ward

Claims (1)

[Claims] 1. A first circuit array that inputs input data to a plurality of stages of serially connected arithmetic circuits, performs predetermined arithmetic operations while the input data is propagating through the arithmetic circuits, and obtains output data. and an error detection code correction circuit that corrects the error detection code in response to the operation in each arithmetic circuit in the first circuit array by inputting the error detection code corresponding to the input data, is connected in series, a second circuit string that outputs an error detection code corresponding to the output data; and an output of the arithmetic circuit in the first circuit string and a corresponding error detection code correction circuit in the second circuit string. A semiconductor integrated circuit comprising at least one error detection circuit that performs comparison with an output, and a first logic circuit that generates an error detection code and detects errors in the operation in parallel with the operation. circuit device. 2. Claim characterized in that the above error detection circuit is provided at least at the output of the first circuit array and at the input of an arithmetic circuit to which parity errors in the first circuit array are not propagated. 1. The semiconductor integrated circuit device according to 1. 3. It is characterized by comprising a second logic circuit consisting of a duplexed arithmetic circuit having the same function and into which the same signal is input, and a comparison circuit that compares the outputs of the duplexed arithmetic circuit with each other. A semiconductor integrated circuit device according to claim 1 or 2. 4. Each of the duplexed arithmetic circuits includes a logic circuit network that receives an input signal and performs a logic operation, a first switch circuit that precharges parasitic capacitance at an interconnection point of the logic network, and the logic circuit. and a second switch circuit that takes out the output signal of the network, and is divided into two systems: a power supply system for clock signals to the first switch circuit and a power supply system for clock signals to the second switch circuit. 4. The semiconductor integrated circuit device according to claim 3, further comprising a clock signal power supply system for supplying power. 5. Claims 1 to 4, further comprising an ALU consisting of an arithmetic unit constituted by the first logic circuit.
The semiconductor integrated circuit device according to any one of the above. 6. an arithmetic unit configured by the first logic circuit;
4. The semiconductor integrated circuit device according to claim 3, further comprising an ALU including a carry lookahead generator section configured by the second logic circuit. 7. an arithmetic unit configured by the first logic circuit;
5. The semiconductor integrated circuit device according to claim 4, further comprising an ALU comprising the second logic circuit and a carry lookahead generator section configured by the clock signal power supply system. 8. A duplex arithmetic circuit having the same function and inputting the same signal, a comparison circuit that compares the outputs of the duplex arithmetic circuit, and a logic circuit network within the duplex arithmetic circuit. Clock signal power supply system to the switch circuits that take out the output signals, and 2.
It has a clock signal power supply system that divides the clock signal into two systems to supply power to the other switch circuits in the duplicated arithmetic circuit, and when diagnosing a failure, it diagnoses the failure of the comparison circuit. 1. A semiconductor integrated circuit device comprising a first logic circuit. 9. Input data to a plurality of stages of serially connected arithmetic circuits, and perform predetermined arithmetic operations on the arithmetic circuits while the input data is propagating to obtain output data; By inputting the corresponding error detection code, the first
a second circuit string, which connects in series error detection code correction circuits that correct the error detection code in response to calculations in each arithmetic circuit in the circuit string, and outputs an error detection code corresponding to the output data; , at least one error detection circuit that compares the output of the arithmetic circuit in the first circuit array with the output of the corresponding error detection code correction circuit in the second circuit array; 9. The semiconductor integrated circuit device according to claim 8, further comprising a second logic circuit that generates an error detection code and detects errors in calculations in parallel with the second logic circuit. 10. Claim 10, characterized by comprising an ALU consisting of a carry lookahead generator section constituted by the first logic circuit and an arithmetic unit constituted by the second logic circuit. 9. The semiconductor integrated circuit device according to 9. 11. As described above, the clock signal is supplied to each arithmetic circuit by connecting one end of the logic circuit network, which receives at least one input signal, performs a logical operation, and brings the terminals into a conductive state or a non-conductive state, to the first power supply. one end of the first switch circuit is connected to a second power supply, the other end of the logic circuit network and the other end of the first switch circuit are connected to form a first node, Further, one end of a second switch circuit for taking out the signal of the first node is connected to the node, the other end of the second switch circuit is set as a second node, and the second node and the second A first switch in an arithmetic circuit that inserts a third switch circuit between power supplies, connects a buffer circuit to the second node, and outputs a signal of the second node to the outside via the buffer circuit. Claim 8, characterized in that the first clock signal is supplied to the circuit and the third switch circuit, and the second clock signal is supplied to the second switch circuit.
The semiconductor integrated circuit device described in . 12. The semiconductor integrated circuit device according to claim 11, wherein the first, second, and third switch circuits, the logic circuit network, and the buffer circuit are constructed using MOSFETs. 13. The above two systems of clock signals are obtained from the output of a clock generation circuit that generates clocks by inputting an original clock signal input to a logic circuit and a control signal for controlling clock generation. Claim 8
The semiconductor integrated circuit device described in . 14. The semiconductor integrated circuit device according to claim 13, wherein the clock generation circuit is provided on the same chip as a logic circuit to which the output signal of the clock generation circuit is input. 15. A first circuit that performs a predetermined operation on input data and outputs output data, and a first circuit that performs a predetermined operation on the input of an error detection code corresponding to the input data and outputs an error detection code corresponding to the output data. A data bus is formed by a first circuit array including a plurality of arithmetic circuits including a second output circuit, and the first circuits in each arithmetic circuit are connected to each other by the data bus. An error detection code bus is formed by a second circuit array connecting the second circuits in the same arithmetic circuit, and the output data of the first circuit and the output of the second circuit in the same arithmetic circuit are A semiconductor integrated circuit device comprising a logic circuit including at least one error detection circuit that performs verification with an error detection code. 16. The semiconductor integrated circuit device according to claim 15, further comprising an ALU configured by the logic circuit. 17, characterized in that the arithmetic circuit includes at least a part of a latch circuit, a shift circuit, and an addition/subtraction circuit;
The semiconductor integrated circuit device according to claim 15 or 16.