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JPH01278032A - Wire bonding process - Google Patents

Wire bonding process

Info

Publication number
JPH01278032A
JPH01278032A JP63106997A JP10699788A JPH01278032A JP H01278032 A JPH01278032 A JP H01278032A JP 63106997 A JP63106997 A JP 63106997A JP 10699788 A JP10699788 A JP 10699788A JP H01278032 A JPH01278032 A JP H01278032A
Authority
JP
Japan
Prior art keywords
masking material
bonding
bonding pads
wire
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63106997A
Other languages
Japanese (ja)
Inventor
Kazunori Narita
成田　万紀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP63106997A priority Critical patent/JPH01278032A/en
Publication of JPH01278032A publication Critical patent/JPH01278032A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/8501—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To make a device miniaturized and highly integrated by a method wherein bonding pads on a substrate are previously covered with a masking material and after fixing the ambient parts, the masking material is released to expose the clean bonding pads so that the masking material may be wire- bonded onto the exposed bonding pads. CONSTITUTION:Bonding pads 1 on a substrate 16 for wire-bonding metallic fine wires 17 by ultrasonic wave and thermal-pressure fixing process are previously covered with sol state setting resin base masking material 4. Later, after setting the masking material 4 by irradiating it with ultraviolet ray or heat ray, parts 6 around the bonding pads are fixed by soldering or bonding process, etc. Then set masking material 4 is released by physical or chemical processing to expose the bonding pads 1 having clean surfaces so that the masking material 4 may be wire-bonded onto the exposed bonding pads. Through these procedures, the gap between the parts 6 and the bonding pads 1 can be reduced so that a device may be miniaturized and highly integrated.

Description

【発明の詳細な説明】 の１ 本発明は、半導体装置特に混成ＩＣ等や薄膜磁気ヘッド
等のワイヤボンディング接続を行う場合の技術に関する
。DETAILED DESCRIPTION OF THE INVENTION 1. The present invention relates to a technique for wire bonding connection of semiconductor devices, particularly hybrid ICs, thin film magnetic heads, etc.

１皮盆皮直 ワイヤボンディング技術そのものは完成されたもので、
金属細線を用いて、熱や超音波で接続するワイヤボンデ
ィング接続方法は広く、半導体装置の組立、つまり半導
体ペレットとリードフレーム又は基板との電気的接続に
用いられている。さらに、ワイヤボンディング技術は半
導体装置の組立だけではなく、多トラツク薄膜磁気ヘッ
ドの組立てにも利用できる。The 1 skin tray straight wire bonding technology itself has been perfected.
Wire bonding connection methods that use heat or ultrasonic waves to connect thin metal wires are widely used for assembling semiconductor devices, that is, for electrically connecting semiconductor pellets and lead frames or substrates. Furthermore, wire bonding technology can be used not only for assembling semiconductor devices but also for assembling multi-track thin film magnetic heads.

Ｂ　ｆ　°　　　°　　　； ところが、ワイヤボンディング接続方法を半導体装置の
うちでも特に混成ＩＣまたは、薄膜多トラツク磁気ヘッ
ドに利用する場合に問題となることは、つぎのとおりで
ある。つまり混成ＩＣの基板上あるいは磁気ヘッドの基
板上において、ワイヤボンディングを行なう部分、即ち
、ボンディングパッドの近傍に多数のチップ部品または
フレシキブルプリント基板などを半田付けあるいは接着
剤により固着しなければならない場合があり、半田付け
や接着剤固着を実行した場合、半田・半田に含まれるフ
ラックス・接着剤などが基板上を流れてボンディングパ
ッドに達し、ボンディングパッドの表面を汚染すること
がある。周知の通り、ワイヤボンディングにおいてはボ
ンディングパッドの表面の清浄度がボンディングに強度
に大きな影響を与え、半田・フラックス・接着剤などで
汚染された表面に十分な接続強度を有するワイヤボンデ
ィングをおこなうことは不可能である。従来は上記のよ
うなボンディングパッドの汚染をさけるためボンディン
グパッドと半田付けないしは接着剤付けする部品類を距
離的に十分離していたが、そのため、混成ＩＣないしは
磁気ヘッドの小型・高密度化の妨げとなっていた。B f ° ° ; However, the following problems arise when the wire bonding connection method is used for semiconductor devices, particularly hybrid ICs or thin film multi-track magnetic heads. In other words, there are cases where a large number of chip components or flexible printed circuit boards must be fixed by soldering or adhesive to the area where wire bonding is to be performed, that is, near the bonding pads on the hybrid IC substrate or magnetic head substrate. However, when soldering or adhesive bonding is performed, the solder, flux, adhesive, etc. contained in the solder may flow onto the board and reach the bonding pad, contaminating the surface of the bonding pad. As is well known, in wire bonding, the cleanliness of the surface of the bonding pad has a large effect on the strength of the bond, and it is difficult to perform wire bonding with sufficient connection strength on a surface contaminated with solder, flux, adhesive, etc. It's impossible. Conventionally, in order to avoid contamination of the bonding pads as described above, the bonding pads and the parts to be soldered or glued were kept sufficiently far apart, but this hindered the miniaturization and high density of hybrid ICs or magnetic heads. It became.

−゛　−の 本発明においては、基板上のボンディングパッドをワイ
ヤボンディングおよびボンディングパッド周辺の部品の
半田付け・接着剤付けに先立って液体状のマスキング材
によっておおう。その手段はマスキング材を注射器から
ディスペンスする手段または、スクリーン印刷による手
段があり基板の状態に応じて使い分ける。そののち、マ
スキング材紫外線を照射や加熱により硬化させ、後工程
の半田付け、接着材付けにおいて、マスキング材が変形
・はく離・溶融等しないようにする。しかるのちに、ボ
ンディングパッド周辺に所望のチップ部品、フレシキブ
ルプリント板などを半田付けないし接着剤付けする。そ
の後、硬化して皮膜状になっているマスキング材を物理
的または化学的に処理してはく離して清浄なボンディン
グパッドを露出させる。この後は、通常おこなわれるよ
うに半導体ペレット等を基板上の所定の位置に搭載し、
半導体ペレット等と基板のボンディングパッドをワイヤ
ボンディングにより接続する。In the present invention, the bonding pad on the substrate is covered with a liquid masking material prior to wire bonding and soldering/adhesive attachment of components around the bonding pad. This can be accomplished by dispensing the masking material from a syringe or by screen printing, depending on the condition of the substrate. Thereafter, the masking material is cured by irradiation with ultraviolet rays or heating to prevent the masking material from deforming, peeling, melting, etc. during soldering and adhesive application in subsequent steps. After that, desired chip components, flexible printed boards, etc. are soldered or glued around the bonding pads. Thereafter, the masking material, which has hardened into a film, is physically or chemically treated and removed to expose a clean bonding pad. After this, semiconductor pellets etc. are mounted on the predetermined position on the board as usual,
A semiconductor pellet or the like is connected to a bonding pad on a substrate by wire bonding.

１且 本発明によれば、基板上のボンディングパッドをおおう
マスキング材は、半田、半田フラックス、接着剤に侵さ
れることがないので、ボンディングパッド付近に、チッ
プ部品などを半田付は又は接着させる時、ボンディング
パッド表面が汚染されるのを防止することができる。し
かも、本発明では、マスキング材は半田付けや接着が終
わった後、物理的又は化学的処理により、はく離するの
で、ワイヤボンディングする際にはく離した清浄なボン
ディングパッド表面にワイヤを接続させることが可能で
ある。1. According to the present invention, the masking material covering the bonding pads on the board is not attacked by solder, solder flux, or adhesive, so it is easy to use when soldering or bonding chip components near the bonding pads. , it is possible to prevent the surface of the bonding pad from being contaminated. Moreover, in the present invention, the masking material is peeled off by physical or chemical treatment after soldering or adhesion, so when wire bonding is performed, it is possible to connect the wire to the peeled clean bonding pad surface. It is.

実ｆｆｉ 第１図ａ　−ｅに本発明のワイヤボンディング方法の一
つの実施例として、混成ＩＣの組立工程に応用した例を
示す。第１図ａ　−ｅは混成ＩＣの組立の工程の進行順
の図である。第１図ａは組立工程にかかる直前の混成Ｉ
Ｃ基板を示し、１６は混成　ＩＣ基板全体、１はワイヤ
ボンディングのためのボンディングパッド、２はチップ
部品例えばチップコンデンサ、チップコイル、チップ抵
抗、ミニモールドトランジスタ、ミニモールドダイオー
ドなどを搭載して、チッチ部品の端子部と基板とを半田
付けするための基板側の半田付はランドである。３は基
板上に半導体ペレット例えばＩＣ。Actual ffi Figures 1a to 1e show one embodiment of the wire bonding method of the present invention, in which it is applied to a hybrid IC assembly process. FIGS. 1a to 1e are diagrams illustrating the sequence of steps for assembling a hybrid IC. Figure 1a shows the mixture I just before starting the assembly process.
16 shows the entire hybrid IC board, 1 is a bonding pad for wire bonding, and 2 is a chip mounted with chip components such as chip capacitors, chip coils, chip resistors, mini-molded transistors, mini-molded diodes, etc. The soldering area on the board side for soldering the terminal portion of the component and the board is a land. 3 is a semiconductor pellet such as an IC on a substrate.

トランジスタ、ダイオードなどの裸のシリコンペレット
を搭載するための半導体ペレットマウントランドである
。１のボンディングパッド、２の半田付はランド、３の
半導体ペレットマウントランドのいずれも複数個あるの
が通常の混成ＩＣの構成である。第１図すは混成ＩＣ基
板１６上にあるワイヤボンディングパッド１だけを選択
的にマスキング材４でカバーし紫外線又は熱線照射によ
り、マスキング材４を硬化させた図である。マスキング
材４を基板１６上に供給する手段としては注射器からの
ディスペンスと、スクリーン印刷とがあるが、供給位置
および供給量を精密にする必要がある場合にはスクリー
ン印刷の方が向いている。This is a semiconductor pellet mounting land for mounting bare silicon pellets such as transistors and diodes. A typical hybrid IC has a plurality of bonding pads (1), soldering lands (2), and semiconductor pellet mounting lands (3). FIG. 1 is a diagram in which only the wire bonding pads 1 on the hybrid IC substrate 16 are selectively covered with the masking material 4, and the masking material 4 is cured by ultraviolet rays or heat ray irradiation. Methods for supplying the masking material 4 onto the substrate 16 include dispensing from a syringe and screen printing, but screen printing is more suitable when the supply position and supply amount need to be precise.

マスキング材４の材質としては、変成アクリレート系の
樹脂が、２７４℃の半田槽の半田に対する耐熱性があり
、かつ半田のフラックス、フラックスを洗うためのトリ
クロロエタン、フレオンなどに対する耐蝕性も持つため
適当である。第１図Ｃはチップ部品６を混成ＩＣ基板１
６に半田５により半田付けし、フラックスを洗浄し乾燥
を終えたものを示す。この段階では、マスキング材４は
基板に付着している。第１図ｄは、第１図Ｃに示す、チ
ップ部品６を半田付けの完了した混成ＩＣ基板１６から
、ボンディングパッドマスキング材４を物理的引き剥し
又は化学的に粘着性低下なものに変質させはく離し、除
去した状態を示す。この段階で、清浄なボンディングパ
ッド１が露出する。As the material for the masking material 4, a modified acrylate resin is suitable because it has heat resistance against solder in a solder bath at 274°C and also has corrosion resistance against solder flux, trichloroethane for washing flux, freon, etc. be. Figure 1C shows a hybrid IC board 1 with chip components 6.
6 shows the product soldered with solder 5, the flux cleaned and dried. At this stage, the masking material 4 is attached to the substrate. FIG. 1d shows a process in which the bonding pad masking material 4 is physically peeled off or chemically altered into a material with reduced adhesiveness from the hybrid IC board 16 on which the chip components 6 have been soldered, as shown in FIG. 1C. Shows peeled and removed condition. At this stage, clean bonding pads 1 are exposed.

こののち、第１図ｅに示すように、半導体ペレット１８
とボンディングパッド１を、金属細線を用いてワイヤボ
ンディング接続し、混成ＩＣの組立を完了する。After this, as shown in FIG. 1e, the semiconductor pellet 18
and the bonding pad 1 are connected by wire bonding using a thin metal wire to complete the assembly of the hybrid IC.

実ＪｆｌＬ二２− 次に本発明によるワイヤボンディング方法を薄膜磁気ヘ
ッドの組立工程に用いたその他の実施例を第２図ａ−ｆ
を参照しながら説明する。第２図ａは、基板上に多トラ
ツクの磁気ヘッドを形成完了した状態の多トラツク薄膜
磁気ヘッド基板を示し、１０は磁気ヘッド基板、９は磁
気ヘッド主要部、７は磁気ヘッド主要部９と外部回路（
図示せず）を電気的に接続するためのワイヤボンディン
グをおこなうためのもうけであるボンディングパッドで
ある。次に第２図すは、ボンディングパッドが、後につ
づく工程において接着剤により汚染されることを防ぐた
めに、ボンディングパッド７に液体ゾル状マスキング材
１３を塗布した状態示す。マスキング材１３は塗布され
た後に紫外線又は熱線により硬化させられ、このときマ
スキング材の形状は変化しない。次に第２図、Ｃのごと
く、磁気ヘッド主要部９と外部回路（図示せず）を電気
的に接続するための予備段階としてフレシキブルプリン
ト板１２を磁気ヘッド基板１０に、接着剤１１を使って
接着する。このとき当然接着剤１１はボンディングパッ
ド７の方に向かって流れるが、ボンディングパッド７は
前述のとおり硬化したマスキング材１３によって覆われ
ているため、　　　゛ボンディングパッド７が接着剤１
１によって汚染されることはない。次に第２図ｄに示す
ように１、磁気ヘッド主要部９を外部から保護するため
に、基板１０の上に接着剤１４を用いて保護板１９を貼
付ける。このときも当然接着剤１４はボンディングパッ
ド７の方向に流れ出すが、ボンディングパッド７は前述
のとおり硬化したマスキング材１３により覆われている
ため、ボンディングパッド７が接着剤１４によって汚染
されることがない。Figures 2a-f show other examples in which the wire bonding method according to the present invention is used in the assembly process of a thin-film magnetic head.
This will be explained with reference to. FIG. 2a shows a multi-track thin film magnetic head substrate in which a multi-track magnetic head has been formed on the substrate, where 10 is the magnetic head substrate, 9 is the main part of the magnetic head, and 7 is the main part 9 of the magnetic head. External circuit (
This is a bonding pad that is used to perform wire bonding for electrically connecting a device (not shown). Next, FIG. 2 shows a state in which a liquid sol-like masking material 13 is applied to the bonding pad 7 in order to prevent the bonding pad from being contaminated by adhesive in subsequent steps. After the masking material 13 is applied, it is cured by ultraviolet rays or heat rays, and the shape of the masking material does not change at this time. Next, as shown in FIG. 2C, as a preliminary step for electrically connecting the main part 9 of the magnetic head to an external circuit (not shown), a flexible printed board 12 is attached to the magnetic head substrate 10 using an adhesive 11. and glue. At this time, the adhesive 11 naturally flows toward the bonding pad 7, but since the bonding pad 7 is covered with the hardened masking material 13 as described above, the adhesive 11 flows toward the bonding pad 7.
It cannot be contaminated by 1. Next, as shown in FIG. 2d, 1. In order to protect the main part 9 of the magnetic head from the outside, a protective plate 19 is pasted onto the substrate 10 using an adhesive 14. At this time, the adhesive 14 naturally flows out in the direction of the bonding pad 7, but since the bonding pad 7 is covered with the hardened masking material 13 as described above, the bonding pad 7 is not contaminated by the adhesive 14. .

次に第２図ｅに示すとおリボンディングパッド７を覆っ
てしたマスキング材１３を物理的な引き剥し又は化学的
な粘着性低下なものに変質させてはがすことにより、ワ
イヤボンディングをおこなうに必要十分な表面清浄度を
もったボンディングパッド７が露出する。最後に第２図
ｆに示すように磁気ヘッド基板１０側のボンディングパ
ッド７とフレシキブルプリント板１２側のボンディング
パッド８をワイヤボンディングで結線することにより磁
気ヘッド１０とフレキシブルプリント板１２の電気的接
続が完了する。このとき、ボンディングパッド７が前述
のとおり清浄であるので十分なボンディング強度が得ら
れる。Next, as shown in FIG. 2e, the masking material 13 covering the bonding pad 7 is physically peeled off or chemically changed into a material with reduced adhesiveness and then peeled off to remove the masking material 13 necessary for wire bonding. The bonding pad 7 with a high surface cleanliness is exposed. Finally, as shown in FIG. 2f, the electrical connection between the magnetic head 10 and the flexible printed board 12 is established by connecting the bonding pad 7 on the magnetic head substrate 10 side and the bonding pad 8 on the flexible printed board 12 side by wire bonding. Complete. At this time, since the bonding pad 7 is clean as described above, sufficient bonding strength can be obtained.

光１Ｆと塾呈− 以上説明したように本発明は、金属細線を超音波ないし
は熱圧着によりワイヤボンディングするための、基板上
のボンディングパッドをあらかじめゾル状ＵＶ硬化樹脂
系のマスキング材により覆い、そののちマスキング材を
紫外線や熱線の照射により硬化させ、しかるのちに、′
ボンディングパッド周辺の部品の半田付けないしは接着
割付は等の固着取付けを行い、そののちマスキング剤を
物理的又は化学的に処理して剥離して清浄な表面を有す
るボンディングパッドを露出させ、露出したボンディン
グパッドにワイヤボンディングすることにより、部品と
ボンディングパッドの距離を従来品に比べはるかに近接
させることができる。したがって上記のようにして得ら
れる基板を有する機器の小型化−高密度化をはかること
が可能となる効果がある。Hikari 1F and School Presentation - As explained above, the present invention is for wire bonding thin metal wires by ultrasonic or thermocompression bonding, and the bonding pads on the substrate are covered in advance with a sol-like UV curing resin masking material. The masking material is then cured by irradiation with ultraviolet rays or heat rays, and then
The components around the bonding pad are fixedly attached by soldering or adhesive allocation, and then the masking agent is physically or chemically treated and peeled off to expose the bonding pad with a clean surface. By wire bonding to the pad, the distance between the component and the bonding pad can be made much closer than in conventional products. Therefore, it is possible to reduce the size and increase the density of devices having the substrate obtained as described above.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａ　−ｅは、本発明のワイヤボンディング方法を
混成ＩＣの組立に応用した実施例の説明図であり、図ａ
−ｅは工程の進度順にかかれている。 第２図ａ−ｆは本発明のワイヤボンディング方法を多ト
ラツク薄膜磁気ヘッドの組立に応用した実施例の説明図
であって、図ａ−ｆは各々工程の進度に従ってかかれて
いる。 １・・・ボンディングパッド、２・・・半田付ランド、
３・・・半導体ペレットマウントランド、４・・・マス
キング材、５・・・半田、６・・・チップ部品、７・・
・ボンディングパッド、８・・・ボンディングパッド、
９・・・磁気ヘッド主要部、１０・・・磁気ヘッド基板
、１１・・・接着剤、１２・・・フレシキブルプリント
板、 １３・・・マスキング材、１４・・・接着剤、１５・・
・ボンディングワイヤ、 １６・・・混成ＩＣ基板、 １７・・・ボンディングワイヤ、 １８・・・半導体ペレット、１９・・・保護板。 １２−・・７レヤ／７゛ＩＶ 丁リントわしFigures 1a to 1e are explanatory diagrams of an embodiment in which the wire bonding method of the present invention is applied to the assembly of a hybrid IC;
-e is written in order of progress of the process. FIGS. 2a to 2f are explanatory diagrams of an embodiment in which the wire bonding method of the present invention is applied to the assembly of a multi-track thin film magnetic head, and the figures a to f are drawn according to the progress of each process. 1... Bonding pad, 2... Soldering land,
3... Semiconductor pellet mounting land, 4... Masking material, 5... Solder, 6... Chip parts, 7...
・Bonding pad, 8... Bonding pad,
9... Main part of magnetic head, 10... Magnetic head substrate, 11... Adhesive, 12... Flexible printed board, 13... Masking material, 14... Adhesive, 15...
- Bonding wire, 16... Hybrid IC board, 17... Bonding wire, 18... Semiconductor pellet, 19... Protective plate. 12-...7 layer/7゛IV Ding lint eagle

Claims (1)

【特許請求の範囲】[Claims] 　金属細線を用いたワイヤボンディングのための基板上
のボンディングパッドを、予めゾル状マスキング材によ
り覆って後、上記マスキング材を硬化させ、そののちボ
ンディングパッド周辺の部品の固着取付けをおこない、
しかる後にマスキング材を物理的又は化学的に処理して
剥離して清浄なボンディングパッドを露出させ、露出し
たボンディングパッドにワイヤボンディングすることを
特徴とするワイヤボンディング方法。A bonding pad on a substrate for wire bonding using a thin metal wire is covered in advance with a sol-like masking material, the masking material is cured, and then parts around the bonding pad are fixedly attached,
A wire bonding method characterized in that the masking material is then physically or chemically treated to peel off to expose a clean bonding pad, and wire bonding is performed to the exposed bonding pad.
JP63106997A 1988-04-28 1988-04-28 Wire bonding process Pending JPH01278032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63106997A JPH01278032A (en) 1988-04-28 1988-04-28 Wire bonding process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63106997A JPH01278032A (en) 1988-04-28 1988-04-28 Wire bonding process

Publications (1)

Publication Number Publication Date
JPH01278032A true JPH01278032A (en) 1989-11-08

Family

ID=14447860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63106997A Pending JPH01278032A (en) 1988-04-28 1988-04-28 Wire bonding process

Country Status (1)

Country Link
JP (1) JPH01278032A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06132626A (en) * 1992-10-21 1994-05-13 Nec Corp Printed circuit board
JP2007201286A (en) * 2006-01-27 2007-08-09 Kyocera Corp Surface mount module manufacturing method and surface mount module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06132626A (en) * 1992-10-21 1994-05-13 Nec Corp Printed circuit board
JP2007201286A (en) * 2006-01-27 2007-08-09 Kyocera Corp Surface mount module manufacturing method and surface mount module

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