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JPH01260856A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01260856A
JPH01260856A JP8932788A JP8932788A JPH01260856A JP H01260856 A JPH01260856 A JP H01260856A JP 8932788 A JP8932788 A JP 8932788A JP 8932788 A JP8932788 A JP 8932788A JP H01260856 A JPH01260856 A JP H01260856A
Authority
JP
Japan
Prior art keywords
phosphorus
boron
doped
gate
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8932788A
Other languages
Japanese (ja)
Inventor
Katsuki Nonaka
野中 功樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP8932788A priority Critical patent/JPH01260856A/en
Publication of JPH01260856A publication Critical patent/JPH01260856A/en
Pending legal-status Critical Current

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Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To suppress the fluctuation of the threshold voltage value of a gate, by adding acceptor impurities such as boron in gate polysilicon, doping phosphorus at the same time, and using movable ions such as alkali metal ions in a gate insulating film as a getter. CONSTITUTION:A polysilicon film 13 which is used as a gate electrode is deposited by a vapor growth method. Boron 13 having the high concentration of 1E15/cm<2>-1E16/cm<2> is doped in the polysilicon film by an ion implanting method. Phosphorus 13'' having the adequate concentration of 5E13/cm<2>-5E14/ cm<2> is doped by an ion implantation method. The boron and the phosphorus are activated 13''' by heat treatment. Since the concentration of the boron is lower than that of the phosphorus, a P<+> polysilicon film whose sheet resistance is sufficiently low is formed. A phosphorus doped P<+> polysilicon film 13''' which has a getter effect for movable ions such as alkali metal ions in a gate insulating film 12 is formed with the phosphorus that is incorporated in the film at the adequate concentration.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は微細化された半導体装置の製造方法に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a miniaturized semiconductor device.

〔発明の概要〕[Summary of the invention]

この発明はP゛ポリシリコンゲート有する半導体装置に
おいて、ゲート電極材料であるポリシリコン膜中に、ボ
ロンなどのアクセプタ不純物に加えリンもドープすると
いうものである。
This invention is a semiconductor device having a P polysilicon gate, in which phosphorus is doped in addition to acceptor impurities such as boron into a polysilicon film that is a gate electrode material.

〔従来の技術〕[Conventional technology]

従来、P゛ポリシリコンゲート形成する場合、ゲート電
極材料であるポリシリコン膜中に、ボロンなどのアクセ
プタ不純物をドープするという方法が行われている。
Conventionally, when forming a P polysilicon gate, a method has been used in which an acceptor impurity such as boron is doped into a polysilicon film that is a gate electrode material.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし従来のP°ボリンリコンゲートの形成方法では、
ゲート絶縁膜中のアルカリ金属イオンなどの可動イオン
をゲッターする作用が無い又は少ないために、ゲートし
きい値電圧が変動するという問題点があった。
However, in the conventional method of forming P° borine recongate,
There is a problem in that the gate threshold voltage fluctuates because there is no or little effect of gettering mobile ions such as alkali metal ions in the gate insulating film.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題を解決するために本発明は、ゲート電極材料で
あるポリシリコン膜中に高濃度にドープされたボロンな
どのアクセプタ不純物を加え、ゲート電極のシート抵抗
に大きな影響を及ぼさない程度の濃度のリンもドープし
た。
In order to solve the above problems, the present invention adds a highly doped acceptor impurity such as boron to the polysilicon film that is the gate electrode material, and has a concentration that does not significantly affect the sheet resistance of the gate electrode. Rin was also doped.

〔作用〕[Effect]

ゲート1i3極中にドープされたリンにより、ゲート絶
縁膜中のアルカリ金属イオンなどの可動イオンがゲッタ
ーされるために、ゲートしきい値電圧の変動を抑制する
ことができる。高濃度にドープされたボロンなどのアク
セプタ不純物と比較して、リンは低濃度にドープされて
いるために、P9ポリシリコンゲート電極の極性やシー
ト抵抗に与える影響は無視することができる。
Since mobile ions such as alkali metal ions in the gate insulating film are gettered by the phosphorus doped into the gate 1i, it is possible to suppress fluctuations in the gate threshold voltage. Since phosphorus is lightly doped compared to heavily doped acceptor impurities such as boron, its effect on the polarity and sheet resistance of the P9 polysilicon gate electrode can be ignored.

〔実施例〕〔Example〕

第1図fat〜telは本発明のリンドープl−P”ポ
リシリコンゲートの形成方法の工程順の概略を表す断面
図である。第1図1dlにおいて11は半導体シリコン
基板、12はゲート絶g膜を表す。第1図(b)におい
て13はゲート電極として用いられるポリシリコン膜が
気相成長法により堆積された様子を表している。第1図
(C1において13′はイオン打込み法によりポリシリ
コン膜中にI E15/aII〜IE16/−の高濃度
のボロンがドープされた様子を表している。第1図1d
lにおいて13′はイオン打込み法により5E13/−
〜5E14/(fflの適度な濃度のリンがドープされ
た様子を表している。第1図1dlにおいて13″は熱
処理によりボロン及びリンが活性化された様子を表して
いる。ボロンに比ベリンは低濃度であるために、シート
抵抗が十分に低いP゛ポリシリコン膜形成されている。
FIG. 1 fat to tel are cross-sectional views schematically showing the process order of the method for forming a phosphorus-doped l-P" polysilicon gate of the present invention. In FIG. In FIG. 1(b), 13 represents a state in which a polysilicon film used as a gate electrode is deposited by vapor phase growth. In FIG. This shows that the film is doped with boron at a high concentration of IE15/aII to IE16/-. Figure 1 1d
In l, 13' is 5E13/- by ion implantation method.
~5E14/(ffl) This shows that phosphorus is doped at an appropriate concentration. In Figure 1 1dl, 13'' shows that boron and phosphorus have been activated by heat treatment. Compared to boron, verine is Since the concentration is low, a P polysilicon film with sufficiently low sheet resistance is formed.

さらに膜中に適度な濃度で含まれるリンにより、ゲート
絶縁膜中のアルカリ金属イオンなどの可動イオンに対し
てはゲッター効果のあるリンドープトP°ポリシリコン
膜が形成されている。この後、通常のフォトリソグラフ
ィ法によりポリシリコン膜をパターニング加工しゲート
電極を形成した。
Further, due to the phosphorus contained in the film at an appropriate concentration, a phosphorus-doped P° polysilicon film is formed that has a getter effect for mobile ions such as alkali metal ions in the gate insulating film. Thereafter, the polysilicon film was patterned using normal photolithography to form a gate electrode.

〔発明の効果〕〔Effect of the invention〕

以上、詳細に説明したように、本発明によるリンドープ
トP9ポリシリコンゲートの形成方法は、微細化された
集積回路において、ゲート絶縁膜中のアルカリ金属イオ
ンなどの可動イオンに対するゲータ−効果を有し、十分
にシートta抗が低いP゛ポリシリコンゲート電極形成
を可能にする優れた特徴を有する。
As described above in detail, the method for forming a phosphorus-doped P9 polysilicon gate according to the present invention has a gator effect on mobile ions such as alkali metal ions in the gate insulating film in a miniaturized integrated circuit, and It has an excellent feature that enables the formation of a P polysilicon gate electrode with a sufficiently low sheet resistance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(al〜te)は本発明のリンドープl−P”ポ
リシリコンゲートの形成方法の工程順の概略を表す断面
図である。 11・・・半導体シリコン基板 12・・・ゲート絶縁膜 13・ ・ ・ポリシリコン膜 13’・・ボロンドープトポリシリコン膜I3“・・ボ
ロン&リンドープトポリシリコン膜13#′・・リンド
ープトP0ポリシリコン膜以上 出願人 セイコー電子工業株式会社 −一一一一一一一一−−−−−−−−−−−−−−一一
一一一一一−−−−−−−−−12”フ′”−ト身と9
F′#R更(a)                 
      ハ11牛鼻体シ1Jコン署可良本光1月の
製造方法の工[F1頁Fr面図第1図
FIG. 1 (al to te) is a cross-sectional view schematically showing the process order of the method for forming a phosphorus-doped l-P'' polysilicon gate of the present invention. 11...Semiconductor silicon substrate 12...Gate insulating film 13・ ・ ・Polysilicon film 13'...Boron-doped polysilicon film I3"...Boron & phosphorus-doped polysilicon film 13#'...Phosphorus-doped P0 polysilicon film and above Applicant: Seiko Electronics Co., Ltd. - 1111 1111---------------111111---12"F'"-To body and 9
F'#R further (a)
HA11 Cow nose body 1J consignment KARA Honko January production method [F1 page Fr side view Figure 1

Claims (1)

【特許請求の範囲】[Claims]  P^+ポリシリコンゲートを有する半導体装置の製造
方法において、ゲートポリシリコン中にボロンなどのア
クセプタ不純物に加えると共にリンもドープすることを
特徴とする半導体装置の製造方法。
A method for manufacturing a semiconductor device having a P^+ polysilicon gate, the method comprising doping phosphorus in addition to an acceptor impurity such as boron into the gate polysilicon.
JP8932788A 1988-04-12 1988-04-12 Manufacture of semiconductor device Pending JPH01260856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8932788A JPH01260856A (en) 1988-04-12 1988-04-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8932788A JPH01260856A (en) 1988-04-12 1988-04-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01260856A true JPH01260856A (en) 1989-10-18

Family

ID=13967578

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8932788A Pending JPH01260856A (en) 1988-04-12 1988-04-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01260856A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02291174A (en) * 1989-04-28 1990-11-30 Nec Corp Manufacture of semiconductor element
US5529940A (en) * 1992-02-03 1996-06-25 Nec Corporation Method of manufacturing a vertical MOSFET having a gate electrode of polycrystalline silicon
US6251712B1 (en) 1995-03-27 2001-06-26 Semiconductor Energy Laboratory Co., Ltd. Method of using phosphorous to getter crystallization catalyst in a p-type device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02291174A (en) * 1989-04-28 1990-11-30 Nec Corp Manufacture of semiconductor element
US5529940A (en) * 1992-02-03 1996-06-25 Nec Corporation Method of manufacturing a vertical MOSFET having a gate electrode of polycrystalline silicon
US6251712B1 (en) 1995-03-27 2001-06-26 Semiconductor Energy Laboratory Co., Ltd. Method of using phosphorous to getter crystallization catalyst in a p-type device
US6518102B1 (en) * 1995-03-27 2003-02-11 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing transistor semiconductor devices with step of annealing to getter metal with phosphorous
US6855580B2 (en) * 1995-03-27 2005-02-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof

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