JPH01256834A - Modem device - Google Patents

Abstract

PURPOSE:To decide optimum transmission speed by one training by providing a mean square error calculation circuit calculating a mean square error during the reception of a prescribed scramble data to an equalizer so as to measure the degree of line equalization. CONSTITUTION:The number of times of accumulation N is set to '8' and '48' by using the CCITT modem recommendations V27ter segment 5 and V29 segment 4. In case of using a V29 modem at first an error rate versus S/N curve of the V29 modem is plotted to obtain the S/n with respect to the user allowable error rate and it is referred to as a threshold level TH. Thus, in the actual facsimile communication, when the value QL is smaller than the TH, 9600bps as the optimum transmission speed is adopted and when larger, 7200bps is selected as the optimum transmission speed. Thus, one training is enough to determine the optimum transmission speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a modem device, and relates to a modem device used, for example, in digital data communication such as GIII facsimile communication.

[Prior Art] When transmitting digital signal data via a general public line that is an analog line, it is necessary to modulate the digital signal and convert it into a desired analog signal before transmitting it. Furthermore, it is necessary to demodulate this modulated signal on the receiving side, and a modulation/demodulation device (modem device) for this purpose is essential.

The transmission speed during data transmission has also been increased, and currently GM facsimile machines have an information transmission speed of 9.
A type that transmits data at a high speed of 600 bps (bit/sec) is used.

Therefore, the transmission signal modulated by the transmitting modem device and sent out to the line is received by the receiving modem device with distortion added due to line distortion, jitter, timing error between transmission and reception, carrier error, etc. The receiving modem device is equipped with an equalizer or the like to correct this distortion, and the signal is corrected so that it becomes the original transmission signal when it is output from the receiving modem device.

The operation of this equalizer will be explained below with reference to FIG. 6 and FIGS. 7(A) to 7(C).

In FIG. 6, 10 is a transmitting modem device, 20 is a receiving modem device, 21 is an equalizer built in the receiving modem device 20, and 30 is a line connecting both modem devices.

The transmission signal ak output from the transmission modem M10 is
As shown in FIG. 7(A), the signal is sent to the line 30 with a uniform gain over the entire band used. However, the line 30 has frequency characteristics, and its transmission characteristics are, for example, the characteristics shown in FIG. 7(B). Therefore, the received signal Rk received by the receiving modem device 20 is affected by this transmission characteristic, and becomes as shown in FIG. 7(B). By equipping the receiving side modem device 20 with an equalizer 21 having the frequency characteristics shown in FIG. 7(C), the output signal akR from the equalizer 21 has the frequency characteristics shown in FIG. ) is a composite property. The image frequency characteristics are opposite to each other, and the characteristic of the output signal akR [the characteristic obtained by convolving both characteristics (simple multiplication in the frequency domain)] is the flat characteristic shown in Fig. 7 (A). . As a result, distortion-free signal transmission is possible.

That is, the role of the equalizer 21 is to extract the inverse characteristics of the line characteristics.

In the method described above, line characteristics are equalized in data communications using public telephone lines, such as facsimile communications.

The table below shows CCITT as a training pattern for the equalizer.
, V29 Recommendation, and with reference to this table, C
The fallback will be explained using the CITT V29 recommendation as an example.

In the table, segment 2 is a pattern for timing phase adjustment, and segment 3 is a pattern for equalizer adjustment.

The table shows synchronization signals recommended by V29, which are used to equalize line characteristics before transmitting and receiving facsimile image data. Following the synchronization signal, a continuous "0" signal for 1.5 seconds ±10%, called TCP (Training Check), is sent to confirm whether the line characteristics have been properly equalized.

Therefore, first, the transmitter side sends out a synchronization signal having a transmission rate of 9600 bps, and then sends out T C' F.

On the receiver side, AGC control, timing extraction, and equalizer adjustment are performed while receiving the synchronization signal.

Next, during the TCP period, for example, check if there are any errors for 1 second, and if there is an error, send an FTT D to the transmitter side.
laning failure) and falls back to 7200 bps. Also, if there is no error, a CFR (receipt confirmation signal) is sent to the transmitter and 9600 b is sent without fallback.
Image data is sent and received using ps.

[Problems to be Solved by the Invention] However, in the above conventional example, an extra step is involved because a fallback is performed every time a TCP error occurs, and a modem with a high transmission speed is not used. However, the disadvantage is that the preparatory steps for transmitting and receiving image data take a lot of time, and the effective transmission speed becomes extremely low.

Therefore, if the transmission path characteristics are poor, V29 modem (9
600bps, 7200bps) than when using V27ter modem (4800bps).

2400 bps), the effective transmission speed may be faster.

From now on, 12.0Kbps, 14.4Kbps.

It is expected that a high-speed modem with a transmission speed of 19.2 Kbps will be recommended, but if a conventional fallback mode is used in a high-speed modem, the effective transmission efficiency will be worse than before. Become.

[Means for Solving the Problems] The present invention has been made for the purpose of solving the above-mentioned problems, and includes the following configuration as a means for solving the above-mentioned problems.

That is, the equalizer includes a mean square error calculation circuit that calculates the mean square error while receiving predetermined scrambled data.

Further, it is desirable to add a square error calculation circuit and an IDF filter to the output of the equalizer determination section as the mean square error calculation circuit.

Furthermore, it is desirable to add an absolute value error or a squared error and a low-pass filter to the output of the equalizer determination section.

[By providing a mean square error calculation circuit with a function greater than 1, it is possible to measure the degree of line equalization and determine the optimum transmission rate with one training session.

That is, in order to solve the above problem, a squared error calculation circuit is installed on the output side of the equalizer judgment section on the receiver side.1. D.

F (Integrate and Dump File
By adding a comparator and a comparator, it is possible to calculate the equalization rate during the period of scrambled data "1" for CCITT recommended synchronization, and select the optimum transmission rate based on the result. be.

[Example] Hereinafter, an example according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a modulation/demodulation device (modem) according to an embodiment of the present invention.
This is a block diagram of the DSP.
(digital signal processing processor).

In FIG. 1, 100 and 118 are transmitting terminals and receiving terminals that are connected to the modem of this embodiment and generate digital signals to be transmitted.

101 is a scrambler that randomizes transmission data in order to prevent continuous output of the same data; 102 is an encoder that assigns a code to the signal from the scrambler 101 for each tribit, guibit, etc.; and 103 is a code amount interference of the signal. Waveform shaping filter (roll-off filter) that prevents
4 is a modulator that performs predetermined modulation processing on the signal from the waveform shaping filter 103. The modulation method in this modulator 104 is a quadrature amplitude modulation (QAM) method that changes the amplitude and phase of a carrier wave.

The signal modulated by this modulator 104 is sent out to an analog public line, etc. (it is converted to an analog signal by a D/A converter 105, and is further processed by a low-pass filter 106 to match the transmission band of the transmission path. The harmonic components are removed and sent to the transmission line.

On the other hand, from the transmission signal from the transmission path, components outside the transmission band are first removed by a bandpass filter 110, then controlled by the AGCll to a signal level that can be handled on the receiving side, and then converted into a digital signal by the A/D converter 112. be converted into After being converted into a digital signal, it is demodulated by the demodulator 113 into the original signal before modulation. Here, reference numeral 114 is a fixture, and as described above, distortion components received during transmission are removed from the received signal transmitted here, and the original transmitted signal is extracted. The output signal of this equalizer 114 is sent to a determiner 115, where it is determined to be a code point, and then decoded by a decoder 126 and sent to a descrambler 117.
The signal randomized by the scrambler 101 on the transmitting side is restored to its original state.

In this way, the signal is returned to the same signal as the transmission signal output from the transmitting terminal 100, and is output to the receiving terminal 118 side.

Then, the signal line 120 determines, for example, that the mean square error cumulative value QL (described later) is determined by the judgment result of the comparator 114 (at the end of upper segment 5 or at the end of upper segment 4).
threshold) less than TH, 9600 b
When selecting the ps transmission speed, set H level ()Iig.
h Level) is output, and the squared error cumulative value Q is the threshold T. Thicker than 7200 bp
When selecting the transmission speed of s, select the L level (Low L
evel ). Of course, when the value of the squared error cumulative value QL exceeds TdIv (the divergence value when the equal fixture diverges, calculated in advance by simulation), a signal line is sent to notify that the tap coefficient of the equal fixture is to be saved and to proceed to retraining. It is also possible to add

Since the configuration and control of the portions of the modem device of this embodiment having the above configuration except for the fixture 114 are well known, a detailed explanation thereof will be omitted, and the detailed configuration and operation of the fixture 114 of this embodiment will be sequentially explained below.

FIG. 8 is a configuration diagram of the fixture of this embodiment. The fixture 114 of this embodiment is composed of a transversal filter. In the figure, 400 is a delay element that delays received data Rk for a certain period of time, and 401 is a delay element that delays received data Rk for a certain period of time. This is the tap gain [C-5-CN] multiplied by the delayed received data immediately above in the figure.

As is well known, this tap gain expressed on the time axis is called a unit impulse response, and the result obtained by Fourier transforming this is the frequency characteristic of the fixture shown in FIG. 7(B).

Further, 402 is a multiplier that multiplies the received data delayed by the delay element 400 and the tap gain 401;
403 is an adder that takes the total value of the multiplication result of the received data delayed by the delay element 400 from each multiplier 402 and the tap gain 401;

The equalizer output signal yk with the above configuration can be expressed by the following equation.

The equalizer 201 adapts to the reverse characteristics of the line by sequentially calculating each tap gain using the following formula using the MSE method (Mean Sguare Error method) based on the received data.

γ+1 8(yk-ak)" Ce =Ce -a -=・" (2) 2Ce However, Ce"1=: γ+ Tap gain value calculated for the first time 5k = Judgment (estimated value) Estimation of received data a + c During the training period, fik=ak.

L: Convergence coefficient (generally α(1) Vk-;ak: Error signal (ek).

Note that the above-mentioned MSE method is an algorithm that minimizes the squared error signal 02k.

Particularly in this modem, speed and precision of this equalization operation are required, and it is no exaggeration to say that this itself determines the performance of the modem.

In this way, the equalizer 114 creates the line inverse characteristics using known data (training data) between the transmitter and receiver before data transmission, and then creates the equalizer characteristics in order to follow the gradual time fluctuations of the line. (automatic equalization or adaptive equalization).

FIG. 2 shows an example in which the phase control section on the output side of the equalizer determining section is configured as a PLL automatic equalizer (PLL automatic equalizer with square error accumulator).

In FIG. 2, R+ is a demodulated complex signal, which is supplied from the demodulator of the receiving system. Reference numeral 600 is a line fixture, which restores data distorted on the line to its original transmission state.

jθ1 Here, Y+ = A+ e is the i-th output of the equal fixture 600 expressed in polar coordinates.

603 is a multiplier, −jφ・of the complex number generator 605;
and the output e jθL Equalizer output Yl=e are multiplied together, and -jθl
It is output as j(θ1−φI) Z+ =Y+ e =A+ e. A determiner 610 determines the code point (input i) closest to the received signal point, which is the output of the multiplier 603. A subtracter 611 subtracts the decision point from the received signal point and outputs an error signal E+=Z+-person.

The error signal E, is then multiplied with the output e of the complex number generator jφL 602 to obtain 1, jφ1 Ele , which is fed back to the equalizer 600.

Here, ej$1 is the phase correction amount.

Next, the phase control surrounded by the dotted line in FIG. 6 will be explained.

609 is a divider and enters Z, which division result,
Approximately ・j (0 "1") can be found.

608 is an imaginary part extractor which outputs sin (θ, -φI).

5 inches (θ1-φl) is approximately equal to (θ1-φl) when (θ14φI). 606° and 607 are normal PLL components, VC○ and low-pass filter, which adjust the phase value (-) to cancel the input phase error.
φl) is output.

Subsequently, the complex number generators 605 and 602 and the complex conjugate generator 604 output −j $1 j $i,
The power outputs are input to multipliers 603 and 601, respectively, and cancel out the phase error of the entire system.

The output E+=Z+-person 1 of the subtracter 611 is inputted to an IDF 613, which will be described later, via an absolute value squaring circuit 612. Note that the absolute value square circuit 612 calculates the square of the distance between the received signal point and the determination point. Subsequently, in the IDF 613, the output of the absolute value squaring circuit 612 is accumulated the number of times (N baud periods) set by the designer, and outputted as Qt. If the line equalization rate is good and the amount of line noise is small, QL approaches zero, and conversely, if the line equalization rate is poor and the amount of line noise is large, the value of QL increases.

Next, using Figure 3, I D F (Integrat
e and Dump Filter) 613 will be explained.

In FIG. 3, 700 is an adder, 701 is a delay device, and 702 is a sampler.

First, the output of the absolute value squaring circuit 612 and the output of the delay device 701 in FIG. 2 are added in the adder 700. This operation is repeated every output period of the absolute value squaring circuit 612, that is, every baud period. The sampler 702 samples the output of the adder 700 for each value N determined by the designer, and subsequently initializes the value of the delay device 701.

In other words, this circuit cumulatively adds N outputs of the absolute value squaring circuit 612.

A method of determining the equalization rate using the PLL automatic fixture with automatic error accumulator described above and determining the optimum transmission speed based on the determination result will be described below.

CCITT Modem Recommendation V27ter segment 5 (sequential “1°” scrambled signal 8SI) and V29
Segment 4 (scrambled data “1” 48S
I) and calculate the cumulative number of times N in Figure 3 as “
8”, set to “48”.

The following explanation will be given using the case where a V29 modem is used as an example.

First, the error rate V, S, and S/N ratio curves of the V29 modem are drawn, and the S/N ratio with respect to the user allowable error rate is determined. By receiving the training signal many times, a mean square error cumulative value is determined from the square error cumulative value QL for the determined S/N ratio, and is set as a threshold To.

Therefore, in actual facsimile communication, if the value of QL is smaller than the threshold TH, 9600 bps is selected as the optimum transmission rate, and if it is larger than the threshold To, then 7200 bps is selected as the optimum transmission rate.
Select ps.

As explained above, by using the above method, the optimum transmission rate can be determined with one training session.

Furthermore, by calculating the value at which the equal fixture diverges in advance through simulation and setting that divergence value as T dlV, the tap coefficient of the equal fixture can be saved when the squared error cumulative value QLO value is larger than the divergence value TdlV. However, it is also possible to move on to retraining.

All comparisons between the equalization degree squared error cumulative value QL and each threshold TH, which have been explained so far, are performed by the comparator 614 shown in FIG.

The above method is also applicable to V27 ter modem, 14.4Kbps, 19.2Kbps
There are many transmission speeds for ultra-high-speed modems such as S, but by using the above method, it is possible to select the optimal transmission speed with one training.

Figure 4 shows the V29 modem (transmission speed 9600 bps/”
7200 bps) is a graph of S/N ratio versus pit error rate. In the same figure, the solid line is 9600 of the V29 modem.
It is the pit error rate when transmitting in bps, and the dotted line is the pit error rate when transmitting at 7200 bps of the V29 modem.

Therefore, if you want to build a communication system with an allowable transmission error rate of 10-4, draw a straight line parallel to the horizontal axis passing through the point where the pit error rate is 10-4, as shown in Figure 4. Straight line and V29 modem (transmission speed 9600b
A perpendicular line is drawn on the horizontal axis from the intersection with the solid line representing the pit error rate of ps).

The intersection of the horizontal axis and the perpendicular line is the V29 modem (transmission speed 9600
This means the minimum S/N ratio that can guarantee a bit error rate of 10-4 at a transmission rate of (bps).

In addition, in Figure 4, the V29 modem (transmission speed 960
0 bps), the minimum S/N ratio that can guarantee a bit error rate of 10-4 is 18.2 dB.

The method for calculating the above cumulative mean squared error will be explained in detail below.

In the case of V29, the cumulative number N shown in Figure 3 is "48
” is.

First, a training process is executed in which a synchronization signal (training) according to CCITT Recommendation V29 is sent from the transmitter side device to the receiver side device. For example, if you repeat this action 100 times, each time (for each training process)
Find the squared error cumulative value QL. Therefore, through a series of training processes, QLOI QLII QL21...
- Obtain 1QL99.

Next, using these Q LOI QLll... and QLII, calculate the cumulative mean square error as follows.

Threshold T in the above formula. is defined as the cumulative mean squared error.

Finally, the PLL with automatic error accumulator that has been explained so far
A method of determining the equalization rate using the automatic equalizer and determining the optimum transmission rate based on the determination result will be described below with reference to the flowchart of FIG.

First, in step 1000, a loop counter βC for counting the number of baud cycles of each segment of a synchronization signal is initialized. In the following step 1001, a normal timing extraction algorithm using a baseband or carrier band extraction method is operated. Subsequently, in step 1002, it is checked whether the loop counter βC has reached 127 (the number of symbol intervals of synchronization signal segment 2 of v29 is counted), and if the loop counter I2c has not reached 127, the loop counter βC is checked in step 1003. Increment βC by 1 and step 10
Return to 01.

When the loop counter βC reaches 127, that is, V29
The number of symbol intervals in synchronization signal segment 2 is 127.
Then, the timing extraction algorithm (step 100
When step 1) has been executed 128 times, the process proceeds to step 1004, where the loop counter 12c is reset and initialized again, and in steps 1005 to 1007, the equalizer tap coefficient is adjusted to adaptively follow the line characteristics using the received data. Run the algorithm that updates 384 times.
In other words, in step 1005, the algorithm for updating the equalizer tap coefficient is executed, and in the subsequent step 1006, the loop counter βC becomes 283, and the count of the number of symbol intervals of V29 synchronization signal segment 3 becomes 383.
Check whether it has reached the number of times, and if it is less than that, step 1
At step 007, the loop counter I2C is incremented by one and the process returns to step 1005.

After executing the algorithm for updating the fixture tap coefficients 384 times, the process proceeds to step 1008, where the loop counter f2
c is initialized, and in subsequent steps 1009 to 1013, squared cumulative error accumulation processing is performed 48 times. First step 1
At step 009, scrambled data "1" of V29 synchronization signal segment 4 is received.Subsequently, step 101
0, the square error between the received signal and the signal coordinate point specified by CCITT, V2'9 recommendation is calculated. Furthermore, in step 1011, the squared errors obtained in step 1010 are accumulated by the IDF shown in FIG. Then, in step 1012, the number of symbol intervals of V29 synchronization signal segment 4 is counted, and when steps 1009 to 1011 have been executed 48 times (when loop counter βC = 47), the process proceeds to step 1014, otherwise, step 1013 The process proceeds to step 1009, increments the loop counter βC by one, and returns to step 1009.

In step 1014, the mean square cumulative error, that is, the value obtained by dividing the square cumulative error by the number of symbol intervals of segment 4, 48, is calculated, and a threshold value T
Compare with H to determine the size. The determination result is obtained, the level of the signal line 120 is switched to either high level or low level, and is output to the receiving terminal 118.

[Other Embodiments] In the above embodiments, the squared error was used as a measure of the equalization rate, but the present invention is not limited thereto, and the absolute value of the error between the received signal point and the determination point may be used. However, it can be easily realized.

In the above explanation, the CCITT V29 recommendation was used as an example, but the present invention is not limited to the V29 recommendation.
It can be easily applied to modems that have multiple transmission speeds such as CI TT, V27ter, and V33 recommendations.

In accordance with the V29 recommendation, in the embodiment, the squared error is accumulated 48 times in the symbol interval of segment 4, but the number of times is not limited as long as it is within 48 times.

In the embodiment, an IDF is used as the accumulator circuit, but the accumulator circuit is not limited to this and can be easily implemented using a normal low-pass filter.

Furthermore, in the embodiment described above, a total of 100 squared errors were accumulated as the mean squared error accumulated value, and the average thereof was determined, but the number of samples is not limited to 100.

As explained above, according to the above embodiments, the following effects can be achieved.

The conventional TCP (training) sequential fallback method for determining the transmission transmission rate has been abolished, and a mean square cumulative error calculation unit has been installed at the output of the judgment unit of the equipment, and the synchronization signal is followed by <T
By determining the equalization rate during the CF reception period and comparing it with the threshold TH determined in advance, the optimal transmission rate can be determined with a single synchronization signal, or if the equalization rate is still poor, training can be performed. It is now possible to do it again.

Furthermore, in modems with multiple transmission speeds, the time required for the pre-procedure can be greatly reduced as described above.
It can be a very efficient modem device.

Along with this, the effective transmission speed has been significantly increased to 12.0Kbps, which is scheduled to be used in the future.

Even if 14, 4 Kbps, and 19.2 Kbps ultra-high-speed modems are standardized and the number of transmission speeds increases from 4 to 37, if equalization processing is performed using the method of this embodiment, the transmission efficiency will be dramatically improved. .

Furthermore, although this embodiment has been explained on the assumption that a DSP is used, the algorithm is not limited to this, and the algorithm is the same even if it is created using hardware. The effect remains the same.

[Effects of the Invention] As explained above, according to the present invention, equalization processing can be performed reliably in a very short time.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment according to the present invention, Fig. 2 is a schematic diagram of equalization operation by the equipment of this embodiment, Fig. 3 is a configuration diagram of the IDF of this embodiment, and Fig. 4 is a diagram of the present invention. A diagram for explaining the S/N ratio versus pit error rate in this embodiment, FIG. 5 is a flowchart showing equalization processing in this embodiment, and FIG. 6 is a diagram for explaining the flow of a general transmission signal. , Fig. 7(A) is a diagram showing the frequency characteristics in the line, Fig. 7(B) is a diagram showing the frequency characteristics in the fixture, and Fig. 7(C) is the diagram showing the frequency characteristics and frequency characteristics of the transmission signal from the transmitting modem. FIG. 8 is a diagram showing the frequency characteristics of the output signal corrected by the fixture. FIG. 8 is a diagram showing the configuration of the fixture of this embodiment. In the figure, 100... Transmission terminal, 101... Scrambler, 102... Encoder, 103... Pulse shaping filter, 104... Modulator, 105... D/A converter, 106 ...Low pass filter, 110...Band pass filter, 111...AGC, 11'2...A
/D converter, 113... demodulator, 114... fixture, 115... determiner, 116... decoder, 117...
... Descrambler, 118 ... Receiving terminal, 400
...Delay element, 401...Tap gain, 402.
. . . Multiplier, 403 . . . Adder. Figure 7 (A)

Claims (3)

[Claims] (1) The equalizer is equipped with a mean square error calculation circuit that calculates the mean square error while receiving predetermined scrambled data,
A modem device characterized in that the degree of line equalization is measured using the circuit, and the optimum transmission speed can be determined with one training. (2) The modem device according to claim 1, wherein a square error calculation circuit and an IDF filter are attached to the output of the equalizer determination section as the mean square error calculation circuit. (3) Claim 2, characterized in that an absolute value error or a squared error and a low-pass filter are added to the output of the equalizer determination section.
Modem equipment as described in section.