JPH01255922A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To decrease the load on software and to realize high speed processing of a data processing system by accumulating parallel data converted by a shift register into a first-in first-out buffer and collectively reading them. CONSTITUTION:Serial data are converted to parallel data by a shift-register 2 and stored into a first-in first-out buffer 3. The number of the parallel data stored into a register 4 is set beforehand, when it arrives at the set number, a comparator 5 generates an interruption signal to a CPU 6. When the value of the parallel data is equal to the value set to a comparing value register 9, a signal is supplied from a comparator 10 to the CPU 6. The parallel data stored in the CPU 6 is read out to a data bus 7 and processed. Thus, the load of the software is decreased and the high speed of the data processing can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application J This invention relates to a semiconductor integrated circuit that processes input serial data.

[Prior Art J] FIG. 7 is a block diagram schematically showing a semiconductor integrated circuit shown in, for example, a user's manual for a signal processor μPD7720 manufactured by NEC Corporation. In the figure,
(1) is a serial data input terminal into which serial data (S) is input, (2) is a shift register that converts serial data to parallel data (FD), (33) is a parallel booter storage input register, ( 34) is this input register (33) A flag register indicating that K parallel data has been stored, (6) is c P U ,
(7) is a data bus, (8) is a storage device, and (11) is the entire semiconductor integrated circuit.

Next, the operation will be explained. Input data to be subjected to data processing is input as serial data to a shift register (2) via a serial data input terminal (1). The shift register (2) sequentially shifts one bit each time data is input, and when a pre-specified number of bits (k bits) of serial data is input, it shifts the serial data of k bits long. 1 word paworeμte°
- Output to the input register (33) as an output. When the K parallel data is stored in the input register (33), a signal (STR) indicating this is input to the flag register (34), and the flag register (34) becomes set. c.
p U (6) monitors all of the flag registers (34) and changes depending on the set state of the flag registers (34).
It is detected that parallel data is stored in the input register (33). Then, the CPU (6) reads out the parallel data stored in the input register (33) through the data bus (7) and performs data processing.

In the above configuration, it is not possible to store multiple parallel data in the input register (33), so the CPU (6) will not be able to store the input register (33) until the next parallel data is input.
33) and processes the stored parallel data.

In addition, the flag register (34) in Fig. 7 is configured with an interrupt circuit, and the parallel data is input to the input register (33).
There is also a semiconductor integrated circuit that generates an interrupt to the CPU (6) every time data is stored in the CPU (6).

Next, with conventional semiconductor integrated circuits, multiple pieces of parallel data (
The operation when performing frame processing, etc. that are used simultaneously will be explained step by step with reference to the flowchart in FIG.

(2) Step (22) First, in the semiconductor integrated circuit (11), the number n of puff relative days required for data processing is specified by a program stored in the built-in storage device or a program read from an external device.

(2) Step (23) The CPU (6) monitors the 7Wog register (34) and waits for data to be input. When a pre-specified number of bits (k bits) of serial data is input, the shift register (2) converts the serial data of each bit into parallel data in which each bit is one word, and transfers the data to the input register (2). 33).

(2) Step (24) When the parallel data is stored in the input register (33), the flag register (34) becomes set. CPU
When (6) detects the set state of the flag register (34), it interrupts the process being executed and moves to interrupt processing.

■Step (25) The CPU (6) transfers data from the input register (33) to the storage device (8). Then, after data transfer, the next parallel data is input to the input register (
33) After completing the data transfer by the time 2 is input,
Resume the interrupted process.

(2) Step (26) After completing step (25), if the number of input parallel data is less than n, the process returns to step (23) and waits for the next parallel data to be input.

The CPU (6) performs steps from step (23) to step (
The operations up to step 26) are repeated until the input processing of n pieces of parallel data is completed.

After the input processing of n pieces of parallel data is completed, the process proceeds to the next step (27).

■Step (27) Perform data processing using n pieces of parallel data at the same time,
One cycle of data processing shown in the flowchart of FIG. 4 is completed.

FIG. 6 shows the operation of the CPU (6) when one cycle of data processing from step (1) to step (2) shown in the flowchart of FIG. 4 is repeatedly performed for a plurality of cycles.

In FIG. 6, (28) is data processing, (29) is an interrupt, (32) is data reading and determination of the number of data, (
31) is a return from interrupt processing.

[Problem to be solved by the invention]

Conventional semiconductor integrated circuits are configured as described above, so that the parallel data stored in the input register must be read before the next bit of serial data is input and converted to l-word parallel data. The data must then be transferred to a storage device.

In the case of frame processing in units of n words, it is only necessary to read out the necessary υ pieces of parallel data after they have all been collected, and an interrupt is generated each time each parallel data is input during execution. There is no need to interrupt processing and transmit data. However, when using a conventional semiconductor integrated circuit, as shown in Figure 6, which shows the operation of a CPU using a conventional semiconductor integrated circuit, an interrupt (29) is generated every time new parallel data is input. It is necessary to interrupt the processing and determine whether the required number of data transfer and parallel data has been obtained (32). This processing has the problem of not being able to speed up the data processing system and increasing the load on the software.

The present invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor integrated circuit that reduces the software load and realizes a faster data processing system.

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention has a first-in first-out buffer that stores an arbitrary number of parallel data converted from serial data by a shift register. Further, the semiconductor integrated circuit according to claim 1 includes a rewritable register that stores the number of interrupt generation words, and a set value of the register and the number of parallel data stored in a separate first-in first-out buffer. A comparator is provided which compares the number of parallel data and provides an interrupt signal to an external or built-in CPU when the number of parallel data becomes equal to or larger than the set value of the register. Further, in the semiconductor integrated circuit according to claim 3, a rewritable register that stores the number of transfer start words, and a set value of the register and the number of parallel data stored in the first-in-first-out buffer are provided. and a comparator that provides a direct memory access request signal to an external or built-in direct memory access control circuit when the number of parallel data is equal to or larger than the set value of the register. .

[Operation J] The comparator in this invention compares the number of parallel data stored in the first-in first-out buffer with the set value of the register, and when the number exceeds the set value, the CPU Multiple parallel data frames can be processed simultaneously by requesting an interrupt to the controller or directly requesting memory access to the direct memory access control circuit.

[Embodiment] An embodiment of the present invention will be described below in Fig. 1.
1 is a configuration diagram schematically showing an embodiment of the semiconductor integrated circuit described in 1.

In the figure, (1) is a serial data input terminal into which serial data (Sl) is input, (2) is a shift register that converts serial data into parallel data (PD),
(3) is a first-in-first-out buffer that stores multiple pieces of parallel data in input order; (4) is a rewritable register that stores the number of interrupt generation words; (5)
is the number of parallel data stored in the first-in first-out buffer (3) and the register (4)
The number of parallel data is compared with the setting value of register (4).
) is equal to or larger than the set value of CPU
(6) is a comparator that provides an interrupt signal to (6), (6) is cPU, (7) is a data bus, (8) is a storage device, and (9) is a comparison device where the value of parallel data for comparison is set. The value register (lO) compares the value of the parallel data (pD) converted by the shift register (2) and the setting value of the comparison value register (9), and when they are equal, the CPU (
6), and (11) is the entire semiconductor integrated circuit.

Next, the operation will be explained. First, in a program written in the built-in storage device or a program read externally, the number of Puffle/I/data that generates an interrupt is specified, and the value n is set in the register (4).

The above Mry can specify a value up to the upper limit number [n] that can be stored in the first-in first-out buffer (3) K. Serial data input to the semiconductor integrated circuit (11) is converted into parallel data with a predetermined bit length of l words in the shift register (2), and then sent to the first-in-first-out buffer (3).
). First-in-first-out buffer (3) C. Can store multiple pieces of parallel data up to m (an integer greater than or equal to 1), and the number of stored parallel data (1 (0≦i6m)) can be stored in the comparator ( 5) will be informed. Comparator (5) compares the number i and the set value υ,
When the number 1 becomes equal to the set value n or becomes larger, CP
Give an interrupt signal (INT) to t7(6)K. C
When the P U (6) receives the interrupt signal (INT), it reads the parallel data stored in the first-in-first-out buffer (3) to the data path (7) and performs data processing.

In addition, the parallel/S converted in the shift register (2)
The value of /7'' is sent to the comparator (10) and compared with the value set in the comparison value register (9).If the two values are equal, the comparator (10) is CPU
Give a signal (MATCR) to (6). For example, parallel data is stored in a first-in first-out buffer (3
), the value of the parallel data determined as the point at which data input is to be terminated is set in the comparison value register (9). When parallel data of a value equal to the set value is input, the comparator (1O) gives a signal (MATCH) to the CPU (6), thereby informing the CPU (6) of termination of data input.

Ratio If! The register (9) may have a configuration in which the set value is fixed, or may have a configuration in which the set value can be rewritten by a program.

Next, FIG. 2 shows a schematic configuration diagram of an embodiment of the semiconductor integrated circuit according to claim 3.

In the figure, (1) is a serial data input terminal into which serial data (sl) is input, and (2) is a serial data input terminal.
(3) is a first-in-first-out buffer that stores a plurality of parallel data in input order; (4) is a rewritable register that stores the number of words in which an interrupt has occurred; (5
) is the number of parallel data stored in the first-in first-out buffer (3) and the register (4).
), and when the number of parallel data is equal to or larger than the set value of the register (4), a direct memory access request signal (DRQ) is provided to the direct memory access control circuit (12). (9) is a comparison value register in which the value of parallel data for comparison is set;
10) compares the parallel data (pD) converted by the shift register (2) with the set value of the comparison value register (9), and when they are equal, direct memory access control circuit (12)
(13) is an example in which the entire semiconductor integrated circuit of the present invention includes a direct memory access control circuit (12), (14) is a processor, (15) is an external path, and (16) is a It is a storage device.

The operation will be explained. A first-in, first-out buffer (3) that is used by a program written to the internal storage device or a program read externally.
Puffre/+L to start transfer from to storage device (16)
15' - The number n of evenings is specified, and the register (4
) is set. The number n can specify a value up to the upper limit number m that can be stored in the first-in first-out buffer (3). Serial data input to the semiconductor integrated circuit (13) is input to the shift register (2) by 1
The words are converted into parallel data with a prespecified pit length and stored in the first-in-first-out buffer (3). first in first)
The out buffer (3) can store a plurality of pieces of parallel data up to m (an integer of 1 or more), and the number i (0≦16m) of stored parallel data is determined by the comparator (
5) will be informed. The comparator (5) compares Equation 1 and set value n, and Equation 1 is the set value, ! ：The built-in direct memory access control circuit (12
) is given a signal (DRQ). Upon receiving the signal (D RQ, ), the direct memory access control circuit (12) sends a hold request signal (HRQ) requesting release of the external bus (15) to the external processor (14). Upon receiving the hold acceptance signal (IiAK) from the processor (14), the direct memory access control circuit (12) transfers the parallel data stored in the first-in first-out buffer (3) to an external path (15). send out,
Parallel data is stored in the storage device (16).

Also, the value of the parallel data converted in the shift register (2) is informed to the comparator (10), and the value of the parallel data converted in the shift register (2) is notified to the comparison value register (
A comparison is made with the value set in 9). If the two values are equal, the comparator (10) provides a signal (MATCH) to the direct memory access control circuit (12).

For example, in order to be able to abort data input before up to n pieces of parallel data are stored in the first-in-first-out buffer (3), set the parallel data value determined as the abort of data input to the comparison value. Register (9
).

When parallel data of a value equal to the set value is input, the comparator (10) can directly give a signal (MATCH) to the memory access control circuit (12) to notify that data input has been terminated. Comparison value register (9
) may have a configuration in which the set value is fixed or a configuration in which the set value can be rewritten by a program.

Next, Section 3 describes the operation when the semiconductor integrated circuit shown in FIG.
Each step will be explained with reference to the flowchart in the figure.

■Step (17) The semiconductor integrated circuit (11) first specifies the number n of parallel data required for data processing by a program written in the built-in storage device or a program read externally, and then executes gX! 1 is given to register (4).

■Step (18) When serial data is input, it is converted into 1 word of parallel data and stored in the first-in-first-out buffer (3rd line).

(2) Step (19) The number 1 of stored parallel data is informed to the comparator (5) and compared with the installed VL controller. If the number 1 of parallel data is smaller than the set value, the comparator (5)
Do not send an interrupt signal (IM'I') to U (6). Then, parallel data storage in step (18) is continued again.

Until n pieces of parallel data are collected, the CPU (6
) can continue data processing without being interrupted by data storage.

■Step (20) When the number 1 of parallel data to be stored becomes equal to the set value n, the comparator (5) gives an interrupt signal (INT).The comparator (6) receives the interrupt signal (INT). takes the first-in first-out buffer (3
) is stored in the data path (7
).

(2) Step (21) The CPU (6) performs data processing using the read n parallel gators.

FIG. 5 shows the operation of the CPU (6) when one cycle of data processing from step (1) to step (2) shown in the flowchart of FIG. 3 is repeatedly performed for a plurality of cycles.

In FIG. 5, (28) is data processing, (29) is an interrupt, (30) is data reading, and (31) is return from interrupt processing. When performing multiple cycles consecutively, as shown in Fig. 5, the CPU is
In (6), data processing of the previous psyche μ can be performed in parallel with data storage without receiving an interrupt.

This invention can be carried out according to the embodiments of the following items (1) to (4).

(1) A logic circuit that converts serial data input from the outside into parallel data, a first-in-first-out buffer that can store multiple pieces of parallel data in the order of input, and a rewritable buffer that stores the number of interrupt generation words. The number of parallel data stored in the register and the first-in first-out buffer is compared with the value of the register, and when the number of parallel data is equal to or larger than the value of the register, an external or a comparator that provides an interrupt signal to a built-in CPU.

(2) The semiconductor integrated circuit according to item 1, wherein a signal is sent to a CPU when the parallel data input to the first-in first-out buffer has a specific value.

(3) A logic circuit that converts serial data input from the outside into parallel data, a first-in-first-out buffer that can store multiple pieces of parallel data in the order of input, and a d-transferable buffer that stores the number of transfer start words. The number of parallel data stored in the register and the first-in first-out buffer is compared with the value of the register, and when the number of parallel data is equal to or larger than the value of the register R11, an external or a comparator that provides a direct memory access request signal to a built-in direct memory access control circuit.

(4) The semiconductor integrated circuit according to item 3, wherein a signal is sent to a direct memory access control circuit when the parallel data input to the first-in first-out buffer has a specific value.

[Effect of the Invention J As described above, according to the present invention, each time serial data is input and converted into one word of parallel data, the CP
There is no need to interrupt the process being executed by U to transfer data. As shown in Figure 5, data can be transferred only after all the data necessary for data processing has been collected, reducing the load on the software and reducing the number of data transfers, increasing the speed of the data processing system. It becomes possible.

Also, since data input can be stopped midway through, it can be used to process any number of data.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an outline of an embodiment of the present invention, and FIG.
3 is a block diagram showing an outline of another embodiment of the present invention, FIG. 3 is a flowchart when processing is performed using n input data simultaneously in the semiconductor integrated circuit of FIG. 1, and FIG.
An explanatory diagram of the CPU operation when performing the processing shown in the figure, Fig. 4 is a flowchart when processing is performed using n input data simultaneously in a conventional semiconductor integrated circuit, and Fig. 6 is a case where the processing shown in Fig. 4 is performed. FIG. 7 is a configuration diagram showing an example of a conventional semiconductor integrated circuit. In the figure, (1) is a serial data input terminal, (2)
is a shift register, (3) is a first-in first-out buffer, (4) is a register, (5) is a comparator,
(9) is the comparison value register (9), (lO) is the comparator, (
12) is a direct memory access control circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts. Dye ip Mi Figure 3 Figure 4 c6 also 6 Mihehehei ~

Claims (2)

[Claims] (1) A logic circuit that converts serial data input from the outside into parallel data, a first-in-first-out buffer that can store multiple pieces of parallel data in the order of input, and a rewritable register that stores the number of interrupt generation words. The number of parallel data stored in the first-in first-out buffer is compared with the value of the register, and when the number of parallel data is equal to or larger than the value of the register, external or internal 1. A semiconductor integrated circuit comprising: a comparator that provides an interrupt signal to a CPU. (2) A logic circuit that converts serial data input from the outside into parallel data, a first-in-first-out buffer that can store multiple pieces of parallel data in the order of input, and a rewritable register that stores the number of transfer start words. The number of parallel data stored in the first-in first-out buffer is compared with the value of the register, and when the number of parallel data is equal to or larger than the value of the register, external or internal and a comparator that provides a direct memory access request signal to a direct memory access control circuit that is configured to perform a direct memory access control circuit.