JPH01248396A - Dynamic random access memory - Google Patents

Abstract

PURPOSE:To easily switch a mode at the time of resetting by setting the sequence of the resetting between a row address strobe signal and a column address strobe signal, and switching the mode. CONSTITUTION:A mode converting circuit 15 is provided which first resets a column address strobe signal the inverse of CAS when both row address strobe signal the inverse of RAS and a column address strobe signal the inverse of CAS are in a low active condition, and changes a signal only when a writing enable signal the inverse of WE is made low for a fixed time from when the row address strobe signal the inverse of RAS is reset. Thus, since a unreliable dummy cycle is unnecessary, and the mode can be switched at the time of the resetting, a single device can have plural types of functions, and the mode can be easily switched.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic random access memory, and more particularly to a dynamic random access memory whose function can be switched among semiconductor memories.

[Conventional technology]

Currently, among semiconductor memories, especially dynamic random access memories (hereinafter referred to as DRAM), page mode (page mode) is used as a function to increase speed.
Page Mode), NBL Mode (Nibb
mode) or static column mode (S
tatic column mode). However, these functions cannot be performed simultaneously in the same device, and they exist as different types. For example, traditional NBL
Switching between a mode device and a page mode device is as shown in FIG.

In FIG. 4, QNIO to QN+3 are N-channel transistors, INV29 to INV32 are inverting circuits, and NO5
is a NOR circuit, NA10 to NAl1 are NAND circuits, 1
is a column address strobe (hereinafter referred to as "CAS") system control circuit, 2 is a pull to NBL) system control circuit, 5
EEND is the sense completion signal and the CAS system start signal.
MSI.2 indicates a cut or fuse by mask slicing (hereinafter referred to as "MS".MS2'').

In this conventional example, if the MSI/MS2 part is in the connected state, when the CAS system becomes active, the CAS
Contacts a and b are clamped to a low potential by system active signal CAS1. As a result, even if the CAS- signal goes into the reset state, the CAS system is not reset, and the NBL
Only the system is reset from 1 to NBL in synchronization with the CAS signal.
Only the system works. That is, the circuit shown in FIG.
Operates in L mode. Furthermore, if MSI and MS2 are in the disconnected state, the CAS system active signal CAS2 causes no change to contacts a and b, and the CAS system operates in synchronization with the CAS signal.

In other words, page mode operation becomes possible.

In this way, two functions were switched depending on whether or not the MSI and MS2 were connected. Here CA
S-system active signal CASI and sense completion signal 5EE
The latch circuit using ND is CA in standby state.
This is to cut the current consumption at the first stage of the S signal.

[Problem to be solved by the invention]

As mentioned above, conventional switching of functions is done by hardware, such as by slicing the contacts MSI and MS2 into mask slices in a post-diffusion process, or by providing a fuse and cutting it with a mask saver or the like. was. Therefore, there is a drawback that switching after assembly is impossible.

In contrast to the conventional function switching method described above, which is based on hardware, the present invention starts with the active state of both the RAS signal and the σT double signal (resetting the TS- signal, that is, setting it in the high state), and then switches the RAS signal to the high state. From reset 1 to The difference is that mote switching can be done easily.

[Means to solve the problem]

The dynamic random access memory of the present invention is
In dynamic random access memory,
After the row address strobe signal and the column address strobe signal are activated at low level, when one of the two strobe signals is reset, the device is activated depending on the state of the other clock signal. The system is equipped with a determination circuit for switching the functions of the system.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of one embodiment of the present invention.
The figure is a time chart of the circuit of FIG.

First, the present invention will be explained in detail with reference to FIGS. 1 and 2. In this embodiment, the determination circuits for switching the functions of the device include a CAS advance reset determination circuit 5 circuit 11, a CAS advance reset WE determination circuit control circuit 12, and a CAS advance reset WE determination circuit 13. , a mode conversion circuit control circuit 14 , and a mode conversion circuit 15 .

In FIG. 1, numeral 11 is a row address strobe, and CAS is a column address strobe, which are external input signals. INVI~INV24 is an inverting circuit, NAI~
NA7 is a NAND circuit, NOI to NO3 are NOR circuits, DE1 to DE2 are delay circuits, Q
p l” Q p3 is P channel transistor, QNI
~QN3 is an N-channel transistor.

The operation of the present invention is to reset the CAS signal before the RAS signal after both the RAS signal and the V-signal are in the active state at low level, and then keep the signal low for a certain period of time T from the time the RAS signal is reset. By doing so, it is possible to convert the mode.

That is, as seen in conjunction with FIG. 2, when the CAS signal is first reset and then the RAS signal is reset by the CAS advance reset determination circuit 11, the signal A1 changes from high to low, and the CAS advance reset determination circuit 11 changes the signal A1 from high to low. Reset WE
The determination circuit control circuit 12 is activated, and the signal B1 changes from high to low. The CAS pre-reset WE determination circuit 13 is enabled, and if the T[ signal is low at that time, the state is latched by the signal B2 changing from low to high and the signal Y becoming the opposite, and thereby the signal C1 The signal C1 is latched from high to low.The change of the signal C1 from high to low causes the inversion circuit INV1 of the mode conversion circuit control circuit 14 to be latched.
5 to 17, a NAND circuit NA7, and a delay circuit DE1, the signal "" becomes a single pulse from high to low, and the signal D1 becomes a single pulse from low to high.

These signals cause the P channel transistor QPS and the N channel transistor QN3 of the mode conversion circuit 15 to
The transfer becomes conductive, the state of the signal E2 is transmitted to the signal E3, and the output is inverted such that if the mode conversion signal CMODE was high, it becomes low, and if it was low -7, it becomes high.

Next, the signal D1 is passed through the delay circuit DE2, and the delayed signal D2 is delayed and changes from high to low. 1 of the signal becomes conductive, inverting the state of the signal E and latching it.

Here, if the mode conversion signal (hereinafter referred to as CMODE signal) is high, it is equivalent to the state in which MSI/MS2 is conductive in Figure 3, and NBL mode operation is possible, and if the CMODE signal is low, MSI - MS2 becomes equivalent to a non-conducting state, allowing page mote. In this way, the CAS signal is reset before the RAS signal, and the R
If the AS signal is held low for a certain period of time T after the AS signal goes high, mode conversion will occur during the reset period, such as changing from NBL mode to page mode and page mode to NBL mode. This made it possible.

At this time, it is easier to use if the initial state after the power is turned on is set to either NBL mode or page mode, but this can be done in the following manner. For example, when setting the initial state to page mode, the inversion circuit I of the mode conversion circuit 15
The current capacity is increased by comparing NV2O with the inverting circuit INV21 and the loads of the signals E1 and E2 are made the same, and the current capacity is similarly increased by comparing the inverting circuit INV22 with the inverting circuit INV23 and the signals E3 and E4 are made the same. make the load the same. In this way, after the power is turned on, the signal E2 becomes the signal E
1, the signal E4 goes high before the signal E3, and the CMODE signal goes low. The first mode after turning on the power is page mode, and then σn
The signal is reset before the R and AS signals, and then the RAS
When the signal is reset, T [if the signal is low, NBL
mode, and the next time you use the same reset method, it will change to page mode. In addition, here C
Although the AS signal is reset before the RAS signal, this can also be achieved by reversing the order of the signals to be reset.

〔Effect of the invention〕

As explained above, the present invention combines the RAS signal and the CA
The CAS signal is reset from the low active state together with the RAS signal, and for a certain period of time after resetting the R-AS signal, the T By providing a circuit, it is now possible to switch modes at reset, which eliminates the need for an uneasy dummy cycle. This has the effect of allowing one device to have multiple types of functions, while also making it easy to switch modes. There is.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the configuration of an embodiment of the present invention;
1 is a time chart of the circuit shown in FIG. 1, and FIG. 3 is a circuit diagram showing an example of the configuration of a conventional technique. ■...CAS system control circuit, 2...NBL system control circuit, ]-1...CAS advance reset determination circuit, 12...
・CAS advance reset WE judgment circuit control circuit, 13...
- CAS advance reset WE determination circuit, 14... mode conversion circuit control circuit, 15... mode conversion circuit.

Claims (1)

[Claims] In dynamic random access memory,
After the row address strobe signal and the column address strobe signal are activated at low level, when one of the two strobe signals is reset, the device is activated depending on the state of the other clock signal. What is claimed is: 1. A dynamic random access memory comprising a determination circuit for switching functions of a dynamic random access memory.