JPH01245487A - digital processing equipment - Google Patents

Abstract

PURPOSE:To shorten a time required for precharging and to read at high speed by setting the potential of a data line and a common data line to an intermediate potential only by a single precharging operation. CONSTITUTION:During a precharging period, the data lines DO, the inverse of DO to which a memory cell MC is connected are precharged to a source voltage side and the common data lines CD, the inverse CD connected to the data lines DO, the inverse of DO through a column switch are precharged to an earth potential side, thereby, the data lines are connected to the common data lines through the column switch according to the selecting operation of the memory cell MC. Thereby, the selecting operation of the memory cell MC is executed and the potential of the data line and the common data line can be set to the intermediate level according to the capacity ratio thereof only by one precharging operation to attain the high speed in an operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having a semiconductor memory device. This relates to effective technology that can be used for (access memory).

[Conventional technology]

A memory cell in an MO8 static RAM is, for example, a pair of drive MOs whose gates and drains are cross-coupled.
It consists of a static clip-flop circuit consisting of 8FETs and their load elements, and a pair of transmission gate MO8FETs. The memory array includes a plurality of memory cells arranged in a matrix and a plurality of pairs of complementary data lines, and each complementary data line is coupled to an input/output terminal of a corresponding memory cell.

The read signal output from the selected memory cell is
Transmitted via the complementary data line pair, for example, differential MO
It is amplified by a sense amplifier circuit using 8FETs.

By the way, there is a multiplexing device that includes a static RAM in order to multiplex a plurality of digital lines into one digital line and perform high-speed transmission. In these multiplexers, static RAMs are used, for example, as time division switches. At this time, the processing capacity of the multiplexing device depends on the access time of the built-in static RAM. Therefore, one way to increase the speed of such a state-type RAM and improve the processing capacity of a multiplexer is to connect complementary data lines to the power supply voltage Vc.
A half precharge method has been proposed in which the battery is charged to a level approximately 1/2 of c.

Regarding the half precharge method mentioned above, ■ Hitachi first applied for the application, for example, in Japanese Patent Application Laid-Open No. 61-253.
695, Japanese Patent Application Publication No. 62-143289 and Patent Application No. 61-13
There is 5909.

Regarding JP-A-61-253695, non-inverting signal line D
o is precharged to the power supply voltage Vcc level, and the inverted signal line n1 is precharged to the circuit ground potential GND level. Thereafter, by short-circuiting (equalizing) the non-inverted signal line Do and the inverted signal line DO, the respective signal lines were brought to approximately 1/2 Vcc level.

In JP-A-62-143289, the non-inverted signal line DO and the inverted signal line DO are each brought to approximately 1/2 VCC level by a precharge operation similar to that described above.

In Japanese Patent Application No. 61-135909, one complementary data line Do, DO is precharged to the power supply voltage Vcc level, and the other complementary data line DI, DI is precharged to the circuit ground potential GND level. After that, one complementary data line DO, Do and the other complementary data line DI, DI are short-circuited (equalized), and each complementary data line is approximately halved.
It was set to Vcc level. In the case of this precharge method, there is initially a level difference between one set and the other of the two pairs of complementary data lines. However, the non-inverted signal line and the inverted signal line of each complementary data line to which the input/output nodes of the memory cell are coupled are brought to the same level by the equalization.

[Problem to be solved by the invention]

However, JP-A-61-253695 and JP-A-62
In case of pre-charge method like -143289,
Complementary data? The first stage precharge operation of setting mDO1DO to the power supply voltage Vcc and the circuit ground potential, and the complementary data lines DO and D.

A second stage precharge operation of short-circuiting is required. At this time, the complementary data line DO.

If the word line is set to the selected state while a level difference remains in Do, there is a possibility that an undesired erroneous write to the memory cell will occur. It is necessary to perform a word line selection operation. As a result, the word line selection timing is delayed, and the operation is certainly delayed accordingly.

In addition, in the precharging method shown in Japanese Patent Application No. 61-135909, for the complementary data line that is precharged to the ground potential GND, memory cells are selected before the complementary data line reaches approximately 1/2 Vcc level after short-circuiting. Information in memory is easily destroyed. Therefore, with this precharge method as well, it is necessary to provide sufficient equalization time as in the above precharge method. Therefore, static type A
M's operation becomes slow.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, during the precharge period, the data line to which the memory cells are coupled is precharged to the power supply voltage side, and the common data line coupled to the data line via the column switch is precharged to the ground potential side of the circuit. (By this means, the data line and the common data line are coupled via the column switch during the selection operation of the memory cell, so that the potentials of the data line and the common data line can be set to an intermediate potential.

[Effect]

According to the above means, with only one precharge operation, the memory cell selection operation and the potential of the data line and the common data line can be set to an intermediate level according to their capacitance ratio, and the sense is sensed at the operating point of the highest sensitivity. The amplifier amplifies the read signal, resulting in faster operation.

〔Example〕

FIG. 1 shows a static type RA to which this invention is applied.
A plan view of an embodiment of a semiconductor substrate (ICCHIP) on which M is formed is shown. The static type RAM of this embodiment is built into a one-chip type digital processing device, such as a multiplexing device, although it is not particularly limited thereto. Each circuit block constituting this multiplexer is a well-known 0MO8 (
Although not particularly limited, it is formed on one of the semiconductor substrates made of single-crystal silicon using complementary integrated circuit manufacturing technology.

In FIG. 1, a plurality of bonding pads BP are provided in the peripheral area of the semiconductor substrate. These bonding pads BP are coupled to corresponding external terminals via bonding wires or the like.

Some of these bonding pads BP are coupled to corresponding unit circuits of the input/output circuit I10 formed at each end of the semiconductor substrate.

The input/output circuit I10 takes in various input digital signals supplied from external devices and transmits them to corresponding internal circuits of the multiplexing device. Furthermore, various output digital signals output from corresponding internal circuits of the multiplexing device are sent to external devices.

A logic circuit section LC including an arithmetic logic unit and various control units constituting a multiplexing device is formed in many parts of the semiconductor substrate. Static RAM of this embodiment
(SRAM) is formed at a predetermined position surrounded by the logic circuit section LC.

This static type RAM is used as a time division switch, so-called TIME 5WITCH, although it is not particularly limited.

In this example, there are two static type RAMSRAMI.
, SRAM 2 are provided 6. Static RAM
During a period when data is being written to the SRAM1, data written to the static RAM SRAM2 in the previous period is read from the static RAM SRAM2.

Also, in the next period, static RAM SRA
At the same time as data is read from M1, new data is written to static type AM SRAM2.

In this way, the input data write operation and the output data read operation are executed in parallel. The input data is output after its array is converted. The array conversion work is controlled by the logic circuit section LC. As a result, this digital processing device operates as a time switch.

FIG. 2 shows a layout diagram of an embodiment of the static type R, AM shown in FIG.

In FIG. 2, although not particularly limited, static RAM includes two sets of memory arrays M-ARYI and M-A
The basic configuration is RY2. Memory array M-ARY
A row address decoder R is provided between I and M-ARY2.
DCR is placed. In addition, row address decoder RD
Word line drive circuits WDI and WD2 are inserted between CR and memory array M-ARYI and 2. A corresponding sense amplifier 8A, write amplifier WA, and read amplifier RA are arranged below each memory array. Further, a corresponding data buffer DB is arranged below each of these amplifiers. A control circuit CTL and an address manual buffer (not shown) are arranged below the row address decoder RDCR and the word line drive circuits WDI, WD2.

As will be described later, the memory arrays M-ARYI and M-ARY2 have word lines arranged in the horizontal direction in the figure, complementary data lines arranged in the vertical direction, and grids at the intersections of these word lines and complementary data lines. It is composed of memory cells arranged in a shape.

The row address decoder RDCR connects the word lines forming each memory array via the word line and drive circuit.
Alternatively, it is set to a high level selection state. On the other hand, complementary data lines constituting each memory array are coupled to a corresponding write amplifier WA and read amplifier RAK via a corresponding sense amplifier 8A. These write amplifier WA and read amplifier RA are further coupled to a corresponding data buffer DBK.

Static RAM is accessed via an internal bus provided in the multiplexer. This internal bus is n+1
It includes a data bus d□-dn of bits, an address bus AO to Ai of n+1 bits, and a control bus consisting of an enable signal line CB, read/write signal line R/W, etc. Although not particularly limited, a static RAM is activated by an enable signal CE, and its operation mode is specified by a read/write signal hole /W.

These control signals are input to the control circuit CTL of the static RAM. The control circuit CTL forms various timing signals for controlling the internal operations of the static RAM based on these control signals.

i + supplied via address bus A O−A i
The 1-bit address signal is input to an address manual buffer (not shown) of the static RAM. These address signals are held by the address buffer and are sent to the row address decoder RDCR as complementary signals.
transmitted to. The row address decoder RDCR decodes these address signals and sends them to the word line drive circuits WDI,
A designated word line is selected with WD2 in the active state.

On the other hand, lower pins (dO to dm) of the data bus correspond to each complementary data line of memory array M-ARYI. Furthermore, the upper bits dm+1 to dn of the data bus correspond to each complementary data line of the memory array M-ARY2. Each data bus d□-dn is coupled to a corresponding unit circuit of a data buffer DB, and is connected to a corresponding complementary data line of a corresponding memory array through corresponding unit circuits of a read amplifier RA and a write amplifier WA. Ru. Each unit circuit of the data buffer DB has a corresponding data bus d
The input data supplied via □-dn is taken in and transmitted to the corresponding write amplifier WA. Further, output data output from the corresponding read amplifier RA is transmitted to the corresponding data bus dO-dn.

FIG. 3 shows a static type RA to which this invention is applied.
A circuit block diagram of one embodiment of M is shown. In the following figures, MOSFETs whose channel (pack gate) portions are marked with arrows are P-channel type, and are distinguished from N-channel MO8PETs whose channel (pack gate) portions are not marked with arrows.

The MOSFET constituting the memory cell is of an N-channel type and is formed in a P-type well region formed on an N-type semiconductor substrate. A P-channel MO8FET is formed on an N-type semiconductor substrate. N-channel ff1M08FET
The P-type well region as the body gate of the MO8FET is coupled to the ground terminal of the circuit, and the N-type semiconductor substrate as the common body gate of the P-channel MO8FET is coupled to the power supply terminal of the circuit. In addition, the MOSFET that constitutes the memory cell
The structure in which the information is formed in the well region is effective in preventing erroneous inversion of information stored in the memory cell caused by α rays or the like. Each MO8FET is manufactured by the so-called self-line technology using a gate electrode made of polysilicon as a kind of impurity introduction mask.

The memory array M-ARY includes a plurality of memory cells MC1 arranged in a matrix, which is illustrated as a representative example.
It is composed of word lines WO to Wn made of polysilicon layers and complementary data lines DO, no to DI, DI. Each data line constituting one complementary data line, for example Do
and Do form one data line pair.

Each of the memory cells MC has the same configuration as each other,
One specific circuit is shown as a representative memory MO8FET Ql, Q with the gate and drain cross-wired together and the source coupled to the circuit ground.
2, and high resistance (Ll, R2) made of a polysilicon layer provided between the drain of the MO8FET QI, Q2 and the power supply terminal Vcc. A transmission gate (MO8F'ET) is connected between the common connection point of the M08FETs Q1 and Q2 and the complementary data lines Do and DO.
Q3°Q4 are provided. The gates of the transmission gates MO8FETQ3, Q4, etc. of the memory cells arranged in the same row are connected to the corresponding word line WO shown by way of example.
and Wn, etc. in common. In addition, the input/output terminals of memory cells arranged in the same column are connected to a corresponding pair of complementary data (or bit) lines Do
, Do, DI, DI, etc.

In the memory cell, MO8FETs Q,1, Q2 and resistors R1, R2 constitute a kind of flip-flop circuit, but the operating point in the information retention state is quite different from that of a flip-flop circuit in the ordinary sense. That is, in the memory cell MC, in order to reduce power consumption, the resistor R1 maintains the gate voltage of MO8FETQ2 at a voltage slightly higher than its threshold voltage when MO8PETQl is turned off. The resistance value is set to a significantly high value to the extent that it can be used.

Similarly, the resistor R2 is also made to have a high resistance value. In other words, the above resistance 1. R2 is MO8FETQl.

The resistance is made high enough to compensate for the drain leakage current of Q2. The resistors R1 and R2 have enough current supply capability to prevent the information charges stored in the gate capacitor f (not shown) of the MO8FET Q2 from being discharged.

According to this embodiment, although the RAM is manufactured by CMO8-IC technology, the memory cell MC is composed of an N-channel MO8FET and a polysilicon resistance element as described above.

The memory cell and memory array of this embodiment are constructed using a P-channel MO8F'ET instead of the polysilicon resistor element described above.
The size can be made smaller than when using . In other words, if a polysilicon resistor is used, the drive mMO8FE
It can be formed integrally with the gate electrode of TQ1 or Q2, and its size can be reduced. Then, as when using P-channel ~l08FET, drive M
Since it is not necessary to separate it from O8FETQI and Q2 by a relatively large distance, no wasted blank space is generated.

In the figure, word line WO is selected by an output signal formed by a NOR gate circuit G1 forming an X address decoder. This also applies to other word lines Wn.

The X-address decoders described above are composed of mutually similar NOR gate circuits G1.02 and the like.

The input terminals of these NOR gate circuits Gl, 02, etc. are supplied with a predetermined combination of complementary address signals consisting of a plurality of bits indicating the X address among the address signals taken into the latch circuit FF, although this is not particularly limited. Ru. The X address decoder decodes the complementary address signal to select one word line.

A pair of complementary data lines Do, , in the memory array
Do is not particularly limited, but P channel MO8FE
TQI 1, Ql 2 and N-channel MO8FETQ
15 and Ql6 are connected in parallel to common complementary data lines CD and CD through CMOS switches. Each data line CD constitutes a common complementary data line.

CD forms one data line pair. Other illustratively shown complementary data lines D1. In Dt, a CMOS consisting of a P-channel MO8FETQ13°Ql4 and an N-channel MO8FETQ17°Ql8 similar to the above is used.
It is coupled to common complementary data lines CD, CD via a switch. This also applies to other complementary data lines (not shown) via similar CMOS switches to the common complementary data line CD.

Combined on CD.

Among the above CMOS switches, N-channel MO8FE
TQI 5 , Ql 6 and Ql7. The gates of Ql8 are coupled to column selection lines yo and yi, respectively. P-channel MO8FET QI l.

The gates of Ql2, Ql 3 and Ql 4 are supplied with output signals of inverter circuits Nl and N2 which receive signals from the column selection lines YO and Yl.

As described above, the configuration using CMOS switches as column switches enables high-speed read and write operations. For example, by setting the column selection line YO to a high level, complementary data 1sL)0. When DO is in the selected state, in the read operation, the P-channel MO8FETs Qll and Ql2 act as gate-grounded and source input amplification M 08 FET, and the data read from the memory cell to the complementary data lines Do and Do are Signals can be efficiently transmitted to the common complementary data lines CD, CD. Also, in the write operation, N-channel MO8FETQ15 and Ql6 are gate-grounded and the source input is increased! Complementary data lines Do act as MO8FETs and are connected to memory cells that are efficiently selected for the write signal supplied to common complementary data lines CD, CD, and CD.
You can tell Do.

This means that other complementary data II! The same applies to selection operations such as DI and DI.

The column selection line YO is selected by an output signal formed by a NOR gate circuit G4 forming an X address decoder. This also applies to the other column selection lines Y1. The X address decoder is composed of mutually similar NOR gate circuits G4 and G3#. The input terminals of these NOR gate circuits G4.03 and the like are supplied with a predetermined combination of complementary address signals consisting of a plurality of bits indicating the Y address among the address signals taken into the latch circuit FF, although this is not particularly limited. Ru. The X address decoder decodes the complementary address signal to select one column selection line.

For example, if the column selection line YO is set to high level,
The N-channel MO8I'ETQ15 and Q16 and the P-channel MO8FETQ11 and Q12 are turned on by the low level of the output signal of the inverter circuit N1, and the complementary data lines Do and DO are connected to the common complementary data line CD,
Combined on CD.

Although not particularly limited, the latch circuit FF takes in the address signal ADD at the timing when the chip enable signal CE changes from low level to high level.

Although not shown, the X address decoder and the X address decoder start their selection operations when the signal CE is set to a high level.

Complementary data lines DO, Do of the memory array M-ARY
Although not particularly limited, P-channel type precharge MO8FETs Q5 to Q8 are provided at Dl and Dt. A precharge signal PC is commonly supplied to the gates of the MO8FETs Q5 to Q8. The precharge MO8FETs Q5 to Q8 are turned on during the precharge period when the precharge signal PC is set to low level, and the complementary data lines DO, DO and DI,
DI is charged up to a first power supply voltage level, for example a high level such as power supply voltage Vcc.

As described above, the configuration using the P-channel MO8FET as the precharge MO8FET allows the complementary data lines DO, DO
It is also possible to make the levels of Di and Di follow the fluctuations in the power supply voltage as described above. This is useful in preventing deterioration of the operating margin caused by the potential of the complementary data line being maintained above the power supply voltage when the power supply drops.

Although not particularly limited to the common complementary data lines CD and CD, the N-channel type precharge M081;'ET
Q9 and QIO are provided. Above MO8F'ETQ9
A precharge signal PC is commonly supplied to the gates of QIO and QIO. The precharge MO8FETs Q9 and QIO are turned on during the precharge period when the precharge signal PC is set to high level, and the common complementary data lines CD and CD are set to the second power supply voltage level, such as the circuit ground potential GND. Set to low level.

The common complementary data lines CD and CD are directly coupled to the input terminals of a differential sense amplifier, although this is not particularly limited. That is, the common complementary data lines CD, CD are connected to N-channel type differential amplification MO8FETQ19. are respectively coupled to the gates of Q20. These differential MO8FETQ
19, an active load circuit consisting of P-channel MO8FETs Q21 and Q22 in a current mirror configuration is thrown to the drain of Q20. Above differential increase @MO8F
'ETQI 9 and Q20 are provided between their common source and the ground potential point of the circuit, and are activated by 'ETQ24 to an N-channel type power switch MO8 which is turned on by a timing signal 8AC. The amplified output signal of the sense amplifier is transmitted to the CMOS inverter circuit N3. which constitutes the readout circuit. It is output through N4.

Between the output terminal of the sense amplifier, in other words, the input terminal of the inverter circuit N3, and the power supply voltage Vcc, there is a P-channel MO which receives the timing signal SAC.
8FETQ23 is provided. MO8FETQ23 above
When the sense amplifier is rendered inactive by the low level of the timing signal SAC, it becomes an on-state trap and pulls up its output terminal to the power supply voltage Vcc. This causes the inverter circuit N3 to receive the voltage at the output terminal.
This is to prevent the generation of a relatively large through current (DC current) caused by the input voltage being maintained at an intermediate level in the 70-state. Therefore, the MO8FETQ23 can be replaced with a high resistance element for pull-up (Vcc level) or pull-down (circuit ground potential).

Further, the common complementary data lines CD, CD are coupled to the output terminal of the next write circuit.

The write circuit consists of N-channel MO8FETs Q25, Q26 and Q27°Q28 in push-pull configuration, and the complementary write signals WD and W) are cross-connected to the output MO8FETs Q25°Q28 and Q26. Q27
are respectively supplied to form complementary write signals, which are transmitted to the common complementary data lines CD, CD.

Thereby, a write signal is supplied to the selected memory cell through the common complementary data 1ilcD, CD, column switch, and complementary data line, thereby performing a write operation. Note that the complementary write signal W
D and WD are both at low level during non-write operations, and the MO8FETQ25. Q26 and Q2
7. Q28 are both turned off. This K causes the output of the write circuit to be in a high impedance state.

The timing generation circuit TG receives the chip enable signal CE.
In response to the read/write control signal R/W, the precharge signal pc, pc and the sense amplifier operation timing signal SAC are generated.

Next, an example of a read operation in the RAM of this embodiment will be described with reference to the schematic timing diagram shown in FIG.

When chip enable signal CE is at low level.

The timing generation circuit TG sets the precharge signal PC to a low level and sets the precharge signal PC to a 71 high level. The low level of the precharge signal PC turns on the P-channel MO8FETs Q5 to Q8, and precharges the complementary data lines DO9Do, Dl, DI, etc. to a high level such as the power supply voltage Vcc. In addition, due to the high level of the precharge signal PC, the N-channel MO8FETQ9 and QIO are turned on, and the common complementary data, 1lcD, and σ, are connected to the ground potential GN of the circuit.
Precharge to low level like D.

The latch circuit FF takes in the supplied address signal ADD at the timing when the chip enable signal CE changes from low level to high level. As a result, the X address decoder and the Y address decoder decode the address signal ADD taken into the latch circuit FF, and decode one word line Wi and a pair of complementary data lines D.
Column selection line Yj corresponding to column selection lines Yj and Dj is set to a high level selection state. At the same time, as the step enable signal CE changes to high level, the precharge signal PC changes from low level to high level, and the precharge signal PC changes from high level to low level, causing the precharge MO8PETQ5 to Q8 and Q9. , Ql
O is turned off.

Along with the selection operation of the column selection line Yj, the common complementary data line CD, CD and a pair of complementary data line Dj.

Dj is combined. As a result, the complementary data line Dj
, Dj and the common complementary data lines CD, CD tend to change to equal intermediate potentials according to the capacitance ratio of the stray capacitances parasitically added to each. At this time, the word line W
Since the selection operation of i is also performed at the same time, a read signal according to the stored information of the selected memory cell appears on the complementary data lines DJ and Dj. Therefore, complementary data line D
j.

The potentials of Dj and the common complementary data lines CD and CD are voltages in which the change in the intermediate potential and the signal due to the read operation of the memory cell are superimposed. As described above, the read signal from the memory cell is transmitted to the common complementary data lines CD and CD by the amplification effect of the P-channel MO8FET forming the column switch.

The timing generation circuit TG changes the timing signal 8AC from low level to high level when a read operation is instructed by the read/write control signal R/W. This allows the sense amplifier power switch M
O8FETQz4 turns on and differential amplification MO8F
ETQl 9.

Supply operating current to Q20. When the sense amplifier is activated in this way, its input voltage is raised to an intermediate potential by the coupling of the complementary data lines Dj, Dj and the common complementary data lines CD, CD, so that the sense amplifier has the highest sensitivity. It is biased to a high operating point and performs an amplification operation of a minute read signal superimposed on the intermediate potential. This enables high-speed read operations.

That is, in this embodiment, in order to cause the sense amplifier to perform amplification operation at the operating point with the highest sensitivity, the selection operation of the column switch is used without providing a second stage precharge period (equalization period). It is something to do. This eliminates the need to set the time required for precharging, thereby ensuring higher-speed operation.

In addition, since the complementary data lines Do, DO, Dl, Dl, etc. are precharged to the power supply voltage Vcc side, even if the word line selection operation is performed at the same time as memory access, the information in the memory cell will be erroneously inverted. Never.

On the contrary, complementary data lines Do, DO and DI.

In the method of precharging all the circuits such as 51 to the ground potential of the circuit, erroneous writing is likely to occur. This is because if a word line is selected while the complementary data lines are both at low level, the high level potential of the flip-flops forming the memory cell will change to the low level potential relatively easily. . For example, suppose that in the memory cell shown in FIG. 3, a high level potential is held at node A and a low level potential is held at node B. Complementary data line D
When word line WO is set to high level while O and Do are both at low level potential, load resistor R1 and MO8FET
A current flows between the power supply voltage Vcc supply terminal and the data line DO via Q3. As a result, the voltage drop caused by the load resistor R1 undesirably changes the potential of the node A from a high level to a low level.

In this case, if the complementary data lines D0°1)O are both at a high level as in this embodiment, even if the word line Wo is set at a high level, the potential of the node A remains at the level of 1. Further, the low level potential of the node B is also maintained as it is. The charge precharged to the data line DO coupled to the node B is transferred to the MO8FETQ in the on state.
2, the potential of the node B will not undesirably change from a low level to a high level.

With this K, the word line selection operation etc. can be started immediately after the completion of the precharge operation for the complementary data line.

FIG. 5 shows the capacitance ratio DC between the capacitance value DC of the capacitor C1 on the complementary data line in the memory array M-ARY and the capacitance value CDC of the capacitor C2 on the common complementary data line.
The relationship between /CDC and access time TA is shown. This characteristic diagram was obtained by computer seam radiation, and the access time TA is the shortest (the capacitance value CDC of the common complementary data line is 2/1 of the capacitance value DC of the complementary data line). The reason for this is that the capacitance value on the CD side of the common complementary data line CD is set to be smaller than the capacitance value DC of the complementary data line. This is because the potential of the complementary data lines CD, CD can be quickly changed to the operating point of the highest sensitivity of the sense amplifier. It is desirable to set the number of coupled complementary data lines or add a dummy capacitor to the common complementary data line when the parasitic capacitance of the common complementary data line is small.On the contrary, if the capacitance value of the common complementary data line is large sometimes,
Either the common complementary data line may be divided and a sense amplifier provided for each, or the number of memory cells coupled to the complementary data line may be increased. In this way, the most efficient read operation can be achieved by adjusting the number of word lines and data lines constituting the memory array M-A)t, Y.

Note that since the write operation is performed in the memory cell using a large signal level, writing can be performed in a shorter time than in the read operation. Therefore, the access time of the RAM is determined by the read operation, and by adopting the above-mentioned precharge method and its memory access, it is possible to realize high speed R and AM.

Note that in the embodiment shown in FIG. 3, the values of the parasitic capacitances connected to the common complementary data lines CD and CD are made different from each other to speed up the read operation of information stored in the memory cells. is possible. In this embodiment, it is reasonable to make the capacitance value of the parasitic capacitance connected to the common data line CD smaller than the capacitance value of the parasitic capacitance connected to the common data line CD. By setting the magnitude relationship of the capacitance values as described above, it becomes possible to control the magnitude relationship of the rising speed of the respective potentials of the common complementary data lines CD, CD in the high level direction accordingly. . i.e. column switch (eg MO8FE'I'Q11).

゛ Q12. Q15 and Q16) are turned on, the potentials of the common complementary data lines CD and CD both rise from low level to high level, but the rising speed is faster than that on the common data line CD side. CD
The side is faster.

Therefore, when high level information is stored in the node BK of the memory cell and low level information is stored in the node A, a minute potential difference occurs between the complementary data lines Do and Do in accordance with the memory cell information. The direction coincides with the direction of the potential difference generated between the common complementary data lines CD and CD based on the capacitance value difference. Therefore, the minute potential difference generated between the complementary data lines Do and DO is expanded more quickly. Therefore, the speed of the amplification operation by the sense amplifier made up of MO8FETQI9 to Q24 is increased. In this case, the output signal of the sense amplifier formed at the common connection point of MO8FETQ22 and Q20 changes rapidly from high level to low level.

On the other hand, when low level information is stored in the node B of the memory cell and low level information is stored in the node A, the complementary data lines Do, D.

The direction of the minute potential difference that occurs between them does not match the direction of the potential difference that occurs between the common complementary data lines CD and CD based on the capacitance value difference. However, this does not prevent faster read operations. This is because in this case, the output signal of the sense amplifier formed at the common connection point between MO8FETs Q22 and Q20 maintains the high level during precharging.

Therefore, when the sense amplifier of this embodiment is used, it is possible to speed up the information read operation by speeding up the operation when the output signal changes from high level to low level.

Note that the capacitance value of the parasitic capacitance connected to the common data line CD is extremely smaller than the capacitance value of the parasitic capacitance connected to the common data line CD (then, the memory cell information itself will be inverted and incorrect information will be generated). When read, a malfunction occurs.According to the studies of the present inventors, the ratio of the capacitance values is preferably about 6:5, for example.

The effects obtained from the above examples are as follows. That is, (1) During the precharge period, the data line pair to which the memory cells are connected is precharged to the power supply voltage side, and the common data line connected to the data line is connected to the circuit ground potential side via the column switch. To recharge. As a result, the data line pair and the common data line pair are coupled through the column switch as the memory cell is selected, and the potentials of the data line pair and the common data line pair are set to an intermediate potential by one precharge operation. can. Therefore, the sense amplifier amplifies the read signal at the operating point of the highest sensitivity while selecting the memory cell, and this results in the effect of shortening the time required for precharging and realizing high-speed read operation. It will be done.

(2) To set the potentials of the data line pair and the common data line pair to an intermediate potential using column switches,
The effect is that the circuit can be simplified.

(3) During the precharge period, the data line pair connected to the memory cell is precharged to the power supply voltage side, and the common data line pair connected to the data line pair is connected to the circuit ground potential side via the column switch. By precharging, there is no need to provide a special time margin for the memory cell selection operation and the sense amplifier operation timing, so the timing setting becomes easy, and the effect of increasing the operation margin can be obtained.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples (although it is possible to make various changes without departing from the gist of the invention). For example, a memory cell as a static type RAM is a P-channel MO8P.
A completely static memory cell configured by combining an ET and an N-channel MO8FET may be used. In addition, when the common complementary data line is divided and a sense amplifier is provided for each, a second column selection circuit is provided on the output side, or the sense amplifier itself is connected to the second column selection circuit.
It may be selectively activated by a column selection signal. Further, the memory access may be performed by an internal synchronization method in which a change in the address signal is detected and the precharge signal is generated.

In the above explanation, the invention made by the inventor of the present application has been mainly explained using as an example the case where it is applied to a RAM built in a digital integrated circuit, which is the technical field that is the background of the invention, but the invention is not limited to this. (For example, the present invention can be applied to a RAM built in a one-chip microcomputer.
, or a semiconductor storage device as an external storage device.
In addition, the present invention can be similarly applied to various ROMs such as mask-type ROM (read-only memory) and EFROM (erasable and programmable ROM). In such a ROM, the memory cells are coupled to one data line, so if a differential sense amplifier is used, a reference voltage is formed and the read signal is sensed. . In this case, the reference voltage can be formed using a constant voltage circuit or a dummy cell. In these various ROMs, the data line is precharged to the power supply voltage side, the common data line is precharged to the circuit ground potential, and the DC potential of the common data line is connected to the sense amplifier as the memory cell is selected. Since the operating point with the highest sensitivity can be set, it is possible to speed up the read operation.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, during the precharge period, the data line to which the memory cells are coupled is precharged to the power supply voltage side, and the common data line coupled to the data line via the column switch is precharged to the ground potential side of the circuit. Then, the data line and the common data line are coupled through the column switch in accordance with the memory cell selection operation, so that the potentials of the data line and the common data line can be set to an intermediate potential with only one precharge operation. Therefore, the sense amplifier amplifies the read signal at the operating point of the highest sensitivity while selecting the memory cell, and together with the shortening of the time required for precharging, a high-speed read operation can be realized.

[Brief explanation of the drawing]

1 is a plan view of an embodiment of a semiconductor substrate on which a static RAM to which the present invention is applied; FIG. 2 is a layout diagram of an embodiment of the static RAM of FIG. 1; Figure 4 is a circuit block diagram of an embodiment of a static RAM to which the present invention is applied. Figure 4 is a timing diagram showing an example of a read operation in the RAMK of this embodiment. Figure 5 is a diagram showing the read access time and , is a characteristic diagram showing the correlation between the capacitance ratio of the data line and the common data line. BP... Bonding pad, LC... Logic circuit section, Ilo... Input/output circuit, M-ARYl, 2... Memory arrays 1, 2, RDCR... Row address decoder, WDI, 2.・Word line drive circuit 1, 2, CTL
...Control circuit, SA...Sense amplifier, WA...
Write amplifier, KA...read amplifier, MC...memory cell, FF...latch circuit, TG...timing generation circuit4. ′− ＼ ±

Claims (1)

[Scope of Claims] 1. A plurality of word lines, a first data line pair, a second data line pair provided corresponding to the first data line pair, and each word line and the first data line pair, respectively. a switch means for electrically isolating or coupling the plurality of coupled memory cells, the first data line pair, and the second data line pair; A first precharge means for setting the voltage of the second data line pair to a second voltage level, and information of the selected one memory cell The second signal is transmitted to the sense amplifier via the data line pair, the switch means, and the second data line pair.
1. A semiconductor memory device comprising: a sense amplifier coupled to a data line pair. 2. The semiconductor memory device according to claim 1, wherein the first voltage level is a positive power supply voltage level, and the second voltage level is a ground voltage level. 3. The switching means connects the first data line pair and the second data line pair in synchronization with the timing when the voltage of the word line corresponding to the memory cell to be selected changes to a selection level. A semiconductor memory device according to claim 2. 4. The semiconductor memory device according to claim 3, wherein the operation of the switch means is controlled by a decoder that decodes the address signal. 5. A plurality of word lines, a first data line pair, a second data line pair, a third data line pair provided corresponding to the first data line pair and the second data line pair, each word line, and the above A first memory cell group, each word line, each coupled to a first data line pair, a second memory cell group, each coupled to the second data line pair, the first data line pair, and the third data line. a first switch means for electrically separating or coupling the second data line pair and the third data line pair; and a second switch means for electrically separating or coupling the second data line pair and the third data line pair; A first precharging means for setting the voltage of the first data line pair and the voltage of the second data line pair to a first voltage level; and setting the voltage of the third data line pair to a second voltage level. Information on one memory cell selected from the first memory cell group is transmitted to the sense via the first data line pair, the first switch means, and the third data line pair. The information of one memory cell selected from the second memory cell group is transmitted to the amplifier and is transmitted to the second memory cell group.
A semiconductor memory device comprising a data line pair, a sense amplifier coupled to the third data line pair, which is transmitted to the sense amplifier via the second switch means and the third data line pair. 6. The semiconductor memory device according to claim 5, wherein the first voltage level is a positive power supply voltage level, and the second voltage level is a ground voltage level. 7. The first switch means or the second switch means switches between the first data line pair and the third data line in synchronization with the timing when the voltage of the word line corresponding to the memory cell to be selected changes to the selection level. 7. The semiconductor memory device according to claim 6, wherein a line pair or said second data line pair and said third data line pair are coupled. 8. The semiconductor memory device according to claim 7, wherein the operations of the first switch means and the second switch means are controlled by a decoder that decodes the address signal.