JPH01240985A - Image data processor - Google Patents

Abstract

PURPOSE:To make efficient an image data processing by dividing the image data into a matrix condition, and storing obtained adjacent units into separate memory blocks. CONSTITUTION:Firsts, the image data are divided into the matrix condition, and for the mutually adjacent units obtained in such a way, their image signals are stored into separate memory blocks 201 and 202. When the image to be read lies over the two units, the image is read from a pair of adjacent units which surely shares a side. Thus, when they are stored into the separate memory blocks 201 and 202, the image signal corresponding to the image to be read can be read at once by a single access.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image data processing device that processes two-dimensional images bit by bit.

(Prior Art) In general information processing devices, character data and numeric data are processed using so-called code data. On the other hand, 2
Dimensionally imaged data needs to be processed bit by bit in memory.

FIG. 2 shows a block diagram of a conventional image data processing device.

This device is provided with an image data memory 1 that stores two-dimensional image data of 4n bits in the X direction and m bits in the Y direction. Normally, data in memory is
For example, data for one word of 4-bit or 8-bit configuration is read or written as a unit. Therefore, this image data, as shown in the figure,
It is divided into strips with a width of n bits in the X direction.

Now, let us consider the case where, among the images stored in the image data memory 1, images a, b, or c, d consisting of a series of pixels as shown in the figure are to be processed.

In this case, for example, data with a width of n bits including images a and b may be directly read out.

However, data reading is performed only in units divided in advance with a width of n bits as shown in the figure. Therefore,
The image data memory is divided into two memory blocks 21. ．．
When the image data is divided into 22 strips and the image data is divided into strips of 11 degrees, 12 degrees, 13 degrees, and 14 degrees, respectively, areas 11 and 13 are stored in the memory block 21, and areas 12 and 14 are stored in the memory block. 22.

First, reading out images a and b will be explained.
As shown in the 0 part of memory blocks 21 and 22, n-bit data including image a is stored in memory block 21.
n-bit data including image b is stored in memory block 22. For images c and d, memory blocks 21.2 are also stored from the corresponding areas.
Data is stored separately for 2 as shown in ■.

The data bus selection circuit 3 is a circuit that selects a total of n bits specified by the processor 4 from among the data of a total of 2n bits (n bits + n bits) manually inputted from the memory blocks 21 and 22, and outputs the selected bits. Therefore,
As shown in the figure, when an image signal as shown in ■ is input to the data bus selection circuit 3, images b and a as shown in ■ are input.
An image signal corresponding to the image signal is output to the readout rotator 51 side. Also, when an image signal as shown in ■ is input to the data bus selection circuit 3, an image d as shown in ■ is input.
, c are output. The image signals shown in (2) have an arrangement opposite to that of images a and b that are originally intended to be read.

Therefore, the rotator 51 sequentially shifts the data one bit at a time in the direction of arrow 5' in the figure, and outputs image signals corresponding to images a and b as shown in (■) in the figure.

The image signal shown in ■ is also similar, and the rotator 5
1 sequentially shifts the data one bit at a time in the direction of arrow 5' in the figure, and outputs image signals corresponding to images c and d as shown in (■) in the figure.

As described above, the processor 4 can read out an arbitrary one-word image from two-dimensionally developed image data and execute predetermined processing. Furthermore, when the processor 4 attempts to write an image signal corresponding to such an image into the image data memory 1,
The corresponding image signal is input to the write rotator 52, and the data is stored in the image data memory I in reverse order.

(Problem to be Solved by the Invention) Incidentally, when processing image data, a similar processing request is made for an image in which image signals are arranged in the Y direction. However, in the conventional image data processing apparatus shown in FIG. 2, unless the image to be processed is composed of image signals arranged in the X direction, it is not possible to read it in one access. Can not.

That is, in the case of image processing in which image signals are arranged in the Y direction, accessing the image data memory 0 times and rotating the data by 90 degrees requires complicated processing. In such a circuit, compared to processing image signals arranged in the X direction,
There is a problem in that a very large amount of time is required to process the image signals arranged in the Y direction.

Therefore, the present inventor developed a device as shown in FIG. 3 (Japanese Patent Application No. 183484/1984) so that image data can be processed at high speed in both the X and Y directions.

For the sake of simplicity, FIG. 3 shows an image data memory 1 that stores two-dimensional image data having a 4.times.4 bit structure.

This image data memory 1 contains, as shown in the figure,
Image signals numbered O to 15 are stored. It is assumed that the X and Y directions in this figure directly represent the X and Y directions of the image, and that each pixel is arranged according to this image signal.

The processor 4 converts four pixels arranged in the X direction or four pixels arranged in the Y direction from this image into one
It is assumed that read processing is performed as a word.

For this reading process, first, the buffer memory 53
, 54, 55, and 56 are prepared. These buffer memories 53 to 56 are all memory elements having an address capacity of 1 bit in width and 4 bits in depth. That is, each of the buffer memories 53 to 56 writes or reads an image signal one bit at a time, and can store a total of 4 bits of image signals in the order of their addresses, and the writing or reading is performed by the address generation circuit. It is controlled by an address signal output from 50.

Further, the image signals are inputted from the image data memory 1 to the buffer memories 53 to 56 as shown by the arrows, but in reality, as shown in the figure, the image signals are input in advance to the image data memory 1 on the same column in the X direction. The image signals are rearranged so that the pixels lined up are sequentially shifted by one pixel in the X direction.

That is, the image signals arranged in the order of 0.1 and 2°3 in the image data memory 1 are stored in the buffer memories 53 to 56.
The image signals stored in the order of 4.5.6.7 in the image data memory 1 are stored in the order of 0, 1, 2.3, etc. in the buffer memories 53-53.
56, the array is rearranged and stored in the order of 7°4.5.6 so that it is shifted to the right by one bit. The next image signals 8.9, 10.11 are stored in the buffer memories 53 to 56 with an additional 1 bit shift, and the last image signals 12, 13° and 14.15 are stored in the buffer memories 53 to 56 with a 3 bit shift. .

The address generation circuit 50 is connected to each buffer memory 53 to 56.
outputs an address signal to each buffer memory 53 to 56.
When an image signal is read out from the image signal, signals like ■ to ■ in the figure are read out.

■ in the figure indicates a case where image signals 0, 1, 2.3 are read out as they are from the buffer memories 53-56.

■ in the figure indicates the image signal 7 from the buffer memories 53 to 56,
4, 5.6 are read out, but compared to the state actually stored in the image data memory 1, this is shifted by 1 bit in the X direction, so as shown by the arrow in the figure. After rotating the data by 1 bit, the processor 4 takes it in.

This process is performed by a rotator as shown in FIG.

■ in the figure indicates a case where image signals corresponding to pixels arranged in the Y direction are read out. When the address generation circuit 50 inputs a predetermined address signal to the buffer memories 53 to 56, the image signals O14, 8, and 12 are read out as they are.

■ in the figure is an image signal corresponding to pixels arranged in the Y direction, and is an image signal shifted by 2 bits in the Y direction, 0, 14
, 2.6 is read out. In this case, the read image signal is read out to the processor 4 after being rotated by 2 bits.

As explained above, when image signals are read out from the image data memory 1 to a plurality of buffer memories each having a width of 1 bit in a predetermined order, image signals of a predetermined width can be read out at high speed in both the X direction and the Y direction. Can be done. However, this configuration has the problem that if the image data memory 1 has a large capacity, an extremely large number of buffer memories are required, which complicates the processing.

The present invention has been made with attention to the above points, and it reads data at high speed in both the X and Y directions, and freely and efficiently processes image data using a large capacity image data memory. The object of the present invention is to provide an image data processing device that can perform the following steps.

(Means for Solving the Problems) The image data processing device of the present invention divides image data into a matrix by straight lines along the X direction and the Y direction that are orthogonal to each other, and divides the image data into a matrix with the same number of pixels in the X direction and the Y direction. Two memory blocks are prepared for storing image signals corresponding to all the pixels constituting the image data, and among the units, the units are adjacent to each other and share the sides. The image signals corresponding to all the pixels constituting the image data are divided into two and stored so that the image signals of the same type are stored in separate memory blocks. It consists of a group of memory elements with a width of 1 bit and a depth of A (A is a positive integer indicating the address capacity of the memory) corresponding to the number of pixels in the X direction of the unit. Arrangement conversion of the image signal is performed so that the pixels lined up in the direction are sequentially shifted by one pixel in the X direction, and the image signal of each unit after this arrangement conversion is divided in the Y direction and divided into separate units. In order to store in a memory element and read out from the two memory blocks an image signal corresponding to a series of pixels continuous in the X direction or Y direction among the image signals of two units adjacent to each other and sharing the side, A memory address for generating, for each memory block, an address signal for reading out the image signals one by one from each memory element constituting the memory block, and an element selection signal for selecting a memory element to be read out. and a rotator that shifts and converts the arrangement of the image signals simultaneously read out from each of the memory elements in the X direction so as to restore the image made up of the continuous series of pixels. It is characterized by:

(Operation) The apparatus of the present invention first divides image data into a matrix, and stores the image signals of adjacent units among the thus obtained units in separate memory blocks.

If an image to be read spans two units, the image will always be read from a pair of adjacent units that share an edge. Therefore, by storing these in separate memory blocks, the image signals corresponding to the image to be read can be read out all at once in one access.

Furthermore, each memory block consists of a memory element group with a capacity of 1 bit in width and A bit in depth, and image signals corresponding to pixels arranged in the X direction and image signals corresponding to pixels arranged in the Y direction are - The order in which image signals are stored is devised so that they can be retrieved at the same time. If the memory address generation circuit generates and supplies predetermined address signals to these memory elements,
An image signal corresponding to a desired image can be read out from any location in both the X and Y directions. Since the read signals are stored shifted in a predetermined direction in each memory element, the rotator converts the arrangement and takes out the signals.

(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an image data processing apparatus of the present invention.

This device includes a first memory block 201 and a second memory block 202 that store image data 100 divided into two parts. The image signals read out from these memory blocks 201 and 202 are manually input to the rotator 300 and then read out to the processor 400. Moreover, the first memory block 20
A memory address generation circuit 500 is provided to supply address signals to the first and second memory blocks 202.

Now, as shown in the figure, the image data 100 is
Each is divided into, for example, four parts by a straight line along the direction, and is divided into a matrix shape. As a result, the image data becomes 4×
4, that is, a total of 16 units 101. Each unit 101 has a pixel 102 of 16 bits in total, 4 bits in the X direction and 4 bits in the Y direction.
It is assumed that it consists of

Note that when dividing the image data 100, the number of divisions in the X direction and the Y direction may be arbitrary, but the pixels composing the unit 101 must be arranged in the same number in the X direction and the Y direction for signal processing. It takes.

The first memory block 201 and the second memory block 202 have a capacity that can store all the pixels constituting the image data 100 shown in the figure divided into two parts. In this case, the first memory block 201 stores the image signal of the unit labeled with the same symbol #1 among the image data 100 shown in the figure. The second memory block 202 stores the image signal of the unit numbered #2. That is, the first memory block 201
The storage locations of the second memory block 202 and the second memory block 202 are selected so that units that are adjacent to each other and share the side 103 are stored separately. Note that the side 103 is a boundary between each unit shown in an enlarged view of the unit 101 in the figure.

The processor 400 also receives one word (width 4) from this device.
bit) data is read and processed. Therefore, as shown in the enlarged part of the unit 101 in the figure, for example, images a and b consisting of 4-bit pixels continuous in the X direction, and images c and d consisting of 4-bit pixels continuous in the Y direction. Reading will be performed. still,
There is also a case where an image e contained entirely in one unit is read out.

A more detailed wiring diagram of each block in FIG. 1 is shown in FIG. 4.

In the figure, first, the first memory block 201 has four
one memory element M13. M12. It is composed of Ml 1°M 10. Further, the second memory block 202 similarly includes four memory elements M23°M22. M21. M
It is composed of 2O. That is, each memory block is provided with four memory elements, the number of which corresponds to the number of pixels in the X direction of one unit 101 of the image data 100 shown in FIG. Each memory element is composed of a memory element group having an address capacity of 1 bit in width and 32 bits in depth.

That is, the image data in the image data memory 110 is composed of 4 x 4 units as in the example shown in FIG. 1, and one memory block contains image signals for 4 x 2 units. Since each memory block is provided with four memory elements, two units of image signals must be stored in one memory element. From this, a 4×4×2, ie, 32-bit image signal is stored in one memory element.

On the other hand, the memory address generation circuit 500 includes an X/Y direction register 510 that stores data indicating the arrangement direction of images to be read or written, and an X coordinate register 510 that stores data indicating the X coordinate of the starting point of the image. 5
20, and a Y coordinate register 530 that stores data indicating the Y coordinate. Based on these signals, in order to output address signals to each memory element of the first memory block 201 and the second memory block 202, the unit address generation section 540, the pixel address generation section 550, and the element selection A section 560 is provided.

The unit address generator 540 receives the X/Y direction signal 511 output from the X/Y direction register 510 and the X coordinate (X3,
2, XI, XO) (7) Upper 2 bits X3.
X2 and the upper two bits Y5 .
Y2 is input. The pixel address generation section 550 includes
In addition to the X/Y direction signal 511 output from the /Y direction register 510, the X coordinates (X3, X2) output from the X coordinate register 520.

X+, Xo) (') Lower two bits x,, Xo, and the Y coordinate (Y3
, Yz , Y+ , Yo ), the lower two bits Y, ,
Y, inputs.

Further, the outputs of the X coordinate register 520 and the X coordinate register 530 are inputted as they are to the element selection section 560. Then, from the unit address generation unit 540, each of the three units that specifies which unit of the image signals stored in each memory element in the first memory block 201 and the second memory block 202 is to be read out. Two sets of bit-configured unit addresses 501 are output. Further, the image address generation section 550 outputs four sets of pixel addresses 502, each consisting of 2 bits, which specify which pixel of the unit specified by the unit address 501 corresponds to an image signal to be read out. Element selection section 560
From then on, for the data bus 301 with four 4-bit configurations,
Eight sets of 1-bit selection signals 503 are output for selecting which memory element is to be connected out of the two memory elements that are connected.

Therefore, a unit address 501, a pixel address 550, and an element selection signal 503 are input to each memory element of the first memory block 201 and the second memory block 202, and the read 1-bit signal is used as data. The signal is connected to be outputted to the rotator 300 via the bus 301.

The rotator 300 includes a reading unit 310 and a writing unit 320 connected to a data bus 301, and a rotation amount generating unit 330 that instructs these units to rotate.

The readout section 310 is a circuit, as shown in FIG. 3, which shifts the image signal as appropriate from 1 bit rotation to 3 bit rotation and outputs it to the output side. The processor 400 reads the rotated image signal via the 4-bit data bus 302, and also sends the data to be written to the image data memory 110 via the data bus 302 to the rotated write unit 320. Output. The rotation amount generation unit 330 generates an X coordinate (X3, X2, X+, Xo) (') output from the X coordinate register 520 of the memory address generation circuit 500.
The lower 2 bits xl and xo and the lower 2 bits Yl and Yo of the Y coordinate (Y3, Yz, Y+, Yo) output from the Y coordinate register are input, and the rotation amount according to the data being handled is calculated. , a circuit that controls the amount of rotation of the read section 310 and the write section 320.

Next, the relationship between the image signals stored in the image data memory 110 and the image signals stored in the first memory block 201 and the second memory block 202 will be described in detail.

FIG. 5 is an explanatory diagram specifically showing the configuration of the memory block and the image signals stored therein.

In the figure, an image data memory 110 stores image signals of 16 bits in the X direction and 16 bits in the Y direction, and each image signal is numbered from 0 to 255.

Also, as shown on the right side of the figure, the first memory block 20
Each memory element M13°Ml 2. Ml 1
．． Each MIO has a capacity of 1 bit wide and 32 bits deep, and its data is read and written using each 5-bit address. Of these, the upper 3 bits are the unit address, and the lower 2 bits are the pixel address.

That is, for example, if we focus on the 4x4 bit configuration unit in the upper left corner of the image data memory 110, this unit has 0, 1, 2, 3 degrees, 16.17, 18, 19 degrees.
, 32, 33, 34° 35.48, 49, 50.51 image signals are stored. These image signals are the first
Memory element M13. of the memory block. M12. Ml
It is stored in addresses from ooooo to 00011 of 1°MIO.

The storage method is as follows.

That is, the arrangement of image signals is converted so that the pixels arranged in advance in the same column in the X direction within this unit are sequentially shifted by one pixel in the X direction.

This is done in the same manner as in the case where the image signals are stored in the buffer memories 53 to 56 already explained with reference to FIG. Another point is that the image signals after array conversion are divided in the Y direction and stored in separate memory elements.
It is similar to that shown in FIG. Incidentally, the image signals of the unit on the right side or below adjacent to this unit are stored in the second memory block 202, as shown in FIG. The storage method is the same.

Next, the operation of unit address generation section 540 shown in FIG. 4 will be explained.

FIG. 6 is a specific wiring diagram of the unit address generation section.

This unit address generation section 540 includes an address converter 541 that receives the outputs of an X/Y direction register 510, an X coordinate register 520, and a Y coordinate register 530.
The output of this address converter 541 and some bits of the X and Y coordinates, Ys.

X3. Adder 542 and adder 543 that receive Y2
It is composed of.

Address converter 541 outputs 4-bit output signals Ql, Q2°Q3 . Q
This is a circuit that obtains 4. Further, the adder 542 receives the X coordinates output from the X coordinate register 520, X3 . X2, XI
, the most significant bit x3 of Xo, and the Y coordinate output from the Y coordinate register 530 ¥3 Y2 , Y+ ,
Input the upper two bits Y3 and Y2 of Yo,
Signal Q3. output from address converter 541. This circuit adds a predetermined value to Q4 and outputs a unit address for the first memory block. Like the adder 542, the adder 543 receives the signals from the X coordinate register 520 and the Y coordinate register 530, and also receives the output signals Ql and Q2 of the address converter 541 to perform a predetermined operation. , is a circuit that outputs a unit address for the second memory block.

The operation of this circuit will be explained in detail using FIGS. 7 and 8.

FIG. 7 is an explanatory diagram of the principle of selecting a unit address.

In the figure, as explained earlier, the image data memory 100 is composed of 4 x 4, that is, 16 units, and each unit is composed of a 16-bit image signal, so a total of 4 x 4 x 16-bit images are generated. The signal is divided into two parts and stored in the first memory block 201 and the second memory block 202. That is,
A 4×4×8, ie, 4×32 bit image signal is stored in the first memory block. The same applies to the second memory block. Then, as shown in the figure, each unit is assigned a unit number in advance such as <0> to <7>. In this case, units stored in the first memory block 201 are marked with hatching, and adjacent units stored in the second memory block 202 are also given the same number.

In this way, all memory blocks have <0 in order from the top.
>~7> units are stored.

Here, the X and Y coordinates in the image data memory 110 are each 4-bit digital data as explained above, but we will focus on the second bit from the top, that is, the X2' and Y straddle. However, as shown in FIG. 7, the position of each unit can be identified as 0.1°0.1. That is, for example, there are a total of four units in which x2 is O and Y2 is 0: the unit in the upper left corner, the unit two places to the right of it, the unit two places below it, and the unit two places to the left of it. By utilizing such a relationship, a unit address can be created as shown in FIG.

In FIG. 8, first, the input and output signals of the address converter 541 shown in FIG. 6 are shown at the left end. The input signal is an X/Y direction signal, which means that when it is O, images aligned in the X direction are processed, and when it is 1, images aligned in the Y direction are processed. Also, X2, y
'2 is the data as explained using FIG. Then, the address converter 541 shown in FIG. 7 converts Ql, Q2 . Q3. Q4
Outputs data such as. Further, on the right side, units selected in pairs in each memory block are displayed. That is, for example, if the unit at the upper left corner of FIG. 7 is the unit that includes the starting point of the image to be read out, the unit at the end point of the image will be the unit to the right or below. The units on the starting point side and the units on the ending point side are limited by the input signal of the address converter 541, and the combinations thereof are shown in the table of FIG.

In these cases, indicate whether the unit stored in the first memory block will be on the starting point side or the unit stored in the second memory block will be on the starting point side in the column labeled pair relationship in Figure 8. it's shown. That is, for example, assume that the unit on the starting point side is the <0> unit of the first memory block.

In this case, the input signal X2. of the address converter 541.
Both Yz becomes O. If X,/Y is 0, it is an image in the X direction, so the units in a pairing relationship are <0> of the first memory block and <O> of the second memory block (#1-12). becomes. Therefore, when the unit number of the first memory block is selected as 0, 10, that is, the same unit number O is selected for the end point side, and this is output from the data address generation section 540 as the unit address in FIG. It will be done.

Also, if X/Y=1 at the same starting point, that is, images are lined up in the Y direction, the paired units are <0> in the first memory block and <1> in the second memory block.
(#1-#2).

In this case, if the unit number of the first memory block is selected as O, 1 is added to the unit number to generate the unit address of the second memory block on the end point side.

Also, the unit that becomes the starting point is the second memory block (7)
<4> If there are 2, X2 = 1, Yz
= O. Then, when X/Y=O5, that is, the images are arranged in the X direction, the paired units are the second memory block <4> and the first memory block <6>.
>(#2-#1). Therefore, in this case, 2 is added to the unit number 4 of the first memory block to generate the unit address of the first memory block.

Also, if X/Y=1 at the same starting point, that is, images are lined up in the Y direction, the paired units are the second memory block No. 4> and the first memory block No. 5>.
(#2-#1).

Therefore, in this case, 1 is added to the unit number of the first memory block to generate the unit address of the first memory block.

The adders 542 and 543 shown in FIG. 6 generate respective unit addresses as described above, and output the signals to the first memory block and the second memory block.

FIG. 9 shows each memory block shown in FIG. 5: 201,
This is an explanatory diagram of a circuit operation for generating the lower 3 bits of the 5-bit address signal 202. The pixel address generation section 550 shown in FIG. 4 generates a pixel address according to this table.

That is, the pixel address generation unit 550 shown in FIG. 4 receives X/Y, X+, Xo, Y+, and Yo as shown in FIG. A 2-bit pixel address signal as shown in the table is output to each of the four memory elements provided in the block 202.

In this way, when reading in the X direction, the same address is supplied to each element, and when reading in the Y direction, the addresses are sequentially incremented by 1. The reason for this becomes clear when looking at Figure 5. As a result, in the X direction or Y direction, the
The image signal is read out in the manner described in ~■.

FIG. 10 is a table showing the amount of rotation when the image signal read out in this manner is rotated by the rotator 300 shown in FIG. 1.

In this table, memory element M13. M12゜Ml 1
．． MIO, M23. M22. Any four of M21°M2O are selected by the element selection section 560 in FIG. 4 and connected to the data bus 301. The O mark in the table is
It shows which memory element is selected in which case, and the * mark indicates the image signal to be loaded into the MSB (most significant bit).

That is, for example, the image signal at the top of the table is Ml 3. M
l 2. Ml 1. Since the image signal is read from Mlo and the MSB is located at the left end thereof, it is read out to the processor 400 as it is without being loaded. Since the image signal in the next stage is stored as the second MSB from the left, it is output after being rotated by 1 bit. Further, depending on the image to be read out, memory elements are selected in various combinations as shown in the figure, and image signals are read out.

As can be seen from the figure, the rotation amount varies by 0.1, 2, 3 degrees, 1.2.3 degrees, depending on the changes in the signals Xl, This is how things are changing. However, whether the arrangement direction of the images to be read out is the X direction or the Y direction does not affect the amount of rotation. Therefore, X+, Xo,
The rotation amount is uniquely determined by the four signals Y+ and Ya.

Note that X2 = O, Y2 = O or X2 = 1.

If Y,=1 (7), then X,=1. When Y2=O or X2=○, Yl=1, memory element M13
and M23, Ml2 and M22, M11 and M21, MIO
and M2O, respectively. Moreover, it goes without saying that the opposite is true when writing data.

Finally, to explain the specific read operation of the device of the present invention, for example, the image data memory 1 shown in FIG.
10, it is assumed that a 4-bit image whose starting point has coordinates (1, 5) is to be read and written.

This data is 81.82 as shown by the hatching in the figure.
, 83.84, and if the coordinates of the starting point are expressed in binary notation, they become 0OOi, 0101. In this case, the unit address also applies to the first memory block.
001 for each memory block, and unit 1> explained in FIG. 7 is selected from both blocks. Further, the pixel address is ol for all memory elements. That is, the address of the memory element is 5 in decimal notation. Also, the element selection signal at this time is X2 =
Since O, Yl = 1, memory element M23. M1
2. M21. M2O is selected.

As can be seen from FIG. 5, the image signal thus output is an image signal shifted by 2 bits, and therefore is read by the processor by shifting the image signal by 2 bits by the rotator.

Also, this time, the coordinates of the starting point are stored in the image data memory 110.
Let us consider the case of reading and writing image data (3, 3) in which 4 bits are arranged in the Y direction. In this case, the coordinates of the starting point are expressed in binary notation as 0011.0011.

Further, the image signal is 51°67.83.99.

Therefore, the address of the first memory block is <0>, the address of the second memory block is <1>, and the address of the memory element Mll of the first memory block 201 is 0.
0011, and the address 00101 of the memory element M23 of the second memory block 202, and the memory element M
The image signal is read from address 00110 of M22 and address 00100 of memory element M20. In this case as well, since the image signal is shifted by 2 bits, it is read out after being rotated by 2 bits.

The image data processing device of the present invention is not limited to the above embodiments.

When image data is divided into a matrix, the number of divisions or the bit configuration of the divided units may be freely selected. Further, the circuits for address generation, data arrangement conversion, etc. may be replaced with circuits having similar functions as necessary.

(Effects of the Invention) According to the image data processing device of the present invention described above, various two-dimensional image data can be read out in word units, and can be subjected to various processes such as rotation, density conversion, scaling, etc. The process of performing arithmetic processing and then storing the data in the image data memory again can be performed at extremely high speed. Moreover, since the image data arranged in the X direction and the image data arranged in the Y direction can be processed using the same algorithm, there is no problem that the calculation speed differs depending on the direction, and the processor can be used efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the image data processing device of the present invention, FIG. 2 is a block diagram of a conventional image data processing device, and FIG. 3 is an explanatory diagram of the operation of another conventional image data processing device. Fig. 4 is a wiring diagram of an embodiment of the device of the present invention, Fig. 5 is an explanatory diagram of the structure of the memory block and stored image signals, Fig. 6 is a wiring diagram of the unit I/address generation section, and Fig. 7 is An explanatory diagram for unit address selection, FIG. 8 is an explanatory diagram of the operation of the unit address generation section, FIG. 9 is an explanatory diagram of the operation of the pixel address generation section, and FIG. 10 is an explanatory diagram of the image signal and rotation amount. . 100... Image data, 101... Unit,
102... Pixel, 103... Side, 110... Image data memory, 201... First memory block, 202... Second memory block, 300... Rotator, 400... Processor, 500...Memory address generation circuit, 501...
Unit address signal, 502... Pixel address signal, 503... Element selection signal. Patent applicant Oki Electric Industry Co., Ltd. Memory block configuration and stored image signals Figure 5

Claims (1)

[Scope of Claims] Image data is divided into a matrix by straight lines along X and Y directions that are perpendicular to each other, and each unit is a collection of units each having the same number of pixels arranged in the X and Y directions, Two memory blocks are prepared for storing image signals corresponding to all the pixels constituting the image data, and the image signals of the units adjacent to each other and sharing the same side are stored in the separate memory blocks. An image signal corresponding to all pixels constituting the image data is divided into two and stored in a memory block, and each memory block has a number of pixels corresponding to the number of pixels in the X direction of the unit. , a group of memory elements with a capacity of 1 bit in width and A bit in depth (A is a positive integer, indicating the address capacity of the memory), and the pixels arranged in the Y direction within the unit are arranged one pixel at a time. The arrangement of the image signals is sequentially converted so that they are shifted in the X direction, and the image signals of each unit after this arrangement conversion are divided in the Y direction and stored in separate memory elements, and from the two memory blocks. , of the image signals of two units adjacent to each other and sharing that side, in the X direction or in the Y direction.
In order to read image signals corresponding to a series of pixels continuous in the direction, one image signal is read out from each memory element constituting the memory block for each memory block.
a memory address generation circuit that generates an address signal for reading out one memory element at a time and an element selection signal for selecting a memory element to be read out; An image data processing device comprising: a rotator that shifts and converts the arrangement of image signals read out simultaneously in the X direction in the X direction.