JPH01239647A - System for monitoring and controlling abnormal operation of system - Google Patents

Abstract

PURPOSE:To prevent the runaway of a system from occurring by setting a control means at an automatic operating mode by setting the operation/non- operation of the control means by a ready signal from a terminal for debugging and a switch signal from an operation/non-operation setting switch. CONSTITUTION:At the time of developing the system, the control means 23 is set at a non-operating mode by turning OFF a switch 24 when the terminal 21 for debugging is connected to the system 20, and the means 23 is set at an operating mode by turning ON the switch 24. At the time of operating the system, the means 23 is set at the operating mode automatically in spite of the ON and OFF of the switch 24 when the ready signal ER at the time of separating the terminal 21 from the system 20 is applied on the means 23. Therefore, when abnormality is generated in the system, the control means 24 is set at a non-operating mode, thereby, the runaway of the system can be prevented from occurring.

Description

[Detailed description of the invention]

[1 Required] The present invention relates to an abnormal operation monitoring and control method for a system configured by a microprocessor, and the present invention relates to an abnormal operation monitoring and control method for a system configured using a microprocessor.
The purpose is to be able to automatically set the control means to the operation mode regardless of the state of the operation/inoperation setting switch. A system debugging terminal for debugging during system development, an abnormal operation monitoring means for monitoring abnormal operation of the system, and an alarm signal for forcibly stopping the system and operating the system when the abnormal operation monitoring means detects an abnormality in the system. /A system that is set to an active/inactive mode by a switch signal of a switch for inactive setting and a ready signal of the debugging terminal to the system, and that is set to an active mode regardless of the state of the switch during system operation. ) 1 means. [Industrial Application Field] The present invention relates to an abnormal operation monitoring and control method for a system configured using a microprocessor. [Prior Art] When an abnormal operation occurs during the operation of a system configured with a microprocessor, it is necessary to stop the CPU in the system to prevent this system from affecting other systems. However, at the system development stage, abnormal operation of the system is likely to occur, so stopping the CPU every time an abnormality occurs will hinder the progress of system development. Therefore, during system development, abnormal operation monitoring control 'f
"It is necessary to switch the circuit between operating and non-operating states. However, if an abnormality occurs in the system during system operation, the system abnormal operation monitoring control circuit will operate reliably.
It is desired to stop the CPU of the system to prevent the system from having a negative impact on other systems. FIG. 3 is a circuit diagram showing a conventional system abnormal operation monitoring control method. In the figure, a system 1 consisting of a microprocessor is used for debugging and other development purposes, and includes a central processing unit (hereinafter referred to as CPU) 2 that controls the entire system, a ROM 3 for storing the main processing program, and a system 1 that is used for debugging and other development purposes. It is equipped with a RAM 4 for storing calculation results and other data, a first communication adapter 5, a second communication adapter 6, and a collar number input/output device 7, and an abnormal operation monitoring circuit 8 is connected to the CPU 2 via a bus. At the same time, the alarm signal ALM of the abnormal operation monitoring circuit 8 is output to the control circuit 9. The first communication adapter 5 is mainly used during the system development stage and is controlled by a system debug program (standard program).
Terminal 1 for system debugging is connected through cable 10 to
1 (CRT, keyboard, etc.) is connected to send and receive data to and from the terminal 11. The second communication adapter 6 is for communicating with other devices (not shown), and the second communication adapter 6 and input/output device 7 are controlled by a main processing program (this differs for each device). . Further, in the system configured as described above, it is possible to control the main processing program, access the ROM and RAM, access the input/output device 7, etc. from the terminal 11. The abnormal operation monitoring circuit 8 monitors abnormal operations caused by system hardware abnormalities, software abnormalities, or a combination of both. The control circuit 9 at the time of abnormality detection includes a switch 9a that switches between operating and non-operating, and an ON10 of this switch 9a.
It is equipped with a NAND gate 9b which has one input as the switch signal from F F and the other input as the alarm signal ALM which is output when the abnormal operation monitoring circuit 8 detects an abnormality in the system, and the output of this control circuit 9 The end is CPU2
of

In the conventional system abnormal operation monitoring and control method configured as described above, when developing a system, a cable is connected to the first communication adapter 5 of system 1. The terminal 11 is connected via the terminal 10, and the development progresses while controlling the main processing program of the system 1, accessing the memory, accessing the input/output devices, etc. from the terminal 11 side.In this system development stage, step-by-step Since the hardware and software are not yet complete, system abnormalities are likely to occur. Therefore, at the initial stage of system development, the switch 9a of the control circuit 9 is turned on to set the control circuit 9 to a non-operating state, so that the abnormal operation monitoring circuit 8 detects system abnormalities. Even if the alarm signal is detected and input to the control circuit 9, the CPU 2 is not stopped, and when the system development is nearing completion, the switch 9a is turned OFF to set the control circuit 9 to the operating state. In addition, during system operation, the switch 9a is set to OFF and the control circuit 9 is set to the operating state.Therefore, when the abnormal operation monitoring circuit 8 detects an abnormality in the system,
The control circuit 9 is operated by the alarm signal ALM, and a stop command is given to the HA T terminal of CP tJ 2, thereby forcibly stopping the CPU 2, and the abnormally operating system adversely affects other systems. to prevent [Problems to be Solved by the Invention] In the conventional system abnormal operation monitoring control method described above, there is no control system for forcibly stopping the CPU 2 when the system is abnormal.
The operation and non-operation modes of the circuit 9 are set using the switch 9a.
This is done manually by turning ON and OFF the switch, so if switch 9a, which should be set to OFF state at the time of system delivery, is mistakenly set to ON state, abnormal operation monitoring will be performed during system operation. Even if the circuit 8 detects a system abnormality, the control circuit 9 does not operate, which may cause the system to run out of control and adversely affect other systems.In addition, there is a problem in that the state management of the switch 9a becomes complicated. . The present invention solves the above-mentioned problems, and is capable of automatically setting the control means to an operation mode during system operation, regardless of the state of the operation/non-operation setting switch of the control means for forced system stop. The purpose is to provide an operation monitoring control method. [Means for Solving the Problems] Fig. 1 is a principle block diagram of the system abnormal operation monitoring and control method of the present invention. In the figure, system 20 is comprised of a microprocessor and performs certain functions. The system debugging terminal 21 is separably connected to the system 20 and performs debugging during system development. The abnormal operation monitoring means 22 monitors abnormal operations of the system 20. The control means 23 controls the system 2 using an alarm signal ALM when the abnormal operation monitoring means 22 detects a system abnormality.
0 is forced to stop, and the operation/
It is set to the active/inactive mode by the switch signal 24a of the inactive switch 24 and the ready signal ER of the debug terminal 21 to the system 20, and during system operation, it is set to the active mode regardless of the ON/OFF state of the switch 24. It is something that [Function] During system development, the debugging terminal 21 is used as the system 20.
The ready signal ER when connected to the control means 23
, the control means 23 is set to the non-operating mode by turning off the switch 24, and the control means 23 is set to the operating mode by turning the switch 24 ON. When the ready signal ER is applied to the control means 23 when the debugging terminal 21 is disconnected from the system 20 during system operation, the switch 24 is turned ON.
, the control means 23 is automatically set to the operating mode regardless of the OFF state. Therefore, the present invention eliminates the need for switching the control means to the operating mode using a switch during system operation, and prevents the problem of the control means going into an inactive mode when a system abnormality occurs, causing the system to run out of control. Can be prevented. [Example] Hereinafter, an example of the present invention will be described in detail based on the drawings. FIG. 2 is an overall configuration diagram of an embodiment to which the system abnormal operation monitoring and control method of the present invention is applied, and the same or equivalent parts as in FIG. 1 are given the same reference numerals and will be described. In the figure, a system 20 composed of a microprocessor includes a CPU 201 that controls the entire system as in the past, a ROM 202 for storing a main processing program, and a CPU 201.
RAM 20 for storing calculation results and other data
3. A first communication adapter 204 that sends and receives signals via the debug terminal 21 and cable 25 mainly during the system development stage, a second communication adapter 205 that communicates with other devices, and a plurality of human output devices 206. The abnormal operation monitoring circuit 22 monitors abnormal operations of the system 20, that is, abnormal operations caused by abnormalities in hardware constituting the system 20, abnormalities in software, or a combination of the two, and is connected to the CPU 201 via a bus 207. has been done. The control circuit 23 controls the CPU 201 of the system 20 to be forcibly stopped, and uses the ready signal ER obtained according to the connection/disconnection of the debugging terminal 21 to the first communication adapter 204 as one input. A NAND gate 231 whose other input is the switch signal of the switch 24 that sets the operation/non-operation of the switch 23, and this NAND gate 2
31 as one input, and an NAND gate 232 having the alarm signal ALM from the abnormal operation monitoring circuit 22 as the other input, and the output signal of the NAND gate 232 is supplied to the HALT terminal of the CPU 201. It has become. Next, the operation of this embodiment configured as described above will be explained. When developing the system 20, the debugging terminal 21 is connected to the first communication adapter 204 of the system 20.
The development progresses while controlling the main processing program of the system 20, accessing the memory, accessing the input/output device 206, etc. At the beginning of this system development stage, the switch 24 of the control circuit 23 is turned OFF.
Turn it on when it is nearing completion. When the switch 24 is OFF, the NA in the control circuit 23
A resistor R is connected to the other input terminal of the ND gate 231 →
-■ voltage is applied and the power of the terminal 21 is turned on, so that the ready signal ER from the terminal 21 becomes logic "
1'' and this is applied to one input terminal of the NAND gate 231, so the output of the NAND gate 231 becomes a logic r
Becomes QJ. Therefore, the output of the NAND gate 232 which has the logic output "0" of the NAND gate 231 as one input is the alarm signal ALM from the abnormal operation monitoring circuit 22 (the logic of the alarm signal when abnormal operation of the system is detected is "0"). 1”), the logic becomes “1” regardless of the CPU 20
Even if the CPU 201 is applied to the HALT terminal of No. 1, the CPU 201 will not be stopped. That is, during system development (debugging), even if the control circuit 23 receives an alarm signal from the abnormal operation monitoring circuit 22, it does not operate, enters a non-operational mode, and does not hinder the progress of system development. Also, when the switch 24 is ON, the NAND gate 231
Since the 10V potential applied to the other input terminal of is grounded,
The output of the NAND gate 231 becomes logic "1" regardless of the ready signal ER from the terminal 21. Therefore, this NA
When the other input of the NAND gate 232 which has the logic output 'IJ of the ND gate 231 as one input, that is, the alarm signal ALM of the abnormal operation monitoring circuit 22 becomes logic "1" when the system is abnormal, the output of the NAND gate 232 becomes logic "1". "
0”. Therefore, the CPU 201 is forcibly stopped. Next, the operation of the system 20 will be described. In this case, the debug terminal 21 is the first
Since the ready signal ER is not connected to the communication adapter 204 of the switch 24, the ready signal ER is always logic "0", and the output of the NAND gate 231 which takes this as one input is the O of the switch 24.
N, is held at logic "1" regardless of the OFF state. Therefore, the output of NAND gate 232 is the alarm signal A
Determined by LM logic. That is, the alarm signal ALM of the abnormal operation monitoring circuit 22 that detected the system abnormal operation
When the logic becomes "1", the output of the NAND gate 232 becomes logic "0" and the CPU 201 is forced to stop, thereby preventing the system from running out of control. As described above, in this embodiment, the control circuit 23 has a NAN
By simply adding the D gate 232, the communication adapter 204
The control circuit 23 can be easily set to operate or disable during system development without changing the standard interface between the terminal and the terminal, and when the system is in operation, the switch 24 can be turned ON. System abnormal operation monitoring control circuit 2 regardless of OFF state
3 can be automatically set to the operating mode, and it is possible to prevent the system from running out of control due to forgetting to switch the switch 24 as in the conventional case. The circuit configuration of the control circuit 23 in the present invention is not limited to that of the logic circuit shown in the above embodiment. [Effects of the Invention] As described above, according to the present invention, the operation/non-operation setting of the control means is performed by the ready signal from the debugging terminal and the switch signal from the operation/non-operation setting switch. During system operation, the control means can be automatically set to the operating mode regardless of the state of the switch.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of the system abnormal operation monitoring and control method of the present invention. FIG. 2 is an overall configuration diagram of an embodiment to which the control method of the present invention is applied. FIG. 3 is a configuration diagram of a conventional system abnormal operation monitoring control method. In the figure, 20 is a system, 21 is a debug terminal, 22 is abnormal operation monitoring means, 23 is a control circuit, 24 is a switch, 201 is a CPU, 204 is a first communication adapter, and 231 and 232 are NAND gates.

Claims (1)

[Claims] (1) A system (20) composed of a microprocessor that performs specific functions, and a system debugging terminal (21) that is separably connected to the system (20) and performs debugging during system development.
), an abnormal operation monitoring means (22) for monitoring abnormal operation of the system (20), and an alarm signal when the abnormal operation monitoring means (22) detects an abnormality in the system, forcibly stopping the system and stopping the operation/operation. It is set to the active/inactive mode by the switch signal of the inactive setting switch (24) and the ready signal RE of the debugging terminal (21) for the system (20), and when the system is in operation, it is not related to the state of the switch. A control means (23) for setting the system to an operation mode without any abnormal operation.