JPH01239486A - Output response compressor - Google Patents

Abstract

PURPOSE:To obtain fault information more in detail than before by providing a selecting means which inputs the output response from one output line to the initial stage of a multi-input line type feedback shift register selectively. CONSTITUTION:When a control signal C2 is set to a logical level '0', AND gates 10, 11, and 12 output logic '0' regardless of outputs D1, D2 and D3 from a circuit to be tested, so the values of flip-flops 1, 2, and 3 of front stages are only shifted to the flip-flops 2, 3, and 4. At this time, a control signal C1 controls a multiplexer 13 to input only the output of the circuit to the output response compressor so that only one of the outputs D0, D1, D2 and D3 of the circuit is selected. Namely, the output response compressor which compresses one optional output among D0-D3 from the circuit is realized in this case.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an output response compressor, especially an integrated circuit which is designed to facilitate testing of the logic function of an integrated circuit, and to enable testing of even extremely complex integrated circuits. Concerning an embedded output response compressor.

[Conventional technology]

One method to facilitate logical function testing of highly integrated and complex integrated circuits is to incorporate test mechanisms such as a test pattern generator and test output evaluation section inside the integrated circuit to be tested. It is something that will happen. By doing so, it is possible to easily perform logic function tests on circuits that are embedded within the integrated circuit and cannot be directly accessed from external terminals, making it difficult to test.

By the way, when a test mechanism is incorporated into an integrated circuit, it is impossible to compare a huge number of output responses one by one with expected values, so a method is adopted in which the output responses are compressed and the compressed output responses are compared with the expected values.

This output response compressor is a logic circuit block that occupies an important part of the test I/output evaluation section.
est Conference) collection of papers page 37~
“BtllLT-IN LOGIC BLO” on page 41
CK 0BSERVATTON TECIINTQUE
The multi-input sign analyzer presented in the paper entitled S'° is often used.

This multi-input code analyzer is designed so that inputs can be input to each stage of a linear feedback shift register, and a schematic diagram of an example of a 4-bit multi-input code analyzer is shown.

Figure 2 shows the output from the circuit under test (not shown).

, Di, D2, and D3, each output of the circuit under test in a certain cycle is
, D2. D3 is input to an exclusive OR circuit (hereinafter referred to as EXOR gate), and after exclusive OR operation with each output of flip-flops 21 and 22.23,
It is input to flip-flops 22, 23, and 24. Further, the output Do of the circuit under test is input to an EXOR gate 25, and after an exclusive OR operation between flip-flops 23 and 24, is input to a flip-flop 21.

Then, in the next cycle, each output of the circuit under test is
,,D2. D3 also has flip-flop 21 in exactly the same way.
, 22, 23, and 24, respectively, and the same operation is repeated thereafter. Therefore, no matter how many patterns there are output from the circuit under test, the results will be compressed to 4 bits, the expected value will only need to be 4 bits, and the amount of hardware added for testing can be reduced.

[Problem to be solved by the invention]

However, in the output response compressor described above, the output from the circuit under test. , D, , D2゜D3 are all compressed at the same time, so even though it is possible to judge whether the entire circuit under test is good or bad, it is impossible to obtain any detailed information about the failure location, making failure analysis impossible. Has a point.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output response compressor that eliminates the problems of the prior art described above and provides more detailed information regarding failure locations.

[Means to solve the problem]

The output response compressor of the present invention is a multi-input linear feedback shift register type output response compressor that simultaneously compresses output responses from a plurality of output lines.
first selection means for selectively inputting the output responses from the two output lines to the first stage of the multi-input linear feedback shift register;
It is determined whether each of the output responses from the output lines remaining after removing the arbitrary one from the plurality of output lines is input to each stage other than the first stage of the multi-input linear feedback shift register.
The present invention is characterized in that a second selection means for selecting is provided.

[Effect]

The present invention solves the problems in the prior art by employing the above configuration. In other words, since the conventional technology can only compress all outputs simultaneously, it is only possible to judge the quality of the entire circuit under test. However, the present invention makes it possible to compress each output of the circuit under test one by one. Detailed information on the failure location can be obtained.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a typical embodiment of the present invention.9 In this embodiment, the output from the circuit under test (not shown) is 4 bits, and the number of stages of the output response compressor to compress this is 4 bits. Although the present invention is not limited to this, it goes without saying that the number of stages of the output response compressor may be greater than the number of outputs of the circuit under test.

Now, the output response compressor shown in FIG. 1 responds to the output from the circuit under test. ,D,,D2. Four flip-flops 1.2, 3.4 corresponding to D3, four EXOR gates 5, 6, 7.8 corresponding to each flip-flop, and their outputs are connected to one input of EXOR 6, 7, 8, respectively. AND gates 10, 11, 12 and multiplexer 1
3, and by switching the control signal C2,
It operates as two types of output response compressors.

One is a conventional output response compressor that simultaneously compresses all outputs Do to D3 from the circuit under test, and the other is the output from the circuit under test. Any one of ~D3
It is an output-responsive compressor that compresses only one output.

When the control signal C2 is set to the logic "1" level,
AND gates 10.11.12 output the outputs from the circuit under test, D2. D, and EXOR game) 6, 7.
8 respectively. Therefore flip-flops 2, 3
．． 4 are the outputs from the previous stage flip-flops 1, 2.3 and the circuit under test, D2. The respective exclusive ORs with D3 are input.

At this time, the multiplexer 13 outputs the control signal C1 from the circuit under test. , Dl.

D2. D, output. If you set it to output,
The EXOR gate 5 receives the output Do from the circuit under test, and the flip-flop 1 receives the output Do from the circuit under test.
, 4, and the exclusive OR of this output Do. That is, in this case, as in the conventional example described above, the output from the circuit under test. An output-responsive compressor is realized that compresses ~D3 all at the same time.

Next, when the control signal C2 is set to the logic “0” level,
AND game 1-10.11.12 is the output from the circuit under test, D2. Since the logic "0'° is outputted regardless of D3, the values of the flip-flops 1 and 2.3 in the previous stage are simply shifted to the flip-flop 2.3.4.

At this time, the control signal C1 is the output D from the circuit under test.
o, D,.

D2. Since the multiplexer 13 is controlled to select any one of D3, only the output from the circuit under test that is selectively output by the multiplexer 13 is
The output will be input to the response compressor. That is, in this case, the output from the circuit under test. An output response compressor is implemented that compresses any one of ~D3.

In this way, by providing one output response compressor with two modes, more information about failures can be obtained than in the conventional example. That is, first the output of the circuit under test. ~D, are operated in a mode that compresses them all at the same time, and the Go,/NOGO test of the circuit under test is performed. Then, only for the circuit under test that is determined to be defective,
By applying a mode in which only one output is selectively compressed and sequentially inputting the outputs of the circuit under test to the output response compressor according to the present invention and testing, it is easy to detect which output has issued an incorrect output. This is because it can be done.

In a mode where only one output can be compressed, it is also possible to detect in which pattern of the input pattern a fault was detected, which greatly increases information on the fault location in the circuit under test compared to conventional methods. . Moreover, it can be realized with the addition of a very small number of logic gates.5 [Effects of the Invention] According to the present invention, by adopting the configuration described above, more detailed failure information can be obtained compared to the conventional example. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. Do, D,, D2. D3... Output from the circuit under test, 1.2.3, 4, 21.22.23.24... Free tube flop, 5, 6, 7, 8, 9.25° 26.2
7.28.29...Exclusive OR circuit, 10.11,
12. ...AND gate, 13...multiplexer, CI, C2...control signal.

Claims (1)

[Claims] In a multi-input linear feedback shift register type output response compressor that simultaneously compresses output responses from a plurality of output lines, the output response from one of the plurality of output lines is selected. a first selection means that is input to the first stage of the multi-input linear feedback shift register; and output responses from the remaining output lines excluding the arbitrary one from the plurality of output lines, respectively, to the multi-input linear feedback shift register. 1. A multi-input linear feedback shift register type output response compressor, comprising second selection means for selecting whether or not to input to each stage of the feedback shift register other than the first stage.