JPH01238332A - Stuff multiplexing method for digital transmission equipment - Google Patents

Abstract

PURPOSE:To improve data transmission efficiency by inserting a frame pulse to a time slot position of a stuff pulse so as to use the stuff pulse and a frame pulse in common thereby decreasing excess bit. CONSTITUTION:A selector 16 selects an output of a frame generating circuit 17 and a data alternately to insert a frame to a header of a frame data. A multiplexer 18 is outputted with sequentially by a high speed clock to attain a multiplexed data. A buffer memory 12 always monitors the phase of write clock and readout clock and when the phase difference reaches a limit or over, a phase detection signal is outputted. When the inhibition circuit 16 receives the signal to stop the readout clock thereby stopping the data readout. The frame pulse is used for the stuff pulse taking bit synchronization. Thus, the excess bit is decreased by one, then the data transmission efficiency is increased.

Description

[Detailed Description of the Invention] [Summary] Regarding the stuff multiplexing method for digital transmission equipment that multiplexes low-speed data of multiple channels into high-speed data, the purpose of the present invention is to transfer low-speed data to a buffer memory in frame units for the purpose of efficient data transmission. When reading data that has been written to and read out, the stuff specification is performed when the phase of the write pulse and the phase of the read pulse almost match, and when performing the stuff specification, a frame pulse is inserted at the time slot position of the stuff pulse. It is configured to serve as both a stuff pulse and a frame pulse.

INDUSTRIAL APPLICATION FIELD The present invention relates to a stuff multiplexing method for a digital transmission device that multiplexes low-speed data of a plurality of channels into high-speed data.

For example, if data transmitted on a 1.5 MHz transmission line is transferred to a higher frequency transmission line, such as 6.3 MHz, the amount of information that can be transmitted will increase, so the 1.5 MHz
Data of multiple channels of z, for example, 4 channels, can be superimposed. Such a multiplexing method is called a stuff multiplexing method. When performing stuff multiplexing, a dedicated frame bit indicating the start position of frame data is required, but when performing multiplex transmission within a shell, surplus bits (bits other than the actual data including the frame hit) are required.
It is desirable that there be less.

[Conventional technology] FIG. 5 is an explanatory diagram of the stuff multiplexing method.

It is assumed that data is transmitted from four transmitting terminals T1 to four receiving terminals T2. Here, it is assumed that the line of each terminal T1 is a 1.5 MH2 transmission line. Low-speed data from these terminals is stuff-multiplexed by the multiplexing circuit 1, superimposed on one 6.3 MHz line, and transmitted to the receiving side. On the receiving side, first, the demultiplexing circuit 2 separates the multiplexed data for each channel and sends it to the receiving terminal T2.

FIG. 6 is a diagram showing the PCM secondary group frame format. In the figure, (a) is a G unit, (b) is a G frame that consists of 4 G units, and (c) is a multi frame that consists of 6 units of 12 G frames. It is. The multi-frame is composed of four sets of frames. The number of bits of the multiframe here is 1176 bits. (d)
is a G pulse that is output for each G frame unit, (E) is a frame pulse (F pulse) that indicates the start position of frame data, and (F) is a multiframe pulse (MF pulse) that indicates the start position of a multiframe. be. (g) is a stuffing designation pulse (S pulse) for specifying stuffing to match the bit rates on the writing side and the reading side, and (, h) are stuffing pulses for making the bit rate matching. (S) shows the stuff pulse insertion state (shaded area in the figure)
FIG.

[Problems to be Solved by the Invention] As shown in FIG. 6, in the conventional stuff multiplexing system, stuffing designation pulses are assigned to the time slots of frame data, and are assigned separately from the frame pulses ( (See (S) in Figure 6). Stuff pulses do not transmit data, and therefore the existence of such surplus bits increases the bit rate, making it impossible to perform efficient data transmission.

The present invention has been made in view of these points, and
It is an object of the present invention to provide a stuff multiplexing method for a digital transmission device that can efficiently transmit data. [Means for Solving the Problems] FIG. 1 is a flowchart showing the principle of the method of the present invention. When multiplexing low-speed data from multiple channels into high-speed data using a digital transmission device that can arbitrarily set the frame format, the present invention writes the low-speed data to a buffer memory in units of frames (
Step [1]) When reading the relevant data, stuff is specified when the phase of the write pulse and the phase of the read pulse almost match (step [2]). A frame pulse is inserted at the time slot position of , so that it serves as both a stuff pulse and a frame pulse (step [3]).

Function] Data transmission efficiency is improved by inserting a frame pulse into the time slot position of the stuff pulse, which has not had much meaning in the past, and causing the stuff pulse and frame pulse to iff, thereby reducing surplus bits.

Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a diagram showing an example of the configuration of the transmitting side of a system implementing the present invention, and FIG. 3 is a diagram showing an example of the configuration of the receiving side of the system implementing the present invention. First, the transmitting side will be explained. Low-speed data from channel (CH) 1 enters the interface circuit 11, where the data and clock are separated. Data enters a write/Mailable buffer memory 12, and the data is sequentially written into the buffer memory 12 using the aforementioned clock as a write clock.

On the other hand, the high-speed clock (matching the transmission frequency on the high-speed side) generated by the high-speed clock generator 13 enters the frequency dividing circuit 14 to 1/N (N is the total number of channels to be multiplexed). After being frequency-divided, it passes through the inhibition circuit 15 and enters the buffer 7 memory 12 as a read clock. The read data enters the selector 16. The selector 16 also contains the output of a frame generation circuit 17 that generates frame data, and the selector 16 alternately selects the output of the frame generation circuit 17 and the data to insert a frame into the header portion of the frame data. The output of this selector 16 is CH
It enters multiplexer 18 as the output of l.

The multiplexer 18 has other channels (CH2=
CHN), and these data are sequentially switched and output using a high-speed clock to form multiplexed data. This multiplexed data is outputted as high-speed data via the interface circuit 19.

On the other hand, in these series of operations, the buffer 7 memory 12
The device constantly monitors the phase of the built-in clock and the readout clock, and outputs a phase detection signal when the phase difference between them exceeds a limit value. When the inhibit circuit 15 receives this signal, it stops the read clock and stops reading data. At the same time, the selection operation of the selector 16 and the multiplexer 18
The multiplexing operation is also canceled. If the phase difference between the self-loading clock of the buffer memory 12 and the read clock is within a predetermined value, no phase detection signal is output from the buffer memory 12, so the above operation is performed to obtain high-speed data. It will be output.

As described above, according to the present invention, the frame pulse also serves as a pit-synchronized stuff pulse. Therefore, the number of redundant pits is reduced by one pit, thereby increasing the efficiency of data transmission.

Next, the operation on the receiving side shown in FIG. 3 will be explained. High-speed data coming on the high-speed line enters the interface circuit 21 and is separated into data and clock. and,
These data and clocks enter the demultiplexer 22 and the logic circuit 23.

The output of the logic circuit 23 enters a synchronization circuit 24, and the output of the synchronization circuit 24 is given to the demultiplexer 22 as a synchronization signal. As a result, the demultiplexer 22 separates the input stuff-multiplexed data for each channel and outputs the separated data.

On the other hand, the output clock of the interface circuit 21 enters the frequency divider circuit 25 and is divided into 1/N, and then passes through the inhibit circuit 26 and enters the buffer memory 27 for each channel as a write clock. The buffer memory 27 constantly monitors the phase difference between the write clock and the read clock.
The phase difference detection signal enters a PLL circuit (comprised of an M valve circuit 28a and a voltage control oscillator 28b) 28, and is read from the PLL circuit 28 and given to the buffer 7 memory 27 as a read clock. The data read from the buffer memory 27 (converted to low speed data) is outputted as low speed data via the interface circuit 29.

Here, it would be inconvenient if the frequency of the write clock of the buffer memory 27 is too high compared to the read clock, so the prohibition circuit 26 prohibits the O-tsuku when the clock increases in response to the stuff designation pit from the demultiplexer 22. This makes it easy to synchronize with the clock on the read side.

FIG. 4 is a diagram showing a frame format employing the present invention. In the figure, (a) shows a multi-frame, (b) shows a G pulse, (c) shows a stuff designation pulse, (d) shows a stuff pulse, and (e) shows a stuff pulse insertion state. (E) As is clearer, according to the present invention, since the frame pulse is placed at the position of the stuff pulse, it is possible to make the stuff pulse and frame pulse both serve as the stuff pulse, and it can be seen that the number of surplus bits is reduced by one bit. . Therefore, the efficiency of data transmission is increased.

[Effects of the Invention] As described above, according to the present invention, the stuff pulse and the frame pulse can serve as both, so data transmission efficiency can be improved.

[Brief explanation of the drawing]

Fig. 1 is a flowchart showing the principle of the system of the present invention]-1 Fig. 2 is a diagram showing an example of the configuration of the transmitting side of the system implementing the present invention, and Fig. 3 is a diagram showing the configuration example of the receiving side of the system implementing the present invention. FIG. 4 is a diagram showing a configuration example, FIG. 4 is a diagram not showing a frame format according to the present invention, FIG. 5 is an explanatory diagram of a stuff multiplexing method, and FIG. 6 is a diagram showing a conventional PCM secondary group frame format. In Figures 2 and 3, 11.19 and 21.29 are interface circuits, 12.27 is a buffer 7 memory, 13 is a high-speed clock oscillator, 14.25 is a frequency divider circuit, 15.26 is an inhibition circuit, 16 17 is a selector, 17 is a frame generation circuit, 18 is a multiplexer, 22 is a demultiplexer, 23 is a logic circuit, 24 is a synchronization circuit, and 28 is a PLL circuit. Flowchart illustrating iq of the method of the present invention, Figure 1

Claims (1)

[Claims] When multiplexing low-speed data of multiple channels into high-speed data using a digital transmission device that can arbitrarily set the frame format, the low-speed data is written to a buffer memory in units of frames (
Step [1]) When reading the written data, stuff is specified when the phase of the write pulse and the phase of the read pulse almost match (step [2]). A stuffed multiplexing method for a digital transmission device, characterized in that a frame pulse is inserted at a time slot position of , so that the frame pulse serves as both a stuff pulse and a frame pulse (step [3]).