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JPH01238126A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01238126A
JPH01238126A JP6644488A JP6644488A JPH01238126A JP H01238126 A JPH01238126 A JP H01238126A JP 6644488 A JP6644488 A JP 6644488A JP 6644488 A JP6644488 A JP 6644488A JP H01238126 A JPH01238126 A JP H01238126A
Authority
JP
Japan
Prior art keywords
silicon
film
silicon nitride
nitride film
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6644488A
Other languages
Japanese (ja)
Inventor
Masaharu Yorikane
頼金 雅春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6644488A priority Critical patent/JPH01238126A/en
Publication of JPH01238126A publication Critical patent/JPH01238126A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To stabilize element characteristics while improving moisture resistance and temperature-cycling resistance by using an silicon nitride film through a sputtering method as a passivation film. CONSTITUTION:A P-N junction is formed on the main surface side of an silicon substrate 1, a silicon oxide film 2 is shaped onto the substrate 1, and an aluminum wiring 3 and an silicon chromium resistor 4 are formed. A silicon nitride film 5 is applied onto the silicon substrate 1 including the aluminum wiring 3 and the silicon chromium resistor 4 through sputtering in the atmosphere of the mixed gas of argon and nitrogen, employing silicon as a target. When the film thickness of the silicon nitride film 5 reaches 500Angstrom or more, the stopping power of contaminated ions and moisture is recognized, but the film thickness may be thickened to 1.0mum or more.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置のパッシベーションに関し、特に、
半導体基板上に形成した多結晶半導体抵抗体或は金属抵
抗体の特性安定化に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to passivation of semiconductor devices, and in particular,
The present invention relates to stabilizing the characteristics of polycrystalline semiconductor resistors or metal resistors formed on semiconductor substrates.

〔従来の技術〕[Conventional technology]

従来、半導体装置では、素子の高密度化や高抵抗を得る
為のi結晶半導体抵抗体や高精度抵抗体を得る為の、シ
リコンクロム抵抗体が用いられている。又、半導体装置
の品質、特に耐湿性の観点から、プラズマCVD法によ
る窒化シリコン膜をパッシベーション膜として用いてい
る。
Conventionally, in semiconductor devices, i-crystalline semiconductor resistors are used to increase the density of elements and obtain high resistance, and silicon chromium resistors are used to obtain high-precision resistors. Further, from the viewpoint of quality of the semiconductor device, particularly moisture resistance, a silicon nitride film produced by plasma CVD is used as the passivation film.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の半導体装置では、パッジベージ日ン膜と
してプラズマCVDによる窒化シリコン膜を用いている
為、窒化シリコン膜成長、及びその後のウェーハ熱処理
、組立工程の熱処理でトランジスタ特性や抵抗体の特性
が変動する。特に、高精度を要求される多結晶半導体抵
抗体やシリコンクロム抵抗体を有する半導体装置では、
歩留の低下や品質の低下という欠点がある。プラズマC
VD法による窒化シリコン膜による特性変動の原因は、
この膜中に含まれる多量の水素が主因だと考えられるが
未だ明らかではない。
In the conventional semiconductor device described above, a silicon nitride film produced by plasma CVD is used as a padding film, so transistor characteristics and resistor characteristics vary due to silicon nitride film growth, subsequent wafer heat treatment, and heat treatment in the assembly process. do. In particular, semiconductor devices with polycrystalline semiconductor resistors and silicon chrome resistors that require high precision,
There are drawbacks such as lower yield and lower quality. Plasma C
The cause of the characteristic fluctuation due to the silicon nitride film produced by the VD method is as follows.
It is thought that the large amount of hydrogen contained in this film is the main cause, but it is not clear yet.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点に対し本発明の半導体装置の製造方法は、半
導体基板上に半導体抵抗体またはシリコンクロム抵抗体
などの抵抗体層および金属配線を形成する工程と、前記
抵抗体層を被覆するスパッタ法による窒化シリコン膜を
形成する工程とを含んでいる。前記スパッタ法による窒
化シリコン膜は、被着時のダメージが少なく半導体装置
の素子特性を劣化させず、室温から500℃程度の温度
で成長でき、外部汚染イオン及び水分の阻止能を有して
いるので、パッシベーション膜として優れている。この
窒化シリコン膜は、シリコンをターゲットとしてアルゴ
ンと窒素の雰囲気でスパッタ形成する方法、また、窒化
シリコンをターゲットとしてアルゴン中又はこれに窒素
を混合させた雰囲気でスパッタ形成する方法がある。
In order to solve the above problems, the method for manufacturing a semiconductor device of the present invention includes a step of forming a resistor layer such as a semiconductor resistor or a silicon chrome resistor and metal wiring on a semiconductor substrate, and a sputtering method for coating the resistor layer. and forming a silicon nitride film by. The silicon nitride film produced by the sputtering method causes little damage during deposition, does not deteriorate the device characteristics of semiconductor devices, can be grown at temperatures from room temperature to about 500°C, and has the ability to block external contaminant ions and moisture. Therefore, it is excellent as a passivation film. This silicon nitride film can be formed by sputtering using silicon as a target in an atmosphere of argon and nitrogen, or using silicon nitride as a target in an atmosphere of argon or nitrogen mixed therein.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は、本発明のシリコン半導体装置への一実施例の
断面図である。第1図において、従来技術を用いてシリ
コン基板1の主面側にPN接合(図示せず)を形成し、
さらに基板1の上にシリコン酸化膜2を形成したのちア
ルミニウム配線3、及びシリコンクロム抵抗4を形成す
る。これらの膜厚はそれぞれ1.0μ、500人が適当
である。次に、シリコンをターゲットとしアルゴンと窒
素混合ガス雰囲気中でスパッタし、前記アルミニウム配
線3及びシリコンクロム抵抗4を含む前記シリコン基板
1上に窒化シリコン膜5を0.1μ程度被着する。この
窒化シリコン膜5の膜厚は、500Å以上あれば、汚染
イオン及び水分の阻止能が認められるが、1.0μ以上
に厚くしても良い。
FIG. 1 is a sectional view of one embodiment of a silicon semiconductor device of the present invention. In FIG. 1, a PN junction (not shown) is formed on the main surface side of a silicon substrate 1 using a conventional technique,
Furthermore, after forming a silicon oxide film 2 on the substrate 1, an aluminum wiring 3 and a silicon chrome resistor 4 are formed. The thickness of each of these films is 1.0μ, and 500 people are appropriate. Next, a silicon nitride film 5 of about 0.1 μm is deposited on the silicon substrate 1 including the aluminum wiring 3 and the silicon chrome resistor 4 by sputtering using silicon as a target in an argon and nitrogen mixed gas atmosphere. If the silicon nitride film 5 has a thickness of 500 Å or more, it will have the ability to block contaminant ions and moisture, but it may be made thicker than 1.0 μm.

第2図は、本発明の実施例2により作られた半導体装置
の断面図である。第2図の例は、ポリシリ抵抗を有する
半導体装置であって、所望のPN接合(図示せず)、ポ
リシリ抵抗6及びアルミニウム配線3を従来技術で形成
した後、スバ、り法で窒化シリコン5を0.1μ被着し
、更に、プラズマ気相成長法でシリコン酸化膜7を1.
0μ程度被着する。
FIG. 2 is a sectional view of a semiconductor device manufactured according to Example 2 of the present invention. The example shown in FIG. 2 is a semiconductor device having a polysilicon resistor, in which a desired PN junction (not shown), a polysilicon resistor 6 and an aluminum wiring 3 are formed using a conventional technique, and then a silicon nitride layer is formed using a sputtering method. 0.1 μm of silicon oxide film 7 was deposited using plasma vapor deposition method.
Approximately 0μ is deposited.

この例では、汚染物質及び水分の阻止膜としてスパッタ
法による窒化シリコン膜5と、特に樹脂封止の半導体装
置に要求される機械的強度を増加させるためのシリコン
酸化膜7とでパッシベーション膜を構成し、化学的物理
的に優れた半導体装置が得られる。
In this example, the passivation film is composed of a silicon nitride film 5 formed by sputtering as a contaminant and moisture blocking film, and a silicon oxide film 7 for increasing the mechanical strength particularly required for resin-sealed semiconductor devices. Therefore, a chemically and physically excellent semiconductor device can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、パッシベーション膜に、
スパッタ法による窒化シリコン膜を用いることにより、
シリコンクロム抵抗体または多結晶シリコン半導体を含
む半導体装置の特性変動を生じず、歩留の改善、素子特
性の安定化を実現し、同時に耐湿性及び耐温度サイクル
性に優れた半導体装置が得られる効果がある。
As explained above, the present invention provides a passivation film with
By using a silicon nitride film by sputtering,
It is possible to improve yield and stabilize device characteristics without causing characteristic fluctuations in semiconductor devices containing silicon chrome resistors or polycrystalline silicon semiconductors, and at the same time to obtain semiconductor devices with excellent moisture resistance and temperature cycle resistance. effective.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例による半導体装置の断面図、
第2図は本発明の実施例2による半導体装置の断面図で
ある。 1・・・・・・シリコン基L  2,7・・・・・・シ
リコン酸化膜、3・・・・・・アルミ配線、4・・・・
・・シリコンクロム抵抗体層、5・・・・・・スパッタ
法による窒化シリコン膜、6・・・・・・ポリシリコン
抵抗体層。 代理人 弁理士  内 原   音
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention. 1...Silicon base L 2,7...Silicon oxide film, 3...Aluminum wiring, 4...
...Silicon chromium resistor layer, 5...Silicon nitride film by sputtering method, 6...Polysilicon resistor layer. Agent Patent Attorney Oto Uchihara

Claims (1)

【特許請求の範囲】[Claims]  PN接合を有する半導体基板上に多結晶半導体抵抗体
またはシリコンクロム抵抗体などの抵抗体層を形成し、
さらにこの抵抗体層の上をパッシベーション膜で被覆す
ることを含む半導体装置の製造方法において、前記パッ
シベーション膜として窒化シリコン膜をスパッタ法によ
り被着することを特徴とする半導体装置の製造方法。
Forming a resistor layer such as a polycrystalline semiconductor resistor or a silicon chrome resistor on a semiconductor substrate having a PN junction,
The method for manufacturing a semiconductor device further includes covering the resistor layer with a passivation film, the method comprising depositing a silicon nitride film as the passivation film by sputtering.
JP6644488A 1988-03-18 1988-03-18 Manufacture of semiconductor device Pending JPH01238126A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6644488A JPH01238126A (en) 1988-03-18 1988-03-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6644488A JPH01238126A (en) 1988-03-18 1988-03-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH01238126A true JPH01238126A (en) 1989-09-22

Family

ID=13315951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6644488A Pending JPH01238126A (en) 1988-03-18 1988-03-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH01238126A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300461A (en) * 1993-01-25 1994-04-05 Intel Corporation Process for fabricating sealed semiconductor chip using silicon nitride passivation film
EP0682359A1 (en) * 1994-05-09 1995-11-15 International Business Machines Corporation Multilayer gate MOS device
JP2017079254A (en) * 2015-10-20 2017-04-27 新日本無線株式会社 Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300461A (en) * 1993-01-25 1994-04-05 Intel Corporation Process for fabricating sealed semiconductor chip using silicon nitride passivation film
US5742094A (en) * 1993-01-25 1998-04-21 Intel Corporation Sealed semiconductor chip
US5856705A (en) * 1993-01-25 1999-01-05 Intel Corporation Sealed semiconductor chip and process for fabricating sealed semiconductor chip
EP0682359A1 (en) * 1994-05-09 1995-11-15 International Business Machines Corporation Multilayer gate MOS device
US5940725A (en) * 1994-05-09 1999-08-17 International Business Machines Corporation Semiconductor device with non-deposited barrier layer
JP2017079254A (en) * 2015-10-20 2017-04-27 新日本無線株式会社 Semiconductor device

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