JPH01238013A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To establish secure electrical connection with low contact resistance by forming a diffusion layer of high impurity concentration in a predetermined region of a semiconductor substrate, forming wiring metal in a connecting hole which is formed by etching a polycrystalline silicon film and an insulating film formed on the semiconductor substrate, and connecting the diffusion layer and the wiring metal. CONSTITUTION:A diffusion layer 14 is provided by introducing impurity into a semiconductor substrate 12. An insulating layer 16 comprising silicon oxide and the like is formed and a polycrystalline silicon film 18 is formed. A connecting hole 20 is formed by etching the polycrystalline silicon film 18 and the insulating film 16. Then, wiring metal 22 comprising an aluminum silicon alloy containing 0.5-2.0wt.% silicon is formed by a vacuum deposition method and the like, and the wiring pattern 22 is patterned into a predetermined shape by photo-etching and further heat-treated in the atmosphere of hydrogen or nitrogen at 400-500 deg.C. No excessive silicon is separated on the semiconductor substrate 12 in the connecting hole 20 but excessive silicon in the wiring metal 22 is separated on the polycrystalline silicon film 18 to from nodules.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular, a method for manufacturing a semiconductor integrated circuit, in particular a method for manufacturing a semiconductor integrated circuit in which an impurity layer with a high impurity concentration formed on a semiconductor substrate is connected to a wiring metal with low resistance. Regarding.

[Conventional technology and its issues]

A conventional example of connection between an impurity layer and a wiring metal will be explained with reference to FIG.

As shown in FIG. 2(a), impurity ions are introduced into a predetermined region of the semiconductor substrate 120 to form an impurity layer 14. Thereafter, an insulating film 16 made of a silicon oxide film or the like is formed on the entire surface, and an opening is formed in the insulating film 16 by photoetching to form a connection hole 20. Thereafter, a wiring metal 22 made of aluminum is formed and heat treated at a temperature of 400 to 500° C. in a hydrogen or nitrogen atmosphere. In this heat treatment, the natural oxide film formed on the semiconductor substrate 12 in the connection hole 20 is removed by utilizing the H'J film reduction effect of aluminum, and the impurity layer 14 and the wiring metal 22 are removed.
An ohmic contact with low connection resistance can be obtained between the two. However, when pure aluminum is used as the wiring metal 22, this heat treatment causes the silicon of the semiconductor substrate 12 to diffuse into the aluminum as a solid solution, causing the semiconductor substrate 12 to be eaten away, resulting in so-called alloy spikes shown in FIG. 2(a). 26 occurs. When this alloy spike 26 grows large and penetrates the impurity layer 14,
The wiring metal 22 and the semiconductor substrate 12 are short-circuited. Note that the shape of the alloy spike 26 is a conical shape in a silicon substrate with a (100) plane orientation, and a shape with a flat bottom in a (111) silicon substrate.

Therefore, in order to suppress the occurrence of alloy spikes 26, there is a method of pre-containing silicon in aluminum at a concentration higher than the solid solubility limit to form the wiring metal 22. However, in the aforementioned heat treatment at 400 to 500°C in a hydrogen or nitrogen atmosphere, the connection window 20
Using the silicon of the semiconductor substrate 12 inside as a seed crystal, the excess silicon in the wiring metal 22 undergoes solid phase epitaxy/dial growth to form precipitated silicon 28. Since this precipitated silicon 28 is close to an intrinsic semiconductor (has a high specific resistance value), when the precipitated silicon 28 is formed in part or all of the connection hole 20, the contact resistance between the wiring metal 22 and the diffusion layer 14 increases. This may cause electrical connection failure.

It is an object of the present invention to provide a manufacturing method for solving the above problems and connecting a wiring metal and a diffusion layer with low contact resistance.

[Means to solve the problem]

In order to achieve the above object, the wiring metal of the present invention and the diffusion layer are connected by the method described below.

A process of forming a diffusion layer having a high impurity concentration in a predetermined region of a semiconductor substrate, a process of sequentially forming an insulating film and a polycrystalline silicon film on the semiconductor substrate, and a process of forming the polycrystalline silicon film and the insulating film by photoetching. The diffusion layer and the wiring metal are connected through a process of etching to form a connection hole and a process of forming a wiring metal.

〔Example〕

The present invention will be described in detail below using the cross-sectional view shown in FIG. 1 showing a method of connecting a diffusion layer and a wiring metal according to the present invention.

First, an opening is selectively formed in a photoresist or a silicon oxide film, which is a photosensitive resin, and the photoresist or silicon oxide film is used as a mask to form an opening of the same or opposite conductivity type as the semiconductor substrate 12 by ion implantation or the like. Introducing an impurity having a first
A diffusion layer 14 is provided as shown in Figure (a). Thereafter, silicon oxide was formed using a chemical vapor deposition method (hereinafter referred to as CVD method).

Alternatively, the insulating film 16 made of silicon oxide to which phosphorus is added, silicon oxide to which boron is added, or silicon oxide to which phosphorus and boron are added is formed to a thickness of 500 nm.
Form to a certain thickness. Furthermore, a polycrystalline silicon film 18 having a thickness of 2 to 1100 nm is formed on this insulating film 16 by CVD or sputtering.

Next, a photoresist is formed on the entire surface of the semiconductor substrate 12 by a spin coating method or the like, and the photoresist is patterned by exposure and development using a predetermined mask. Using this patterned photoresist as an etching mask, the polycrystalline silicon film 18 and the insulating film 16 are etched to form connection holes 20 as shown in FIG. The diffusion layer 14 may be formed by introducing an impurity into a region aligned with the connection hole 20 using the insulating film 16 as a mask for impurity introduction.

Next, as shown in FIG. 1 (C1), for example, silicon 0.
A wiring metal 22 made of an aluminum silicon alloy containing 5 to 2.0% by weight is formed by a vapor deposition method or a sputtering method. After that, the wiring metal 2 is etched by photo-etching.
2 is patterned into a predetermined shape, and further heat-treated at a temperature of 400 to 500° C. in a hydrogen or nitrogen atmosphere. In this heat treatment, the semiconductor substrate 1 inside the connection hole 20
The excess silicon in the interconnect metal 22 does not precipitate on the polycrystalline silicon film 18, but the excess silicon in the interconnect metal 22 precipitates on the polycrystalline silicon film 18, forming a small lump, so-called silicon nozzle 24. This is due to the effect of the area ratio between the wiring metal 22 on the connection hole 2o and the wiring metal 22 on the polycrystalline silicon film 18. This is because excess silicon in the wiring metal 22 is not deposited, but on the polycrystalline silicon film 18 having a large surface roughness.

FIG. 3 shows the relationship between the size of the connecting hole and the maximum diameter of precipitated silicon deposited by solid phase epitaxial growth in the connecting hole in the manufacturing method of the present invention.

After depositing polycrystalline silicon with a thickness of 3 Qnm on the insulating film,
A connection hole having a size of 0.8 to 5 μm is formed, and then a wiring metal made of an aluminum silicon alloy containing 1% silicon by market weight is formed, and the wiring metal is etched into a predetermined pattern. , and further at a temperature of 425°C in a hydrogen atmosphere.
A sample was prepared by performing a heat treatment for 30 minutes. Thereafter, the wiring metal was peeled off, and the maximum diameter of the deposited silicon on the surface of the semiconductor substrate within the connection hole was measured. The graph in FIG. 3 shows the maximum value measured on a plurality of semiconductor substrates for 100 connection windows of each size.

As is clear from Figure 3, in connection holes with a size of 1.5 μm or less, no precipitated silicon is generated (not observed).On the other hand, in connection holes with a size of 2 μm or more, no precipitated silicon is generated due to solid phase epitaxial growth. However, the area ratio of the precipitated silicon area to the connection hole area is less than 10%, and the connection between the diffusion layer and the wiring metal is made with a sufficiently low contact resistance.Furthermore, the precipitated silicon occurs in the fine connection hole. The fact that this is not observed supports the correlation between the area ratio of the wiring metal on the connection hole and the wiring metal on the polycrystalline silicon film and the occurrence of silicon precipitation.

〔Effect of the invention〕

As is clear from the above explanation, the silicon contained in the wiring metal made of aluminum-silicon alloy in an amount exceeding the solid solubility limit does not precipitate on the semiconductor substrate in the micro-sized connection holes, so the wiring metal and the diffusion layer A reliable electrical connection can be made with low contact resistance.

[Brief explanation of the drawing]

FIGS. 1A and 1B are cross-sectional views showing a manufacturing method for connecting a wiring metal and a diffusion layer in the present invention. Figures 2 (a) and [b] are cross-sectional views for explaining the problems between the wiring metal and the diffusion layer in the conventional example, and Figure 3 shows the size of the connection hole and the solid phase in the connection hole in the manufacturing method of the present invention. It is a graph showing the relationship between the maximum diameter of precipitated silicon that is epitaxially grown and precipitated. 14... Diffusion layer, 16... Insulating film, 18... Polycrystalline silicon film, 20... Connection hole, 22... Wiring metal. Figure 1 (a) (b) (C) 14, Fox Salvation 16, Life Color Shuhen and Moon Smell 18, % Kiyoshi Akashi, Sokonru tip 22, West Spirit Metal

Claims (1)

[Claims] a step of forming a diffusion layer having a high impurity concentration in a predetermined region of a semiconductor substrate; a step of forming an insulating film on the semiconductor substrate; a step of forming a polycrystalline silicon film on the insulating film; and a step of forming a polycrystalline silicon film on the insulating film. etching the polycrystalline silicon film and the insulating film to form a connection hole;
1. A method for manufacturing a semiconductor integrated circuit, comprising the step of forming wiring metal.