JPH01238000A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Previous Requirements] With respect to semiconductor memory devices, the purpose of this invention is to accurately detect intermediate defective products in the next test of memory elements. In a configuration in which a memory cell is arranged at each intersection of a bit line connected to a line via a pull-up transistor and led out to a sense amplifier via a data transfer transistor, and a word line that intersects the bit line. , a pull-up transistor different from the pull-up transistor is disposed between the power supply line and the bit line, a pull-down transistor is disposed between the bit line and ground, and the pull-up transistor and the pull-down A configuration is adopted in which signal lines for supplying signals for making each transistor conductive are led out to respective corresponding bonding bands.

[Industrial application field]

The present invention relates to a semiconductor memory device.

[Conventional technology]

Recent memory devices have become larger in capacity, and there is a trend in which subsequent tests (tests for classifying good/defective products on a wafer) require a very long time.

However, due to the manufacturing process, it is not possible to spend a long time on testing.
Therefore, we have no choice but to simplify the test and make it less time consuming.

FIG. 2 is a circuit diagram showing the structure of an SRAM (static RAM), and the problems of the above-mentioned - next test will be explained with reference to this diagram.

The part indicated by code 1 in the center of the figure is one cell,
This corresponds to 1 bit. Q1 and Q2 are bit lines BL
, a pull-up transistor that pulls up BL, WL
CD is a word line that selects a row decoded from a row address (Ro-Address), and CD is a column line that selects a digit (Column) decoded from a digit address (Column Address).

Transistor Q5 of this digit line CD. Through Q6, the cell information passes through the pass lines 3 and B, enters the sense amplifier S, and is then taken out as an output.

In the circuit with the above configuration, reading is performed when the word line WL is "H".The potentials of the bit lines BL and BL are approximately Vcc/2, and the content of cell 1 is "H". The potential of both is slightly "H" or "L" depending on whether it is "H" or "L".

, and a potential difference is created between BL and BL.

At this time, if the levels of BL and BL are too low, it will be similar to writing "L' into the cell. If it is too high, it will be difficult to create a potential difference on the bit line because the cell is small, and reading will be delayed.

Therefore, during design, care must be taken to find the best point for the bit line potential. In other words, if the level of the bit line shifts, the load on the cell increases, and weak cells may suffer from malfunctions such as being unable to read data.

If the cell is clearly defective, it can be easily detected;
In order to detect cells that are on the verge of failure, efforts are being made to eliminate defects by conducting tests with devised cell data and addressing.

[Problem to be solved by the invention]

Therefore, if the primary test is simplified, defective cells that are close to the passing line will not be detected and will be sent to the final test.
Since this results in a failure in the final test, there is a problem in that the yield in the final test (test after assembly and before shipment) decreases.

Therefore, it is desired to be able to perform an accurate and efficient primary test.

An object of the present invention is to enable intermediate defective products to be accurately detected in a primary test of a memory element.

[Means to solve the problem]

The present invention makes it easy to solve subtle defects in the circuits surrounding the cells by installing a means for forcibly pulling up or pulling down the bit lines BL and BL' only during the next test. The power supply line 2 that supplies the power supply voltage Vcc and the pin I/wires BL and B
A pull-up transistor Q3. Q4 is connected to the bit line BL, and pull-down transistors Q7. QB, and the pull-up transistor Q3. Q4 and pull-down transistor Q7. Signal lines for supplying signals to Q8 are led out to corresponding pads P1 and P2, respectively.

[For production]

During the primary test, by applying a voltage to band P1 or P2, the potential of bit lines BL and D can be lowered by 2' without changing Vcc.
A wide variety of test conditions can be realized, and even more severe test conditions can be added to perform the primary test without taking much time.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

FIG. 2 is a diagram showing the configuration of one embodiment of the present invention.
The same parts as in the figures are indicated by the same reference numerals. The semiconductor memory device of the present embodiment has a conventional configuration in which a pull-up transistor Q3. Write Q4 on Mata'=
Pull-down transistors Q7 and QB are provided between the output and the ground, and the pull-down transistors Q3. The gate of Q4 is connected to the bonding pad PL, and the pull-down transistor Q7. QB
The gate is also led out to the bonding pad P2.

With this configuration of this embodiment, when performing the next test, voltages are applied to pads Pi and P2, respectively, and bit lines BL and BL are pulled up or down, respectively, thereby detecting defective products. Detection power can be increased.

The operation during the test will be explained below.

- In this embodiment configured as described above, the pad P
By applying a voltage to pull-up transistor Q3. By making Q4 conductive, the potential of the pinto lines BL, BL can be raised, and by applying a voltage to the pad P2, the pull-down transistors Q7. By making QB conductive, the potentials of the pin 1- lines BL and BL can be lowered.

Using this, Bad P1 and Bad P during the first exam
By applying a voltage to 2, it is possible to raise and lower the potential of the bit lines BL and BL in addition to the normal - test conditions. It is possible to accurately detect items that are just close to the pass line, which would become defective if the voltage fluctuated.

As described above, in this embodiment, bit lines BI1. By arbitrarily raising or lowering the potential of BL from the level set at the time of design, it is possible to perform the primary test at a level that is more severe than usual, and defective products can be effectively removed.

During assembly, pads P1 and P2 are connected to ground potential, and pull-up transistors Q3, Q4 and pull-down transistors Q7, . By turning off Q8, there is no adverse effect on the operation during actual use.

Conventionally, the bit line BL was set by increasing or decreasing Vcc.
, B were tested by changing the potentials, so the potentials of the bit lines BL, BL varied in proportion to Vcc, but in this example, Vcc was high and the potentials of the bit lines BL, BL changed in proportion to Vcc. V in a state such as low or the opposite state, etc.
It has the advantage that it is possible to create a state that is not proportional to cc, and that the primary test can be performed under various test conditions that may occur during actual use.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to increase the detection rate of defective products in the primary test with a simple structure.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing problems of the conventional technology. In the figure, 1 is a cell, Q3. Q4 is a pull-up transistor, Q7. QB is a pull-down transistor, BL,
BL is the bit line.
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Claims (1)

[Claims] Connected to a power supply line (2) that supplies a power supply voltage (V_C_C) via pull-up transistors (Q1, Q2), and connected to a sense amplifier (S) via data transfer transistors (Q5, Q6). The bit line (BL
, ■) and a word line (WL) that intersects the bit line. Pull-up transistors (Q3, Q4) different from the pull-up transistors (Q1, Q2) are arranged between the bit lines, and pull-down transistors (Q7, Q8) are arranged between the bit lines and the ground. , characterized in that signal lines for supplying signals for rendering the pull-up transistors (Q3, Q4) and the pull-down transistors (Q7, Q8) conductive are led to corresponding pads (P1, P2), respectively. semiconductor storage device.