JPH01237734A - Duplexing device - Google Patents

Abstract

PURPOSE:To enable collating the contents of data from a main storage without damaging the processing ability of an information processor by activating the collating timing of the duplexed main storage device by utilizing a refresh timing. CONSTITUTION:An address/data output circuit (MATT) 220 for discordance detection of a 0-system sets the refresh (RFL) timing and an address A is generated from the counter of the circuit 220 at the time of the RFL and supplied to a DRAM element 210. Thus, data D is read from the element 210 and sent to a main storage 21 of a 1-system through the circuit 220. On the other hand, the RFL timing is set in the main storage device 21 of the 1-system and the same address as a main storage device 20 of the 0-system is generated by the activation of RFL operation in an MATR 230 and the data D is read from a DRAM element 211 of its own system and sent through the MATT 221 to the MATR 231. When the discordance between both data D is detected in the circuit 231, the discordance is informed to the CPU 10 of the 0-system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and more particularly to a duplication device for verifying the contents of a duplexed main memory device.

[Conventional technology]

There has conventionally been a duplication device in which main storage devices are duplicated, a central control unit writes data to these two main storage devices, and when reading data, collates the contents read from these main storage devices. In such duplexing devices, access to these main storage devices is stopped when a discrepancy in the contents of the dual storage devices is detected.

[Problem to be solved by the invention]

Therefore, although such conventional duplexing devices ensure data reliability, the waiting time of the central control device becomes long, which causes a decline in the performance of the information processing device.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a duplication device that does not reduce the processing capacity of an information processing device.

[Means to solve the problem]

In the present invention, two main storage systems and a central control unit are prepared, and when the central control unit of one system operates, data is written to the main storage systems of both systems, and when the central control unit reads data, In a duplex information processing device that reads data from these main storage devices, (i) refresh means for refreshing memory elements consisting of dynamic RAM arranged in the main storage devices of both systems, and (ll) A check address generating means that generates a check address in the main memory devices of both systems; (iv) data transmitting/receiving means for transmitting and receiving the data read by the data reading means and its address between the main storage devices of both systems; (■)
The duplexing device is provided with a mismatch detection means for comparing the data read in the other system at the received address and the data read by the own system at the address to detect a mismatch.

That is, in the present invention, the refresh timing is used to activate the verification timing of the duplicated main storage device. Therefore, the free time of the main storage device is effectively utilized, and the contents of data read from the duplicated main storage devices can be collated without impairing the processing capacity of the information processing device.

〔Example〕

The present invention will be described in detail below with reference to Examples.

FIG. 1 shows an outline of an information processing device to which a duplication device of the present invention is applied.

This information processing device has two central control units (CPUs) 10 and 11 for redundancy, and two main storage devices (
MM) 20.21.

For convenience, one system consisting of the central control device 10 and the main storage device 20 is called the 0 system, and the central control device 11 and the main storage device 2
For convenience, the other system consisting of 1 will be referred to as 1 system.

Now, between the 0-system central controller IO and the main storage device 20 is 1. They are connected by an address/data bus 30. An address/data bus 31 connects the central control unit 11 of the first system and the main storage unit 21 . Main note of 0 series 1. !
An address/data bus 32 is connected between the device 20 and the main storage device 21 of the first system to copy data. 1 system central control unit 11 and 0 system main storage device 20
A mismatch report signal line 40 is connected between the two main storage devices 20 and 21 in order to report a mismatch between the contents read from the two main storage devices 20 and 21. The central control unit 10 of the 0 system and the main controller 1 of the 1 system. A discrepancy report signal line 41 is connected between the α units 21 and 21 to report a discrepancy between the contents read from the two main storage devices 20 and 21.

FIG. 2 specifically shows the inside of a 0-system main storage device as an example.

The 0-system main memory device 20 includes a memory access receiving circuit 200 that receives a memory access signal sent from the 0-system central control unit 10 (FIG. 1) via an address/data bus 30.

The data output from this memory access receiving circuit 200 is stored in a DRAM (dynamic random access memory).
In addition to being written to the memory (memory) element (MEM) 210, the data is also output directly to the address/data bus 32, so that data with the same content is supplied to the main 21.0 device 21 of the 1st system as shown in FIG. It has become.

The 0-system main memory 20 contains a mismatch detection address/
Data output circuit (MATR) 220 and mismatch detection address/data reception and mismatch detection circuit (MATR)
230 is also arranged.

FIG. 3 is for explaining the data copying operation in such a duplexing device.

Now, from the D system CPU 10 to the address/data bus 30
It is assumed that a write instruction is also issued to the O-system main storage device 20 via the O-system main storage device 20. This -1! The f write instruction is transmitted to the main storage device 21 of the first system via the memory access receiving circuit 200 and the address/data bus 32. As a result, the same data is written to the same address of each DRΔM element 210, 211 in both the main memory A, α device 20, and SIL.

FIG. 4 is for explaining the fresh timing of this duplexing device.

The DRΔM elements 210 and 211 of both systems are elements that store information to be stored in the form of charges, so they must be refreshed at regular intervals in order to retain information.

During the refresh period, the central controller 1
As described above, access from 0 or 11 is stopped.

In the duplication device of this embodiment, the DRAM elements 210, 21
During the period when 1 is refreshed, 1 data is read and sent to the other system. In the other system as well, the time for refreshing and the time at which data at the corresponding address is read are matched, and it is detected whether the read data and the transferred data match or not. If there is a discrepancy, this will be reported.

The refresh operation outlined above will be specifically explained in conjunction with FIG. 5.

The 0-system mismatch detection address/data output circuit 220 sets the refresh timing.
), address A is generated from the counter of the address/data output circuit 220 for mismatch detection at the time of refreshing (
In step (2), this is supplied to the DRAM element 210 of the system. As a result, output data D is read from the DRAM element 210 (step ■), and the contents are read out from the DRAM element 210 as 1 through the address/data output circuit 220 for detecting mismatch.
The data is sent to the main memory 21 of the system (step ■).

On the other hand, in the ■ system main storage device 21, the 0 system main storage device 2
At the same time as 0, the refresh timing is set (step ■). Then, by starting the refresh operation, 0
Address A, which is the same as the main memory 20 of the system, is the address for mismatch detection/data reception and mismatch detection circuit (MATR).
) 231, the step ■) of your own system “D R
Data D is read from the A young element 211 (step 2). This read data Di is sent to the mismatch detection address/data output circuit 221 and the mismatch detection address/data reception and mismatch detection circuit 231.
(Step ■).

Since the O-system output data D explained in step (2) above is transferred to the address/data reception and mismatch detection circuit 231 for mismatch detection, this circuit 231 receives both data D.

It is detected whether there is a mismatch in D (step ■). As a result, if there is a mismatch between data D and D, that is, if an error exists (step ■;
Y), a mismatch is reported to the 0-system CPU 10 via the mismatch report signal line 41 (step 0).
It turns out.

Note that in the above explanation, detailed explanations of the synchronization method during refresh and the method of reading the same data in both systems have been omitted. These can be realized using already existing technologies. For example, address/data reception and mismatch detection circuits 230, 231+, :D for detecting mismatch in both systems.
Counters with the address width of RAM elements 210 and 211 are prepared, and the same clock signal is manually input, and the counters of both systems are simultaneously run at the same determined timing.

All you have to do is set it.

〔Effect of the invention〕

As described above, according to the present invention, the refresh timing is used to activate the collation timing of the duplicated main storage device! With this, data inconsistency can be detected using the free time of the main storage device, and the central control device does not require any additional waiting time. Therefore, it is possible to check the contents of the duplicated main storage devices without impairing the processing capacity of the information processing device.

[Brief explanation of the drawing]

The drawings are for explaining one embodiment of the present invention, of which FIG. 1 is a block diagram showing an overview of the information processing device, FIG. 2 is a block diagram showing the configuration of the main storage device, and FIG. 0
Figure 4 is a block diagram showing the configuration of the main parts of the duplexing device to explain how data is stored from the central control unit of the system to the main memory of both systems. FIG. 5 is a block diagram showing the configuration of the main parts of the duplexing device for explaining how data mismatch is detected during freshening. 10...0 system central control unit, 11...
・1 system central control unit, 20...0 system main memory, 21...1 system main memory, 32...address/data bus, 40. 41・
...Discrepancy report signal line, 200...
Memory access receiving circuit, 220.221...
Address/data output circuit for mismatch detection, 230.231...Address/data reception and mismatch detection circuit for mismatch detection. Applicant: NEC Corporation Representative

Claims (1)

[Claims] Two systems of main storage devices and central control devices are prepared, and when the central control device of one system operates, data is written to the main storage devices of both systems, and the data of the central control device is In a duplex information processing device that reads data from these main memories at the time of reading, there is provided a refresh means for refreshing a memory element consisting of a dynamic RAM arranged in each of the main memories of both systems; Check address generation means for generating a check address in a main memory; and data for reading data corresponding to the address generated by the check address generation means using the refresh time of the memory element by the refresh means. reading means; data transmitting/receiving means for transmitting and receiving the data read by the data reading means and its address between the main storage devices of both systems; What is claimed is: 1. A duplication device comprising: a mismatch detection means for comparing data and detecting mismatch.