JPH01235483A - Image enlargement processing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to devices that handle digitized video signals, such as color televisions, VTRs (video tape recorders), video printers, and image transmission devices. The present invention relates to an image enlargement processing circuit for enlarging and displaying an image obtained by the video signal.

[Conventional technology]

With the development of digital signal processing technology and the development of high-speed, large-capacity devices, home electronic products such as color televisions are being digitized. In products such as color televisions and VTRs, functions such as screen freezing (still image display), parent-child two-screen display, and multi-channel (simultaneous display of multiple screens) have already been realized using digital memory.

On the other hand, a possible next step to these functions is the enlarged display of images. In addition to enlarging the details of an image, you can also display it on a large screen by lining up several TVs. A conventional image enlargement display method will be described below.

FIG. 13 is an explanatory diagram for explaining the conventional image enlargement display method, in which each scanning line is viewed from the horizontal direction of the television screen, with the time axis as the horizontal axis and the vertical direction of the television screen as the vertical axis. This is a diagram. Note that the circles indicate scanning lines.

The structure of a general interlaced video signal is as shown in FIG. 13(a). In order to enlarge and display an image obtained by this interlace video signal, for example, by 2 times, the information of the following fields is written into memory once, and when read out, the reading speed corresponding to the vertical and horizontal directions of the TV screen is set. can be read at half the write speed. That is, the vertical direction is 1
The same line is read out twice line by line, and read out in the horizontal direction according to a clock having half the frequency of the writing clock.

The result of this operation in the vertical direction is shown in Figure 13(b).
It will look like this. That is, as shown in FIG. 13(b), each of the first field and the second field is enlarged twice in the vertical direction. However, when the first field and the second field are displayed alternately, the vertical relationship is reversed in the scanning line indicated by the arrow, and the scanning line structure is disturbed, so that a perfect enlarged display cannot be obtained.

Therefore, as shown in FIG. 13(C), the first field,
It is conceivable to display the same signal in both the second field to prevent disturbances in the scanning line structure.

Furthermore, as another method, disturbances in the scanning line structure can be prevented by displaying only one field (for example, only the first field).

However, in this case, screen flickering occurs, which poses a problem.

The above discussion is based on the case of standard speed display (such as when displaying on a television with standard speed playback), but similar problems arise when displaying at double speed (for example, JP-A-58-20
This problem also occurs in cases where interlaced scanning is converted to 11th scanning and displayed on a double-speed playback television as described in Japanese Patent No. 5377.

Like FIG. 13, FIG. 14 is an explanatory diagram for explaining the conventional image enlargement method.

When an interlaced video signal as shown in FIG. 14(a) is doubled by interpolating the interpolated scanning line signal with the information of the previous field, and the resulting image is enlarged and displayed, The result will be as shown in Figure 14(b).

In other words, in the case of double-speed display, as in the case of standard-speed display, if the same line is read twice each line in order to double the vertical magnification, the result will be as shown in Figure 14(b). Moreover, the upper and lower scanning lines are reversed every two scanning lines, which disrupts the scanning line structure and results in an incorrectly enlarged display screen, which is a major problem.

For example, there is a proposed example described in Japanese Patent Laid-Open No. 61-149987 that solves the above-mentioned problem of disturbance in the scanning line structure. However, in this proposed example, when there is movement in the enlarged image, has a new problem of being displayed as a double image. That is, in this alternative example, the image before l field and the image of the current field are displayed on the screen at the same time, so if there is movement in the images, the shifted images will be displayed at the same time, and as a result, This results in a double image being displayed.

[Problems to be Solved by the Invention] As described above, when obtaining an image enlarged from an interlaced video signal, when writing and reading the video signal to a memory, simply write the same line one line at a time in the vertical direction N
In the method of reading out times at a time and reading out in the horizontal direction according to a clock with a frequency of 1/H of the clock at the time of writing, in both standard speed display and double speed display,
There was a problem in that the scanning line structure was disturbed and a high-quality enlarged image could not be obtained. Further, even in the previously proposed examples that solved the problem of such a disordered scanning line structure, there was a problem in that if there was movement in the image to be enlarged, a double image would be displayed.

Furthermore, the above problem occurs not only when obtaining an image enlarged from an interlaced video signal, but also when obtaining an image enlarged from a non-interlaced video signal.

The purpose of the present invention is to solve the problems of the prior art described above,
In particular, in the case of double-speed display, when obtaining an enlarged image from an interlaced or non-interlaced video signal, it is difficult to obtain a high-quality enlarged image without disturbing the scanning line structure or producing double images. The object of the present invention is to provide an image enlargement processing circuit that can perform image enlargement processing.

[Means to solve the problem]

In order to achieve the above-mentioned object, the present invention provides a real/interpolated scanning line signal generation means for generating an actual scanning line signal and an interpolated scanning line signal from an input video signal, and and an interpolated scanning line signal, respectively, and generate a write address and a read address for the first buffer memory and a write address and a read address for the second buffer memory, respectively. The first and second address generating means input the actual scanning line signal and the interpolated scanning line signal respectively read from the first and second buffer memories, double the frequency of each signal, and output the signal. a double speed conversion memory; a switch means for inputting an actual scanning line signal and an interpolated scanning line signal outputted from the double speed conversion memory and selectively outputting one of them by switching a switch; image enlargement on the video signal; When processing and displaying an enlarged image on the screen, the first and second address generation means are set such that the read address generation period in the vertical direction of the screen is equal to the write address generation period in the vertical direction of the screen. Control so that it is multiplied by N (N is an arbitrary number),
The switch means is configured to include an enlargement control means for controlling the switching order of the switches in the switch means to be changed between an odd field period and an even field period of the video signal.

[Effect]

The actual/interpolated scanning line signal generating means performs motion-adaptive scanning line interpolation processing on the inputted video signal such as a color television signal, so that the actual/interpolated scanning line signal generation means sequentially generates a motion that does not cause double images for each field. Actual scanning line signals and interpolated scanning line signals for performing scanning can be created. next,
These two scanning line signals are stored in the first and second buffer memories, respectively, and the first and second address generation means are used to enlarge the image in the vertical direction of the screen. Read addresses are generated and supplied to the first and second buffer memories so that the generation cycle of read addresses in the vertical direction of the screen is N times longer than the generation cycle of write addresses. Thereby, an actual scanning line signal and an interpolated scanning line signal which have been subjected to image enlargement processing are read out from the first and second buffer memories, respectively, and supplied to the switching means via the double speed conversion memory. Ru. The switch means selectively switches and outputs the two inputted scanning line signals, and at this time, the expansion control means controls the switching order so that the odd field period and the even field period have different switching orders. . As a result, a high-quality enlarged image can be obtained in both odd-numbered fields and even-numbered fields without the vertical relationship of the scanning lines being reversed and the scanning line structure being disturbed.

〔Example〕

A first embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, Lot is an input terminal for an interlaced video signal, 102 is an output terminal for a double-speed converted video signal, and 103 is a real/interpolated scanning line signal generator for creating an actual scanning line signal α and an interpolated scanning line signal β. A circuit 104 is a first buffer memory 105 for temporarily storing the actual scanning line signal α.
106, 107 are the second buffer memories for temporarily storing the interpolated scanning line signal β; The first . second write address generator, 1
08,109 is the above-mentioned No. 1. Second buffer memory 104
, 105, a read address generator that provides a read address (read address); 110, a double-speed conversion memory for double-speed conversion; 112 is an enlargement control circuit that generates each control signal, and 113 is an enlargement control switch.

Below, the operation of this embodiment will be explained first at the time of enlargement (i.e.,
The operation during enlarged display will be explained in detail, and then the operation during normal operation (that is, when enlarged display is not carried out) will be briefly explained.

To simplify the explanation of the operation during enlargement, here, we will explain the case where an image of 1/4 of the screen is enlarged to double both vertically and horizontally, that is, the case shown in Fig. 2 (a). The second image of the part
Consider the case where the image is enlarged and displayed as shown in Figure (b).

In FIG. 1, when enlarging, first, enlarge control switch 1
13 is turned on, and the control operation of the enlargement control circuit 112 is switched to the control operation during enlargement.

On the other hand, the real/interpolated scanning line signal generation circuit 103 generates an actual scanning line signal α and an interpolated scanning line signal β from the interlaced video signal inputted from the input terminal 101, and outputs them to the first buffer memory 104 and the interpolated scanning line signal β, respectively. The data is output to the buffer memory 105 of No. 2.

FIG. 3 is an explanatory diagram showing a write address generated from the write address generator and a read address generated from the read address generator when enlarged in FIG. 1. In addition, in FIG. 3, the first and second buffer memories 104
, 105 has a capacity of one field,
In addition, writing/reading can be performed asynchronously.

1st. The second write address generators 106 and 107 generate the first write address as shown in FIG. 3(a). It is output to second buffer memories 104 and 105.

As a result, 1. Second buffer memory 104.10
5, the actual scanning line signal α and the interpolated scanning line signal β output from the actual/interpolated scanning line signal generation circuit 103 are each 1.
One field is sequentially written to the address indicated by the write address according to write clocks W, CLK1.W, CLK2 of a constant frequency, for example, 4 fsc (f3 (: color subcarrier frequency)).

On the other hand, as described above, when the control operation of the enlargement control circuit 112 is switched to the control operation during enlargement, the enlargement control circuit 112 starts the first. The second read address generators 108 and 109 each receive a control signal indicating that it is time to expand, and a signal indicating whether the input video signal is the first field or the second field (more - boat fishing). In other words, it outputs a signal indicating whether the field is an odd field or an even field. Furthermore, the latter signal is
Field signal o d input to enlargement control circuit 112
It is output based on d/e v e n.

In response to the above control signals, the first. In the second read address generators 108 and 109, the enlarged position on the screen (i.e.
(which part of the screen you want to enlarge).

and the video signal field, determine the read start address, and then repeatedly output the same read address twice to double the horizontal magnification, and further double the vertical magnification. 2 same lines
Repeatedly output each time.

That is, in this embodiment, the enlarged position in the screen is the part shown in FIG. 2(a), so the first
In the field, the read start address is set to zero,
1st. The second read address generators 108 and 109 sequentially generate read addresses as shown in FIG. 3(b).
．． It is output to second buffer memories 104 and 105.

However, in the second field, from the first read address generator 108 to the first buffer memory 104, the first
As with the field, the read start address is set to zero, and read addresses as shown in FIG. 3(b) are sequentially output. By shifting 1 from zero, read addresses as shown in FIG. 3(C) are sequentially output.

Therefore, in the first buffer memory 104, the written actual scanning line signal α is read out from the address indicated by the read address in FIG. 3(b) in accordance with the read clocks R and CLK1 in both the l-th field and the second field. However, in the second buffer memory 105, the first field is written from the address indicated by the read address in FIG. 3(b), and the second field is written from the address indicated by the read address in FIG. 3(C). Interpolated scanning line signal β is read out according to read clocks R and CLK2.

Through the above steps, a signal that has been subjected to image enlargement processing for enlarging the image twice in the horizontal and vertical directions is obtained.

Next, the actual scanning line signal α and the interpolated scanning line signal β subjected to the image enlargement process are input to the double speed conversion memory 110,
A double-speed converted actual scanning line signal α and an interpolated scanning line signal β are generated.

Here, the double speed conversion memory 110 is asynchronous, and its read clock R, CLK3 is the write clock W, CLK3.
The frequency is twice that of LK3.

That is, the double speed conversion memory 110 converts the inputted actual scanning line signal α and interpolated scanning line signal β to a constant frequency, for example, 4f5. are written with write clocks W and CLK3, respectively, and the written actual scanning line signal α
and interpolated scanning line signal β, write clock W, CLK3
By reading with the read clock R, CLK3 having twice the frequency (that is, 8 fsc in this example), it is possible to obtain the double-speed converted actual scanning line signal α and interpolated scanning line signal β.

Next, the double-speed converted actual scanning line signal α and interpolated scanning line signal β are input to the switch circuit 111, respectively.

Here, the switch circuit 111 is switched as follows by a control signal from an enlargement control circuit 112 that performs a control operation during enlargement.

FIG. 4 is an explanatory diagram for explaining the operation during enlargement in FIG. 1.

How to read Figure 4 will be explained.

In Figure 4, (a) indicates the vertical line number, (b)
1 shows the contents of an actual scanning line signal (actual signal) and an interpolated scanning line signal (interpolation signal) output from the actual/interpolated scanning line signal generating circuit 103 in FIG. 1, respectively.

That is, since the video signal input to the input terminal 101 in FIG. 1 is an interlaced video signal, the actual scanning lines ■, ■, ■, etc. of the television screen 200 shown at the left end of FIG.
・In contrast, the vertical line numbers are shifted by one scanning line between the first and second fields, and in the first field, the actual scanning line signals R,, R, . , ■, ... and the interpolated scanning line signal ro+rl
+...corresponds to even-numbered scanning lines ■, ■,..., and in the second field, the actual scanning line signal rO+
rl+ ... corresponds to the even-numbered scanning lines ■, ■, ..., and the interpolated scanning line signals R,, R,, ... correspond to the odd-numbered scanning lines ■, ■, ... .

In addition, (C) is 1. in FIG. The outputs of the second buffer memories 104 and 105 are shown, respectively. The left side of the broken line in the middle is the output of the first buffer memory 104, and the right side is the output of the second buffer memory 105.

That is, as described above, in the first field, the first . The read addresses of both the second buffer memories 104 and 105 are as shown in FIG. 3(b), so Ro is read from the first buffer memory 104.

Ro, R,, R, . . . are the second buffer memory 1
From 05, ro l ro, rl + rl +
... are output respectively, and in the second field, the read address of the first buffer memory 104 is as shown in FIG.
Since the read address of 05 is as shown in FIG. 3(C), the first buffer memory 104 is ro r
ro + rl r rl + . . . from the second buffer memory 105 are R,, R,, R,, R,.

R2, . . . are output respectively. Furthermore, here, the fourth
The vertical line numbers shown in Figure (a) are 1st. This corresponds to the vertical address (address in the vertical direction) of the second buffer memories 104 and 105.

In other words, the first. The output from the second buffer memory 1o4°105 is that in the first field, both the actual scanning line signal and the interpolated scanning line signal are read twice from the 0th line, while in the second field, the actual scanning line signal is read out from the 0th line. Each line is read out twice, and the interpolated scanning line signal is read out one line before the actual scanning line signal.

Further, (d) shows the switching method of the switch in the switch circuit 111 shown in FIG. 1, and (e) shows the method of switching the switch in the switch circuit 111 shown in FIG.
The double-speed converted video signal (double-speed output) output to
are shown respectively. In (d), "actual" indicates selecting the upper side (i.e., the actual scanning line signal α side) of the switch circuit 111, and "auxiliary J" indicates selecting the lower side (i.e., the interpolated scanning line signal β side). ing.

In the switch circuit ill of FIG. 1, the enlargement control circuit 112
As shown in FIG. 4(d), the switch is changed every double-speed line (that is, every cycle of the double-speed horizontal synchronizing signal 2fll). That is, in the first field, the actual scanning line signal α is selected for standard speed even lines (when the vertical line number is even), and the interpolated scanning line signal β is selected for odd lines (when the vertical line number is odd). On the other hand, the second
In the field, even-numbered lines at standard speed are interpolated scanning line signals β
.

The actual scanning line signal α is selected in this order, and for odd lines, the actual scanning line signal α and the interpolated scanning line signal β are selected in this order.

In other words, in the first field, for each double-speed line, real, real, complementary, complementary, real, real, etc., and in the second field, complementary, real, real, complementary, complementary, etc. .

In fact, I flip the switch as if to say...

By switching the switch of the switch circuit 111 in this way, the output terminal 102 receives the double-speed converted video signal as RO+ RO+ r O+ rO+ R1+R+ in the first field, as shown in FIG. 4(e).
,”, but in the second field Ro + r O+
r O+R1+R1+'l+ . . . are respectively output.

The video signal thus obtained at the output terminal 102 is input to a double-speed monitor (not shown), where an enlarged image is displayed.

As described above, according to the present embodiment, the video signal obtained at the output terminal 102 shown in FIG. 4(e) and the scanning lines ■, ■, ■、・
As you can see from the correspondence with ..., the scanning lines ■, ■,
For ■, ■, ■, ■, ..., the video signal is R,, R,, r,, r, in both the first field and the second field.
,R,,R,.

..., and the vertical relationship between scanning lines is not reversed and the scanning line structure is not disturbed as in the conventional case, so it is possible to obtain a high-quality enlarged image.

Also, 1st. Second read address generator 108.10
By freely setting the above-mentioned readout start address in 9, it is possible to enlarge an image at an arbitrary position on the screen (for example, the screen shown in FIG. 2(a), etc.).

The above is the operation during enlargement in this embodiment.

On the other hand, during normal times (that is, when no enlarged display is performed), the enlargement control switch 113 is turned off and the control operation of the enlargement control circuit 112 is switched to the normal control operation.

When the control operation of the enlargement control circuit 112 switches to the normal control operation, the enlargement control circuit 112 notifies the first and second read address generators 108 and 109 of the normal operation as control signals. A signal is output.

In response to this, the first. Second read address generator 10
8 and 109, the third address is used as the read address, respectively.
An address similar to the write address shown in Figure (a) is output.

In addition, the switch circuit 111 controls the actual scanning line for each line at double speed (that is, for each period of the horizontal synchronization signal 2fo at double speed) according to the control signal from the enlargement control circuit 112 that performs control operations in normal operation. The switch is changed so that the signal α and the interpolated scanning line signal β are outputted alternately, that is, real, complementary, real, complementary, . . . .

As a result of the above-described operation, a normal double-speed converted video signal is output from the output terminal 112.

As described above, in this embodiment, in order to perform double speed conversion, an actual scanning line signal and an interpolated scanning line signal are respectively created, and the selection order of the actual scanning line signal and interpolated scanning line signal is determined depending on the incoming field. By changing the , it is possible to reproduce high-quality enlarged images.

Figure 5 shows the real/interpolated scanning line signal generation circuit 1 in Figure 1.
FIG. 2 is a block diagram showing the configuration of 03 in detail.

In FIG. 5, 702 is a frame memory that delays the input signal by one frame, and 703 is a frame memory 7.
A motion detection circuit 704 detects the movement of an image using the input/output signals of the motion detection circuit 703, and a motion adaptive Y signal separates the luminance signal/chrominance signal (hereinafter referred to as Y/C) according to the motion signal from the motion detection circuit 703. /C separation circuit; 705 is a field memory that delays the output signal of the motion adaptive Y/C separation circuit 704 by one field; 706 is a field memory for delaying the output signal of the motion adaptive Y/C separation circuit 704;
This is a motion-adaptive scanning line interpolation circuit that creates an interpolated scanning line signal according to the motion signal from the motion detection circuit 703 from the output signals of the /C separation circuit 704 and the field memory 705, and is otherwise the same as in FIG. It is.

A color television signal is input to the input terminal 101 as an interlaced video signal.

The motion detection circuit 703 uses the input/output signals of the frame memory 702 to determine whether the image is a still image or a moving image. On the other hand, the input/output signals of the frame memory 702 are also input to a motion adaptive Y/C separation circuit 704.
Interframe Y/C separation or intrafield Y/C separation is performed using the motion signal from the motion detection circuit 703, and a luminance signal (or color signal) is obtained. Similarly, in the motion adaptive scanning line interpolation circuit 706, the motion detection circuit 7
According to the motion signal from 03, the field memory 705
An interpolated scanning line signal is created using the input/output signals of .

The actual scanning line signal α and the interpolated scanning line signal β obtained by the above method are used as the first. By inputting data into the second buffer memories 104 and 105, and then operating as described above,
Enlarged images can be obtained.

In this way, the embodiment shown in FIG. 1 can be combined with signal processing circuits having various types of interpolation methods.
In particular, by using the motion-adaptive processed real scanning line signal α and interpolated scanning line signal β as shown in FIG. It is possible to obtain high-quality enlarged images at twice the speed.

Next, FIG. 6 is a block diagram showing a second embodiment of the present invention.

In FIG. 6, 801 and 802 are frame memories 70
2 and a third .2 which gives the write address of the field memory 705. A fourth write address generator, 803.804, provides read addresses for frame memory 702 and field memory 705. A fourth read address generator 805 is a color television signal (interlaced video signal) from the input terminal 101 and a motion adaptive Y/C.
A second switch circuit 80 selects one of the output signals of the separation circuit 704 and supplies it to the frame memory 702.
6 is a third switch circuit that selects and outputs one of the output signal of the motion adaptive Y/C separation circuit 704 and the output signal of the motion adaptive scanning line interpolation circuit 706; A fourth switch circuit 808 selects and outputs one of the output signal of the Y/C separation circuit 704 and the output signal of the frame memory 702, and 808 selects and outputs the output signal of the motion adaptive scanning line interpolation circuit 706 and the field memory 705. This is a fifth switch circuit that selects and outputs one of the output signals, and the other parts are the same as those in FIG.

Generally, in order to obtain a progressive scan image of higher quality than an interlaced scan color television signal, a frame memory 702 for Y/C separation as shown in FIG.
Many systems include field memory 705 for scan line interpolation.

Therefore, in this embodiment, the frame memory 702 used for Y/C separation is also used as the first buffer memory 104 for performing image enlargement processing, and the field memory 705 used for scanning line interpolation is the same (for performing image enlargement processing). second for
It is configured so that it can be used also as the buffer memory 105.

Here, when enlarging the image twice both horizontally and horizontally, the image actually displayed on the double-speed monitor (not shown) is 1/4 of the entire screen of the incoming video signal, so , 1st. The memory capacity required for the second buffer memories 104 and 105 is 1/1 of the capacity required for writing.
Equivalent to 4 fields, the capacity required for reading is 1/1
This is equivalent to 4 fields, and in total, the capacity equivalent to 1/2 field is sufficient.

On the other hand, the frame memory 70 for motion adaptive Y/C separation
2 and a field memory 70 for motion adaptive scan line interpolation.
5, when enlarging, it is only necessary to correctly store incoming data for a portion corresponding to 1/4 screen that is actually displayed, and therefore the remaining storage area is used for the enlargement. It can be used in place of the second buffer memories 104 and 105.

In this embodiment, in normal times (that is, when no enlarged display is performed), the second to fifth switch circuits 805 to 808
is always connected to the a terminal side, performs the same operation as the circuit shown in FIG. 5, and obtains a double-speed converted video signal as the output signal of the first switch circuit 111.

On the other hand, during enlargement, the enlargement control circuit 112 controls the second
．． By controlling the switching of the third switch circuits 805 and 806 and connecting them to the a terminal side during the period in one screen and connecting them to the b terminal side during the other periods in one screen,
The signal after Y/C separation or scanning line interpolation is written into an unused area of the frame memory 7o2° field memory 705.

Then, the read enlarged signal (signal subjected to enlargement processing) is transmitted to the fourth terminal connected to the b terminal side. The signal is inputted to the double speed conversion memory 110 through the fifth switch circuits 807 and 808, and then taken out as a double speed converted signal from the first switch circuit 111.

According to this embodiment, it is possible to obtain an enlarged image without using a buffer memory only for the enlargement function.

In the first and second embodiments described above, an interlace video signal was considered as the input signal. However, there are also non-interlaced video signals. Therefore, next, an embodiment that can also handle non-interlaced video signals will be described.

FIG. 7 is a block diagram showing a third embodiment of the present invention.

In FIG. 7, 901 is a non-interlace determination circuit that determines whether the input video signal is an interlace signal or a non-interlace signal, 902 is a gate circuit that gates the field signal o dd / even, and others. is the same as in Figure 1.

In general, the difference between interlaced video signals (No. 8 and non-interlaced video signals) is the scanning line ■ of the television screen 200 shown at the left end of FIG.

In ■, ■, ..., in the interlace video signal, for example, the odd field (i.e., the first field)
The signals corresponding to the odd-numbered scanning lines ■, ■, ■, .

In contrast, in a non-interlaced video signal, for example, in both odd and even fields, signals corresponding to ■, ■, ... are sent.
, ■, ■, . . . where only the signals corresponding to the signals are sent.

Therefore, when the input video signal is a non-interlaced video signal, the first . The operations of the second read address generators 108, 109 and the switch circuit 111 are as follows:
There is no need to differentiate between odd and even fields as in the case of interlaced video signals.

Therefore, in this embodiment, when the input video signal is a non-interlaced video signal, the following operation is performed.

Here, a field signal o d d / indicating whether the input video signal is the first field or the second field (or, to put it in a fishing way, whether it is an odd field or an even field) even is shown in Figure 8 (
As shown in a), the input video signal is an odd number (odd
) field is at high level (H level),
When it is an even IX (e v e n) field, it is assumed to be at a low level (L level), and the non-interlace determination circuit 901 determines that the input video signal is as shown in FIG. 8(b). It is assumed that 1 level is output when it is determined that the signal is a non-interlaced signal.

That is, when the input video signal is a non-interlaced video signal, the output signal of the interlace determination circuit 901 that is input to the gate circuit 902 becomes H level, so that the output signal is input from the gate circuit 902 to the enlargement control circuit 112. The signal is a field signal o dd/e
Regardless of v e n, it is always at H level, and the first. The second read address generators 108 and 109 and the switch circuit 111 are fixed to even field processing, and an enlarged image without disturbance in the scanning line structure can be obtained even when a non-interlaced video signal is input.

The method for handling the input of non-interlaced video signals in this embodiment can also be applied to the circuit shown in FIG. 5 or 6 described above.

Next, FIG. 9 is a block diagram showing a fourth embodiment of the present invention.

In FIG. 9, 1101 is a read clock R, CL.
The frequency dividing circuit 1102 halves the K3 frequency, the switch circuit 1102 switches the read clock between the normal time and the enlarged time, and the others are the same as in FIG.

By the way, in the above-described embodiment of FIG. 1, when enlarging, in order to double the horizontal magnification, the first embodiment shown in FIG. From the second read address generation 8108.109, the first. Although the same read address was repeatedly given twice to each of the second buffer memories 104 and 105, in some cases, such a method may not be possible.

Therefore, in such a case, a problem arises in that enlargement can only be performed in the vertical direction.

Therefore, in this embodiment, the frequency of the read clocks R and CLK3 input to the double speed conversion memory 110 is set to
In other words, by setting the frequency to half the frequency (when no enlarged display is performed), the image is enlarged twice in the horizontal direction.

That is, in this embodiment, during normal times, the switch circuit 110
2 is connected to the a terminal side, and double-speed conversion memory 110
For example, the frequency of the write clock W, CLK3 is 4f.
sc, the frequency of the read clock R, CLK3 is 8f8. Therefore, double-speed conversion can be achieved.

On the other hand, when enlarging, the enlargement control circuit 112 connects the switch circuit 1102 to the b terminal side, and the double speed conversion memory 11
As the 0 read clock, a clock whose frequency is 1/2 of the normal frequency is used. Here, the address of the double-speed conversion memory 110 is reset by the same double-speed horizontal synchronization signal 2 as in normal times.
If you use fH, the read speed will be 1/2, so
An image enlarged twice in the horizontal direction can be extracted.

According to this embodiment, as described above, even if horizontal expansion cannot be performed using the read address generator and buffer memory, horizontal expansion can be performed using the double-speed conversion memory 110. can.

Note that this embodiment can also be applied to the circuits shown in FIG. 5, FIG. 6, or FIG. 7 described above.

Next, FIG. 10 is a block diagram showing a part of an image enlargement processing circuit as a fifth embodiment of the present invention.

In Figure 10, 1201 and 1202 are the first
The first one shown in the figure. Second buffer memory 104.105
An input terminal 1203 for the actual scanning line signal α and interpolated scanning line signal β supplied from the enlargement control circuit 114 is connected to the input terminal 1203 for the actual scanning line signal α and the interpolated scanning line signal β supplied from the enlargement control circuit 114 shown in FIG. Second read address generator 108, 109
Output terminal for control signals supplied to 1204.1205
1206 is a switch circuit for switching between the actual scanning line signal α and the interpolated scanning line signal β; 1206 is the switch circuit 1204°12;
The switch circuit for multiplexing the scanning line signals supplied from 05, the line memory 1207 for double speed conversion (line memory HM63021 manufactured by Hitachi), and the others are the same as in FIG.

Line memo IJ for double speed conversion made by Hitachi used in this example
1207 has a format in which when an actual scanning line signal and an interpolation scanning line signal are multiplexed and input, a double-speed converted video signal is output. Therefore, in this embodiment, instead of the switch circuit 111 used in FIG.
204, 1205° and 1206 are arranged before the line memory 1207 for double speed conversion, and the switch circuit 12
The output signals of 04°1205 are multiplexed by a switch circuit 1206 and supplied to a line memory 1207 for double speed conversion. The control signals for the switch circuits 1204 and 1205 may be the same as those for the switch circuit 111 in FIG. Further, in this embodiment, the horizontal expansion is performed in the same manner as in the embodiment shown in FIG.

As described above, in this embodiment, double speed conversion can be performed simply by using a commercially available line memory as the double speed conversion memory. The configuration of this embodiment is shown in FIGS. 5, 6, and 7.
It can also be applied to the circuit shown in the figure.

Now, in the description of each of the embodiments above, the case where the image is enlarged twice and displayed is explained, but the present invention is not limited to this, and the present invention is applicable to the case where the image is enlarged N times and displayed. can also be applied.

That is, when displaying an image enlarged by N times, in the circuits of FIGS. 1, 5, 6, and 7, the first and second read address generators 108 and 109: The same read address is repeatedly output N times in order to expand N times in the horizontal direction, and the same line is repeatedly output N times in order to expand N times in the vertical direction. .

In the circuit of FIG. 10, in order to expand N times in the horizontal direction, instead of repeatedly outputting the same read address N times as described above, the frequency of the read clocks R and CLK3 is reduced by 1/2 in the frequency dividing circuit 1101. The frequency should be divided into N.

The method of switching the switches in the switch circuit 111 is as follows.

FIG. 11 shows the operation during 3x enlargement in the present invention.
The figures are explanatory diagrams for explaining the operations during 4x enlargement.

11 and 12, (a) shows the vertical line numbers, and (b) shows the actual scanning line signal (actual signal) output from the real/interpolated scanning line signal generation circuit 103 and the interpolated scanning line signal (interpolated (C) shows the switching method of the switch in the switch circuit 111, respectively.

That is, by switching as shown in FIG. 11(c), 3
It is possible to display an image that has been enlarged twice, and the 12th
By switching as shown in Figure (C), it is possible to display an image enlarged four times.

Above, we have explained the case where double speed display is performed.
In Figure (c) or Figure 12 (c), if only the circled items are selected and switched for each standard speed line (for example, (C
), then the circled fruit, fruit, complement, fruit, fruit, supplement, ・
...and so on. ), even in the case of standard speed display, enlarged display that does not cause double images due to movement is possible.

〔Effect of the invention〕

According to the present invention, in the case of double-speed display, when obtaining an image enlarged from an interlaced or non-interlaced video signal, the scanning line structure is not disturbed or double images are not generated (high-quality enlargement is possible). You can get the image.

Furthermore, in a signal processing circuit equipped with a frame memory used for Y/C separation and a field memory used for scanning line interpolation, if the buffer memory for performing enlargement processing is also used as the frame memory or field memory, a new Expansion functionality can be achieved without adding memory to the .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is an explanatory diagram showing which part of the screen is enlarged in the embodiment shown in Fig. 1, and Fig. 3 shows the write address generated from the write address generator and the read address generated from the read address generator during enlargement in Fig. 1. FIG. 4 is an explanatory diagram showing the operation during enlargement in FIG. 1, and FIG. Detailed plot diagram,
FIG. 6 is a block diagram showing a second embodiment of the present invention, and FIG.
8 is a waveform diagram showing an example of the waveforms of the field signal and the output signal of the non-interlace determination circuit in FIG. 7, and FIG. 9 is a block diagram showing the third embodiment of the present invention. FIG. 10 is a block diagram showing a part of the image enlargement processing circuit as the fifth embodiment of the present invention, and FIG. 11 explains the operation during 3x enlargement in the present invention. FIG. 12 is an explanatory diagram for explaining the operation at 4 times magnification in the present invention.
3 and 14 are explanatory diagrams for explaining the conventional image enlargement display method, respectively. Explanation of symbols 103...Actual/interpolated scanning line signal generation circuit, 104°1
05... Buffer memory, 108, 109... Read address generator, 110... Double speed conversion memory, l1
2... Enlargement control circuit, 113... Enlargement control switch, 702... Frame memory, 703... Motion detection circuit, 704... Motion adaptive Y/C separation circuit, 70
5... Field memory, 706... Motion adaptive scanning line interpolation circuit, 901... Non-interlace determination circuit. Agent Patent Attorney Akio Namiki Figure 2 (CI) (b) Figure 3 (a) (C) Knee Engineering (+ p Figure 10 Figure 11 Figure 12 Figure 13 (Q) (b) l'
c) do to to
Do Do Figure 14 (Q) (b) <゛To

Claims (1)

[Scope of Claims] 1. Actual/interpolated scanning line signal generation means for generating an actual scanning line signal and an interpolated scanning line signal from an input video signal, and the generated actual scanning line signal and interpolated scanning line signal. first and second buffer memories temporarily storing the first and second buffer memories, respectively;
first and second address generating means for generating a write address and a read address for the buffer memory of the first and second buffer memories, and a write address and a read address for the second buffer memory, respectively; a double-speed conversion memory that inputs the real scanning line signal and the interpolated scanning line signal, doubles the frequency of each, and outputs the double-speed conversion memory; and inputs the actual scanning line signal and the interpolated scanning line signal output from the double-speed conversion memory. a switch means for selectively outputting one of them by switching a switch; The switching means are controlled so that the generation cycle of read addresses in the vertical direction of the screen is N times the generation cycle of write addresses in the vertical direction of the screen (N is an arbitrary number), and the switching means is An image enlargement processing circuit comprising: enlargement control means for controlling the switching order of the switches to be changed between an odd field period and an even field period of the video signal. 2. In the image enlargement processing circuit according to claim 1, the actual/interpolated scanning line signal generating means comprises a frame memory into which the video signal is input, temporarily stored and output, and an input/output signal of the frame memory. Detect movement in the image by typing,
a motion detection means for outputting the detection result as a motion signal; a luminance signal/color inputting the input/output signal of the frame memory, separating a luminance signal or a color signal according to the motion signal and outputting the luminance signal or color signal as the actual scanning line signal; signal separation means; a field memory into which the actual scanning line signal outputted from the luminance signal/chrominance signal separation means is input, temporarily stored and output; and a field memory into which the input/output signals of the field memory are input; 1. An image enlargement processing circuit comprising: scanning line interpolation means for performing scanning line interpolation according to the method and outputting the interpolated scanning line signal. 3. In the image enlargement processing circuit according to claim 1, the actual/interpolated scanning line signal generating means comprises a frame memory into which the video signal is input, temporarily stored and output, and an input/output signal of the frame memory. A luminance signal that is input, separates a luminance signal or a chrominance signal, and outputs it as the actual scanning line signal.
color signal separation means; a field memory for inputting the actual scanning line signal outputted from the luminance signal/chrominance signal separation means; temporarily storing and outputting the actual scanning line signal; scanning line interpolation means for performing interpolation and outputting the interpolated scanning line signal; a first feedback means for feeding back the scanning line signal to the frame memory; a second feeding means for feeding back the interpolated scanning line signal outputted from the scanning line interpolation means to the field memory; supplying means for supplying the output signal of the memory to the double speed conversion memory, the first buffer memory is also used as the frame memory, and the second buffer memory is also used as the field memory. Characteristic image enlargement processing circuit. 4. In the image enlargement processing circuit according to any one of claims 1 to 3, the positions of the double-speed conversion memory and the switch means are replaced with each other, and the actual data input to the double-speed conversion memory is An image enlargement processing circuit characterized in that a scanning line signal and an interpolated scanning line signal are input to the switch circuit, and a signal output from the switch circuit is input to the double speed conversion memory. 5. The image enlargement processing circuit according to any one of claims 1 to 4, which determines whether the video signal is an interlaced signal or a non-interlaced signal, and transmits the determination result. Non-interlace determining means is provided for inputting to the enlargement control means, and when the determination result is that the signal is a non-interlace signal, the enlargement control circuit determines that the switching order of the switches in the switch means is the same as that of the video signal. An image enlargement processing circuit characterized in that the switch means is controlled so that the odd field period and the even field period are the same. 6. The image enlargement processing circuit according to any one of claims 1 to 5, further comprising a switching means for switching the frequency of a read clock of the double-speed conversion memory, and performing image enlargement processing on the video signal. When displaying an enlarged image on the screen, the switching means is controlled by the enlargement control means to switch the frequency of the readout clock, so that the double-speed conversion memory converts the video signal into an image in the horizontal direction of the screen. An image enlargement processing circuit characterized by performing image enlargement processing for enlarging .