JPH01231461A - Integrated circuit for line data transmission/reception - Google Patents

Abstract

PURPOSE:To reduce hardware and to easily realize character interleave by a parallel data by devising a circuit so as to input a data corresponding to a bit serial data in parallel. CONSTITUTION:A 2nd input terminal 20 receiving a parallel signal in addition to a 1st input terminal 21 receiving a reception data as a bit serial data and an input data circuit 11 converting the signal of the 2nd input terminal 20 and giving the result to shift registers 13, 15, 16 are provided to the circuit. With a parallel data given externally to the input data circuit 11 from the 2nd input terminal 20, the data is set to the shift register of the input data circuit 11 and sent to the succeeding circuit via a selection circuit 12 for each bit and the circuit acts similarly in a way that as if the data given to the input data circuit 11 in a form of serial data were inputted to the 1st input terminal 21. Thus, the character interleave by the parallel data is easily realized without increasing the hardware quantity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit for transmitting and receiving line data. In particular, the present invention relates to an integrated circuit for transmitting and receiving line data when converting a high-speed line to a low-speed line using character interleaving.

〔overview〕

The present invention provides an integrated circuit for transmitting/receiving line data that inputs bit serial data and outputs the data as a parallel signal of multiple bits. By converting the data into data similar to bit serial data and feeding it to the subsequent conversion circuit, it is possible to easily implement character increments using parallel input without the need for special hardware.

[Conventional technology]

Conventionally, this type of line data transmission/reception integrated circuit has no method other than bit serial input for reception. Therefore, when low-speed line information with character increments is transferred over a high-speed line, the information on the low-speed line is normally obtained as parallel data by the line data transmission/reception integrated circuit for high-speed line reception, but this is need to be converted to data.

[Problem that the invention seeks to solve]

The conventional integrated circuit for transmitting and receiving line data mentioned above has no method for reception other than bit-serial input, so when receiving by character interleaving, a large amount of hardware is required to convert parallel data to bit-serial data. It has its drawbacks.

SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks and to provide an integrated circuit for transmitting/receiving line data that can reduce hardware and easily implement character interleaving.

[Means for solving problems]

The present invention provides line data that includes a first input terminal into which received data is input as bit serial data, means for converting this bit serial data into a parallel signal of multiple bits, and an output terminal that sends out this parallel signal. In the transmitting/receiving integrated circuit, a second input terminal for inputting a parallel signal is provided separately from the first input terminal, and the signal of the second input terminal is converted into bit serial data, and the above conversion means is provided. The invention is characterized in that it includes an input data circuit that provides input data.

[Effect]

Data equivalent to bit serial data can be externally input to the second input terminal as a parallel signal. This input data is input to the subsequent conversion circuit as if it were a bit serial input. In this way, character increments using parallel data can be easily realized without increasing the amount of hardware.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

The figure is a block diagram showing the configuration of an embodiment of the present invention.

The line data transmission/reception integrated circuit 10 according to the embodiment of the present invention has a first input terminal 21 into which received data is input as bit serial data, and shift registers 13, 15 and 16 which convert this bit serial data into a plurality of bits of parallel signals. , an output terminal 23 that sends out this parallel signal, a second input terminal 20 that inputs the parallel signal separately from the first input terminal 21, and a signal of this second input terminal 20 that converts the signal of this second input terminal 20 into bit serial data. and an input data circuit 11 that converts the data and supplies it to shift registers 13, 15 and 16.

Furthermore, the input data circuit 11 and the first input terminal 21
The error control circuit 14 includes a selection circuit 12 that selects an input from the input terminal and sends it to the shift register 13, an error control circuit 14 connected to the shift registers 13 and 15, and a control circuit 17 connected to a signal line 22.

The above circuits are general registers, shift registers, and selectors, and the error control circuit 14 has functions such as CRC calculation or parity check, and is constituted by a set of adders and gates.

Next, the general reception operation of the line data transmission/reception integrated circuit 10 will be explained. First, serial data from the line is input through the No. 1 input terminal 21, character assembly is performed in the selection circuit 12, shift register 13, and shift register 15, and output as a parallel signal to the outside by the register 16. Ru. Furthermore, the error control circuit 14 checks whether there are any errors in the received data.

The above is the general operation of the conventional line data transmitting/receiving integrated circuit, but the operation in the parallel input mode according to the present invention, which operates in addition to this, will be explained. When parallel data is input from the outside to the input data circuit 11 through the second input terminal 20, the data is set in the shift register of the input data circuit 11, and passed through the selection circuit 12 bit by bit to the subsequent circuit. Thereafter, the data applied to the input data circuit 11 operates in the same manner as if serial data were inputted through the first input terminal 21. therefore,
When line data is obtained in the form of parallel signals during character incretion, by inputting this data to the input data circuit 11, low-speed line data can be received.

〔Effect of the invention〕

As explained above, the present invention has the advantage that by allowing data equivalent to bit serial data to be input in parallel, hardware can be reduced and character increments can be easily realized using parallel data. .

[Brief explanation of the drawing]

The figure is a block diagram showing the configuration of an embodiment of the present invention. 10... Integrated circuit for transmitting and receiving line data, 11... Input data circuit, 12... Selection circuit, 13.15...
Shift register, 14...Error control circuit, 16...
Register, 17... Control circuit, 20... Second input terminal, 21... First input terminal, 22... Signal line,
23...Output terminal.

Claims (1)

[Claims] 1. A first input terminal (21) into which received data is input as bit serial data; means (13, 15, 16) for converting this bit serial data into a plurality of bits of parallel signals; In the line data transmission/reception integrated circuit equipped with an output terminal (23) for sending out parallel signals, a second input terminal (20) for inputting parallel signals is provided separately from the first input terminal; an input data circuit (11
) An integrated circuit for transmitting and receiving line data.