JPH01231426A - Data selecting circuit - Google Patents

Abstract

PURPOSE:To obtain an output waveform in which distortion is suppressed by connecting plural units each consisting of a multiplexer with a retiming flip-flop as a tree structure. CONSTITUTION:Units 2-6 consist each of a multiplexer with a retiming flip-flop storing the result of arithmetic operation synchronously with a clock signal, the retiming flip-flop stores an output signal of the multiplexer tentatively before a selection signal of the multiplexer changes from a low level to a high level or vice versa and outputs the value as an output signal of the units 2-6. Thus, the distorted output signal of the multiplexer appeared while the selection signal is changed is not outputted and the output signal without distortion before the selection signal is changed is outputted as the output of the units 2-8, then the output signal of the data selecting circuit where the units 2-6 are configurated as tree structures 8, 9 has no distortion. Thus, an output waveform without distortion is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a data selection circuit that is an improved multiplexer or demultiplexer.

(Prior art) Integrated circuit using Schottky gate field effect transistor (MES FET) using GaAs as base material
IC) is attracting attention because it can operate at high speed with lower power consumption than IC using Sl. Due to its high speed, it is expected to be applied to various logic circuits such as shift registers and multiplexers. In particular, time-sharing multiplexers (data selection circuits) are used as high-speed data generation circuits for high-performance equipment such as electronic computers and communication equipment. It is often used in important parts.

There are two types of data selection circuits: a shift register type circuit shown in FIG. 7 and a combinational logic circuit type shown in FIG. 8 in which multiplexers are combined in a Towry structure. Shift register type circuit (SR type).

Combinatorial logic circuits (SQ type) each have advantages or disadvantages compared to the other as shown in Table 1, and are generally used depending on the requirements of the application circuit.

(Left below) Table I Advantages and disadvantages of SR type and SQ type GaAs I
In the case of C, since its application is generally high speed, it is often a combinational logic type circuit (SQ type), with some exceptions.

However, as shown in Table 1, 5Qfi has many disadvantages, including the major disadvantage that the output signal (Dout) is distorted. Figure 9 shows the conventional 4:
1 shows an example of an l multiplexer. FIG. 9(a) is the logic circuit diagram of fi, (90°)t (901), (9
0ri.

(90 Hatake) was a 3-person NOR gate. (904
) is a four-person NOR gate. FIG. 9(b) shows the waveform when this multiplexer is operated. 3 person power No.
Hole Gu) (90°), (901), (901),
(901) respective input data 'tH No. Do, Dt,
D2. The case where the 1 selection signal (St, so) is inputted is shown in the state where Da is '0'', ''l', '1', and '0'.

At time A, 51=1. With So:O input.

Since the outputs of the three-person NOR circuit are all '0'', the output signal (Dout) of the four-person NOR circuit (904) is 11.
It will be 1m. At time C, the 3-man power NOR circuit similarly outputs ``锴'', and the 4-man power NOR circuit (904) (D
Dout is.

It becomes 61'. However, at 1 hour B, while kSisS (1) is changing, it may become '0'' at the same time.

In this case, the output of the 3-person NOR circuit (90°) is “1”
.

The output of (90□), (9oz), (908) is “o
``tonashi'', therefore 4-person power N that should continue to output ``1''
D out of the OR circuit (904) momentarily drops to ``O''. That is, in a multiplexer like S,
Since this effect could not be avoided when the voltage level of S changes, and the input data signal was not output stably, the conventional 8Q type composed of these multiplexers did not use such a configuration for the output signal. There was a problem in that the distortions were superimposed.

(Problems to be Solved by the Invention) As described above, in the conventional SQ type circuit composed of multiplexers, distortion is superimposed on the output waveform.

There was a problem that it was not in good condition.

The present invention has been made in view of one or more problems, and it is an object of the present invention to provide a data selection circuit that is suitable for high-speed operation and can obtain an output waveform with distortion suppressed to the same extent as the SR type.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a data selection circuit configured by connecting a plurality of unit units configured by providing a retiming flip-flop in a multiplexer in a Towley structure. .

It also includes a multi-input multiplexer or demultiplexer made of a combinational circuit of logic gates, and a counter that extracts a multi-bit data selection signal from an input clock signal and supplies the data selection signal to the multiplexer or demultiplexer. Provided is a data selection circuit comprising: a data selection circuit characterized in that the data selection signal changes bit by bit.

(Function) First, in the present invention, a unit is configured by holding arithmetic results in synchronization with a clock signal or by providing a timing free lag frog in a multiplexer, and when the selection signal of the multiplexer changes from a low level to a high level. Before changing from high level to low level, the retiming flip temporarily holds the output signal of the multiplexer and outputs this value as the output signal of these units.

Therefore, the distorted multiplexer output signal that appears while the 1 selection signal changes is not outputted, and the undistorted output signal before the selection signal changes can be output as the output of the unit, so the unit is assembled into a Towry structure. The output signal of the data selection circuit has a waveform without distortion.

Second, the data selection signal supplied from the counter to the multiplexer or demultiplexer is 1, for example (S
. , 81)=(0,0)2:'(0,1)−:(1,
1) 2 (1,0) Tsumap IOJ, %te 0→1→3
→2, and So or 81 is changed by 1 bit every clock.

Therefore, there is no instability that occurs when So and S change together, and the output of the multiplexer or demultiplexer is stable.

(Example) A detailed explanation of the present invention will be given below using examples.

FIG. 1 is a block diagram of a 16-bit data input time division multiplexer circuit according to a first embodiment of the present invention. DC using GaAs MESFET as basic gate
A NOR gate of an FL circuit was used. (1) is a 16-bit input latch and consists of 16 D-type flip-frogs. (2), (3), (4), (5) and (6) are 4:1 multiplexers with retiming flip-flops, which are units of the present invention. Also, (2).

The multiplexers <3), (4), and (5) constitute the first stage (s), and the multiplexers (6) constitute the second stage (9), respectively.

Each multiplexer has a built-in D-type flip-flop as a timing flip-flop. (
7) is a 4-stage synchronous counter, and the 4-bit output is sent to the first and second stage multiplexers (8) through a latch consisting of 70 built-in D-type flips.
, (9) can be output.

4-bit output of counter (7) (e.g. 0000→00
01→0010...), the lower two bits are So,
S, is supplied to the first stage multiplexer (8),
The upper 2 bits are So of the second stage multiplexer (9),
Supplied as Sl. Other NO of each multiplexer
In the R gate, (So, 5l) - (80
, st), (So, Sr) are input. The output of the counter (7) is updated in synchronization with the clock signal (CK).

According to this embodiment, both the first stage (8) and the second stage (9) operate according to the same CK, making it easy to design the υ1 circuit.

From the second stage multiplexer (9), data is output from the data at the end of the counter (input data D.-D15 as the output of the force is updated).

These multiplexers (2), (3), (4),
(5) and (6).

As shown in FIG. 2(a), the NOR gate (
200), (2oo), (20ri, (20B),
(20tt), (20ff), (206), (
20? ).

(20g), (20G), (20t.), (201+
), the conventional structure is 4:1 as shown in Figure 4.
It is constructed by adding a D-type flip-frog device to a multi-plexer (2+). At this time, one NOR gate was removed from the general D-type frig-frog, and 5 human-powered NO
R gate (20+t) was substituted for simplification. A block diagram of these is shown in FIG. 2(b). Next, the operation of this multiplexer will be explained according to FIG. Figure 3 (
3(a) shows a logic circuit diagram, and FIG. 3('b) shows a selection signal, a clock signal, and an output signal (D out), respectively. Three-man powered NOR gate (20°λ(201), (201χ(2
01) input data signal, Dl, D, D,
A case will be described in which the values are "0", "1", 1", and 0", respectively. At time A, the 1 selection signal 80=Q, 3s=l, so the output of the NOR gate (20°) is "On", and the other three NOR gates (201), (zot)
, (2oi) outputs ``0'', and along with this, 4-man power N0F-game) (20,) outputs ``l''. The clock (CK) of this time-type flip-flop
Since ``1'' is input in , this four-person NOR
Game) Holds the output of (204), 11'', and outputs Q p D out ``1''.And f)
out "1"d, from the characteristics of a D-type flip-flop.

Until time C comes and "1" is input to CK again.

It remains unchanged at time B as well. Like this.

It is possible to output distortion-free D out according to the timing input to CK of the D-type flip-flop.

As a result of actually operating the data selection circuit of this example,
It was confirmed that it operates normally at a clock frequency of 1460MHz. For comparison, we fabricated a prototype data selection circuit with a similar Towley structure consisting of the conventional multiplexer shown in Figure 9, and the yield was as follows.

In the case of the present invention, it is 71 inches, and in the conventional example, it is 55 inches. This difference in yield is thought to be due to distortion of the parallel data between layers within the chip and the data selection signal, considering that chip failures occurred due to timing errors in the conventional case, and the effectiveness of the present invention is considered to be confirmed by experiment).

Next, a second embodiment of the present invention will be described. Figure 4 is the second
FIG. 2 is a logic circuit diagram of a 4-pit input data selection circuit according to the embodiment. (41) is (41°), (411),
('1it).

This is a four-person multi-flexor system consisting of a (41m) human power line and an output line (414). (43 is four buffer gates (43°), (431), (431)
, (433). Also,
(4!9 is D type 7 lip flow, G (421), (42
This counter is composed of a clock driver 04 of both phases, which supplies complementary clock signals to the clock counter t).

The two-phase clock driver (14) to which the one-pulse clock signal (CLOCK) is input outputs a complementary clock signal, and supplies this to the clock signal counter (6). This clock signal (in the 4th series, two types of complementary signals (So, St) are generated from this clock signal.

(So, see). °This complementary signal 8. , 8. ,
S,, 3. is the buffer gate (43°), (43υ
, (43), the current is amplified in (43s) and supplied to the multiplexer (41) as a data selection signal.

This multiplexer (4 units) will be further explained in detail in Figure 5.The circuit configuration is as shown in Figure 5(a).
Circuit (500), (501), (sos), (s
ow) and a four-person NOR circuit. The input data signals of this multiplexer are D, D, Dt.
are sequentially ``IQ'', IIIN, and ``'θ''.

1'', the data selection signal so is changed by 1 bit for each clock signal as shown in Table 1.
so, s,, s, each NOR circuit (SOO)
.

(501), (sot), (50m) were input.

Table 1: The data selection signals so, s, s, s are not in sequential order, but are expressed in decimal notation as 0 → 1.
I am trying to change it from →3 →2. At the same time, by arranging the input lines in advance in the order of Do, D,, D,, D, the number of input lines is the same as that of a normal multiplexer.
c Do, Dt.

The data input to D, ``'0'', 11'',
@1” and O” can be output in order to the output line D out. Figure 5(b) shows that (So=St) changes from (0,0) to (0
, 1) Dou for the time when one bit changes
In the diagram showing the voltage level of t, Dout is bordered by the value a near the center of 1 and O at time A, and below that value '
0" If it is larger than this, there is definitely no siros time for ``1". Figure 5(e) shows the case of a conventional multiplexer for comparison. (so, St) is (0, 1) → (1
, 0), Dout should always be displayed as 1'', but it becomes unstable and falls to ``0'' during the B-B time, resulting in a malfunction. In addition, the data selection circuit of this embodiment can perform reliable operation at high speed.

This data selection circuit was prototyped using a NOR gate of a DCFL circuit using GaAs ME S FET as a basic gate, and it was confirmed that it operated normally at a clock frequency of 1800 MHz. In addition, we prototyped a 4:1 multiplexer using a conventionally used 2-bit synchronous counter instead of a digital camera counter, and confirmed that it operated normally up to a clock frequency of 1400 MHz.

In this embodiment, a 4:1 multiplexer is used that reads out a 4-bit simultaneous input signal bit by bit.

The invention is not limited to this, and for example, as in the first embodiment, four emmultiplexers arranged in parallel may be arranged in the front stage in a Towry structure, and the 16-bit signal may be read out one bit at a time. good.

A third embodiment of the present invention will be described with reference to FIG. 6th
Diagram (a) Te, (60,) is NOT circuit, button is 4:
1 Demultiplexer, signal series input signal DIN
Do, D,, D,, D, by these circuits.
The signal is divided into four signals and output in order. At this time, the data selection signal s0. of the 4:1 demultiplexer. The optical, s, blades are made in the same way by the clock (49) and buffer circuit (43) shown in Fig. 4. Fig. 6(b) shows the inside of the 4:1 demultiplexer as a logic circuit. !l), (600),
(601), (1502).

(SOW) is a three-man NO method circuit. “0”,”
1”, “1”.

When serial data (DIN) sent in the order of "0" is input in synchronization with the timing of the data selection signal,
First, the first "0" is input to the NOT circuit (604). This data is changed to '1'' by a NOT circuit (604), and four NOR circuits (600), (601)
, (60z).

(6OS). In addition, data selection signals (so, S) are sent to the NOR circuit in synchronization with the timing of this data.
t) is input as "0", "0". Therefore, NOR
``0'' is output to the output line D of the circuit. In this way, other serial data "1", "1", "0" (0
,1), (1,1).

(1, 0) and a data selection signal that changes by 1 bit.'
) are sequentially output to the D+, Dt, and Da output lines.

In this case as well, it is possible to avoid an unstable state that would occur if the data selection signals (So, St) change simultaneously.

Stable high-speed operation is possible with a2.

The present invention has been explained above with reference to several embodiments.
The present invention can be applied to all SQ type data selection circuits,
In addition to GaAsIC, 5iIC and these hybrid ICs4[
Needless to say, it can also be applied. Further, the multi-breather may be configured with a NAND gate instead of a NOR gate.

It goes without saying that the present invention can be implemented with various modifications without departing from the spirit thereof.

〔Effect of the invention〕

According to the above configuration, it is possible to provide a data selection circuit that is suitable for high speed operation and suppresses output waveform distortion.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data selection circuit according to a first embodiment of the present invention, FIGS. 2 and 3 are diagrams showing a 4:1 multiplexer according to a first embodiment of the present invention, and FIG. Figure, 5th
The figure shows a second embodiment of the invention. In fig. 1...16-bit person Carracci. 2, 3.4.5.6...4:1 multiplexer. 7...4-stage synchronous counter. 8...1st row, 9...2nd row. 41...4:1 multi-luxury, 42...Jeonun counter. 43...Buffer circuit, 60...4:1 demultiplexer. 604...NOT circuit. Agent Patent Attorney Noriyuki Chika Yudo Mitsuyuki Matsuyama Figure 1 Figure 3 Figure 9 Figure 4 rA

Claims (6)

[Claims] (1) A data selection circuit configured by connecting units configured by providing a multiplexer with a retiming flip-flop in a tree structure. (2) The data selection circuit according to claim 1, wherein the retiming flip-flop is a D-type flip-flop circuit. (3) A multiplexer or demultiplexer consisting of a combinational circuit of logic gates, and a multi-bit data selection signal that sequentially selects the input data of the multiplexer or demultiplexer from a clock signal, and the data selection signal is transmitted to the multiplexer or the 1. A data selection circuit comprising a counter that supplies a demultiplexer, wherein said data selection signal changes bit by bit. (4) The data selection signal is supplied to the multiplexer or demultiplexer via a buffer gate provided between the multiplexer or demultiplexer and the counter.
Data selection circuit as described. (5) The data selection circuit according to claim 3, wherein the counter is comprised of a flip-flop. (6) The data selection circuit according to claim 1 or 3, wherein the multiplexer is comprised of a NOR gate.