JPH01231107A - Clock pulse stop control system - Google Patents

Abstract

PURPOSE:To quickly stop a device in which a fault has been generated at the time when the fault has been generated, and also, to take a coincidence of a stop state at the time of debug of a multi-processor system by providing a switching device and switching a switch in accordance with use. CONSTITUTION:Information processors 2, 3 are both provided with a logic circuit which operates by synchronizing with a clock pulse, and a clock pulse, and a clock pulse input stopping means for responding to formation of a stop condition in the own device at the time of an enable state. A clock pulse generating device 1 is provided with a clock pulse generating means, a clock pulse stop means for responding to an input of a stop signal at the time of an enable state, and a stop signal input means for inputting a stop signal to the clock pulse generating means at the time when the stop condition of one of the information processors 2, 3 has been formed. A switching device 4 sets alternatively all the clock pulse input stopping means and clock pulse stopping means in the information processors 2, 3 to an enable state.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock pulse stop control system, and more particularly to a clock pulse stop control system for a plurality of information processing devices.

Previously, there were two types of clock pulse stop control systems of this type. Figure 2 shows the two conventional examples.
This will be explained using FIG.

Figure 2 shows the first example of the conventional clock pulse stop control system.
In FIG. 0, which is a system diagram showing an example configuration, a first example of a conventional clock pulse stop control system includes a clock pulse generator 1 and two information processing devices 2 and 3.

The clock pulse generator 1 includes an oscillator 11, drivers 12 and 13 for distributing and supplying clock pulses to the information processing devices 2 and 3, respectively, and a stop (permission) signal for stopping the supply of clock pulses. The circuit includes a flip-flop 16 that generates clock pulses, and a driver 14 that supplies clock pulses to the flip-flop 16.

The information processing devices 2 and 3 include flip-flop (F/F) groups 23 and 33 that operate in synchronization with clock pulses, respectively.
, driver groups 21 and 31 for distributing and supplying clock pulses 101 and 102 supplied from the clock pulse generator 1 to these flip-flop groups, and a flip-flop for detecting device stop conditions such as failure occurrence. 24 and 34.

The information processing device 2 also has an OR circuit 26, to which the outputs of the flip-flops 24 and 34 are input.

The operation of the conventional clock pulse stop control system having such a configuration will be explained with reference to FIG.

FIG. 3 is a time chart showing the operation of each part of the clock pulse stop control system in FIG. 2. In FIG.
The transmitting side of the clock pulses 101 and 102, the output of the flip-flop 24, the transmitting side of the output 203 of the OR circuit 26, the receiving side of the output 203 of the OR circuit 26, the output 104 of the flip-flop 16, and the clock pulse 101
The waveforms of the receiving side of the clock pulse 102 and the receiving side of the clock pulse 102 are shown.

When a failure or the like occurs at time t1, the flip 70 knob 24 is turned on, and the output 203 (transmission side) of the OR circuit 26 is turned on. This output 203 has a signal propagation delay due to the distance between the devices, and reaches the input of the flip-flop 16 with a delay (■). This turns the flip-flop 16 on, and the stop (permit) signal 1
04 turns off (■), this stop signal 104 turns drivers 12 and 13 off, and the sending of clock pulses 101 and 102 is suppressed (■), sending of clock pulses 161 and 102 is immediately suppressed. However, the signal propagation delay is added, and the information processing device 2
and 3, the clock pulse stops at time t2a with a delay of Δt (■).

In the case of this first example, when a failure occurs, the signal propagation delay when sending the output 203 of the OR circuit 26 to the clock pulse generator 1 and the transmission of the clock pulse are suppressed, and then the information processing devices 2 and 3 are The drawback was that it took a long time for the clock pulse to stop. Due to this delay time, there is a drawback that many clock pulses are sent out from the time when a failure occurs until the clock pulses actually stop.

Note that this delay time increases as the distance between the signal line between the clock pulse generator and the information processing device increases;
The shorter the synchronization of the clock pulses, the greater the value.

FIG. 4 is a system diagram showing the configuration of a second example of the conventional clock pulse stop control system. In FIG. It is configured to include information processing devices 2 and 3.

The clock pulse generator 1 includes an oscillator 11 and drivers 12 and 13 for distributing and supplying clock pulses to the information processing devices 2 and 3, respectively.

Information processing bag r! 12 and 3 are flip-flop (F/F) groups 23 and 33 that operate in synchronization with clock pulses, respectively, and clock pulses 101 and 102 supplied from the clock pulse generator 1 are distributed to these flip-flop groups. driver groups 21 and 31 for supplying signals, flip-flops 24 and 34 for detecting device stop conditions such as occurrence of a failure, and stop (permission) signals 250 and 350 for suppressing input of clock pulses. It is configured to include flip-flops 25 and 35 for sending clock pulses, and drivers 22 and 32 for supplying clock pulses to the flip-flops 25 and 35.

Clock pulses of opposite polarity are input to the flip-flops 25 and 35 so that the tarlock is inhibited at the correct timing.

Further, the information processing device 22 has an OR circuit 26,
The outputs of the flip-flops 24 and 34 are input to this OR circuit 26.

The operation of the conventional clock pulse stop control system having such a configuration will be explained with reference to FIG.

FIG. 5 is a time chart showing the operation of each part of the clock pulse stop control system of FIG. 4. In FIG.
The output of the flip-flop 24 and the output 2 of the OR circuit 26
03, the clock pulse 210, the input of the flip-flop 25, and the output 25 of the flip-flop 25.
0, clock pulse 310, and flip-flop 35
The respective waveforms of the input of the flip-flop 35 and the output 350 of the flip-flop 35 are shown.

When the output of the flip-flop 24 turns on in response to the establishment of the stop condition for the fault, the OR circuit l? 826
The output 203 (transmission side) turns on (■), and this output 203 is relatively far away from the flip-flop 25 and input to the flip-flop 35 late due to the signal propagation delay due to the distance between the devices. (■), which results in
The flip-flop 25 is turned on, and the output (stop signal) 250 is turned off (■).Also, due to a timing shift, the flip-flop 135 is turned on, and the output (stop signal) 350 is turned off. (■).

Then, the clock pulse (output of the driver group 21) 210 is output at time t1 by the output 250 of the flip-flop 25.
(■), and the flip-flop 3
The clock pulse (driver group 31
output) 310 is suppressed at time t2 (■),
In other words, clock pulse 310 is inhibited with a delay of Δt from clock pulse 210.

In the case of this second example, the delay time from when a failure occurs and the output 203 of the OR circuit 26 turns on until each clock pulse is inhibited is small, but the timing of inhibition of each information processing device is The problem was that it would shift.

Therefore, it is suitable for immediately freezing the device when a failure occurs, but it has the disadvantage that when debugging a multiprocessor system, each device stops separately and the states cannot be matched. there were.

An object of the present invention is to provide a clock pulse stop that can immediately freeze a device in which a failure occurs when a failure occurs, and ensure that the stop states match when debugging a multiprocessor system. It is to provide a control system.

Structure of the Invention The clock pulse stop control system of the present invention includes logic circuits each receiving a clock pulse as an input and operating in synchronization with the clock pulse, and a logic circuit that receives a clock pulse as an input and operates in synchronization with the clock pulse. a plurality of information processing devices each having a clock pulse input stop means for stopping input of the clock pulse; a clock pulse generation means for generating the clock pulse; and a clock pulse input stop means for generating the clock pulse; and a stop signal input means for inputting the stop signal to the clock pulse generation means when a stop condition for any one of the plurality of information processing devices is satisfied. The information processing apparatus is characterized by comprising: a switching device that selectively enables all of the clock pulse input stopping means in the plurality of information processing devices and the clock pulse stopping means.

K soilyo Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a system diagram showing the configuration of an embodiment of a clock pulse stop control system according to the present invention.

In the figure, a clock pulse stop control system according to an embodiment of the present invention includes a clock pulse generator 1, two information processing devices 2 and 3, and a switching device 4.

The clock pulse generator 1 includes an oscillator 11, drivers 12, 13 and 14, and a flip-flop 16, and has almost the same configuration as the first conventional example (see FIG. 2).

The first information processing devices 2 and 3 each have a frit flop group 23.
and 33, driver groups 21 and 31, and driver 22
and 32, flip-flops 24 and 25, and 34 and 3
5, each having almost the same configuration as the second conventional example (see FIG. 4). The difference from the second conventional example is that the output of the flip-flop 24 of the information processing device 2 is input to the flip-flop 25 in addition to being input to the OR circuit 26, and the output of the 7-lip-flop 34 of the information processing device 3 is input to the OR circuit 26. In addition to being input to the circuit 26, it is also input to the flip-flop 35.

Switching equipment! 4 has a switch 41 and an inverter 42, which selectively enables the 7 flip-flops 16 in the clock pulse generator 1 and the flip-flops 25 and 35 in each of the information processing bags e2 and 3. It is something to do.

In this configuration, by keeping the switch 41 in the on state, when a failure occurs, it is possible to quickly stop the device in which the failure has occurred.

Further, by turning off the switch 41, it is possible to match the stop states of each information processing device when debugging a multiprocessor system.

Note that the switch 41 may be dynamically controlled using software.

Further, in this embodiment, the case where there are two information processing apparatuses has been described, but it is clear that similar effects can be obtained for even more information processing apparatuses.

1 匪゜Left-hand type - As explained above, the present invention provides a switching device and changes the switch according to the application, so that when a failure occurs, the device in which the failure occurs is quickly stopped, and the multiprocessor system is This has the effect of making it possible to match the stop states during debugging.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing the configuration of a clock pulse stop control system according to an embodiment of the present invention, and FIG. 2 is a system diagram showing the configuration of a first example of a conventional clock pulse stop control system.
Fig. 3 is a time chart showing the operation of each part in Fig. 2, Fig. 4 is a system diagram showing the configuration of a second example of a conventional clock pulse stop control system, and Fig. 5 is a time chart showing the operation of each part in Fig. 4. FIG. Explanation of symbols of main parts 1... Clock pulse generator 2.3...
...Information processing device 4...Switching device

Claims (1)

[Claims] (1) A logic circuit that receives a clock pulse as input and operates in synchronization with the clock pulse, and a clock pulse that stops the input of the clock pulse in response to the establishment of a stop condition within the device when enabled. a plurality of information processing devices having input stop means; clock pulse generation means for generating the clock pulse; and clock pulse stop means for stopping generation of the clock pulse in response to input of a stop signal when in an enabled state. , a clock pulse generation device having stop signal input means for inputting the stop signal to the clock pulse generation means when a stop condition for any one of the plurality of information processing devices is satisfied; and within the plurality of information processing devices. A clock pulse stop control system comprising: a switching device that selectively enables all of the clock pulse input stop means and the clock pulse stop means.