JPH01228219A - logic circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Schottky barrier gate type FET made of compound semiconductor
Regarding logic circuits suitable for application to ultra-high-speed logic operation integrated circuits using
In order to improve reliability and reduce dependence on power supply voltage, it is composed of Schottky barrier gate type field effect transistors, and has at least two switching means for switching and outputting a high potential or a low potential depending on the input logic level.
In a logic circuit arranged in stages or more, when the output of one switching means is at a high potential, the high potential is clamped to a predetermined constant value, and the current flowing from the output to the next stage switching means is shunted. A bypass means is provided to bypass a predetermined constant power source.

[Industrial application field]

The present invention relates to logic circuits, and in particular to gallium arsenide (Ga
The present invention relates to a logic circuit suitable for application to an ultra-high-speed logic operation integrated circuit using a Sho-Nodky barrier gate type FET made of a compound semiconductor such as As).

Recently, there has been an increasing demand for high-speed operation in semiconductor integrated circuits, and Schottky barrier gate FETs (hereinafter referred to as MES) made of compound semiconductors such as GaAs have recently been increasing.
FET: MEtal Sem1conduc
With the practical use of torFETs, high-speed operation is being achieved.

QaAs has an electron mobility of approximately 5 compared to silicon.
It is about twice as large and has various excellent physical properties as a high-speed, high-frequency device material. For example, GaAs has a larger band gap than silicon, so it is possible to obtain a high-resistance crystal called a semi-insulating crystal. In this case, a single MES FE based on a semi-insulating crystal
By configuring an integrated circuit using T or MES FETs, parasitic capacitance can be reduced, elements can be easily isolated, and an integrated circuit capable of ultra-high speed operation can be realized.

In addition to GaAs, there are various combinations of compound semiconductors such as gallium phosphide (GaP), indium phosphide (InP), and indium arsenide (InAs). Therefore, it is hereinafter referred to as a III-V semiconductor.

As mentioned above, MES FETs made of m-v semiconductors are capable of ultra-high-speed operation, and do not lose their amplification effect even at frequencies of about 30 GIIz. Therefore, it can be applied to a wide variety of fields, for example, it is applied to logic circuits that perform logic operations at ultra-high speed, and ultra-high-speed logic operation integrated circuits are realized.

[Conventional technology]

As such a conventional logic circuit, for example, the so-called S D F L (Shcott
kyDiode EFT Logic).

In the figure, 1 is a logic circuit using 5DFL, and the logic circuit 1 is composed of inverters 2a and 2b connected in two stages.
Consisting of The configurations of the inverters 2a and 2b are the same, and hereinafter, the members constituting the two will be designated by symbols a and b to correspond to each other.

The input signal Din is input to the inverting logic circuit 6a through a level shift circuit 5a consisting of a level shift diode 3a and a constant current-connected pull-down FET 4a. The inverting logic circuit 6a has a driver FET7a and a driver F
Load FET8a connected with constant current as load of ET7a
When the input signal Din becomes H level, the driver FET7a is ONL and the load FET8 is connected from the positive power supply line.
common power supply line Vs via a and driver FET7a
A current determined by the load FET 8a flows through s.

Therefore, the output of the inverter 2a is at L level, t, that is, 1. becomes the potential of the common power supply line Vss, and the output signal Dout of the next stage inverter 2b becomes H level.

At this time, the level shift of inverter 2b)・circuit sba
This is the pull-down FET4 via the load FET3a in the previous stage.
A current determined by b flows into the negative power supply line VEE via the pull-down FET 4b.

On the other hand, when the input signal Din goes to L level, the driver F
Since ET7a is turned off, the output of inverter 2a becomes H level. In this case, a current determined by the load FET 8a flows into the level shift circuit 5b at the next stage, and most of this current is transferred to the MES FET 7b from the driver FET 7b.
Since it is an ET, it flows into the gate of the driver FET7b.

In addition, in order to increase the speed of the − layer, the area of the level shift diodes 3a and 3b is expanded to increase the interelectrode capacitance.
It acts as a so-called speed amplifier capacitor. For example, when the area of the level shift diodes 3a and 3b is 40 μm×6 μm, a capacitance of approximately 200 fF is generated, and the high frequency signal component is transmitted to the next stage via the interelectrode capacitance.

Problems to be solved by invention C] However, in such conventional logic circuits,
Since the current value flowing into the next stage differs depending on the logic level of the previous stage, the following problems have occurred.

That is, since the current flowing into the next stage flows through the level shift diode 3b which functions as a speed-up capacitor, the voltage between the electrodes of the level shift diode 3b differs depending on the output logic level of the inverter 2a. For example, Voo-2°OV, Vss=Ov, yEE
= -1,6y, the output D2 of inverter 2a
The interelectrode voltage V and inflow current I of the level shift diode 3b for each logic level have been obtained as experimental data as shown in Table 1 below.

Table 1 As is clear from Table 1 above, the change Δ■ in the voltage V between the electrodes of the level shift diode 3b is 0.13V with respect to the change in the logic level - of the output D6 of the inverter 2a. Therefore, the inverter 2a charges and discharges the interelectrode capacitance C of the level shift diode 3b by the voltage ΔV, and the charging and discharging time Δt is expressed by the following equation (2).

■ For example, the charging/discharging time Δt based on the data in Table 1 is approximately 52
psec, the time required for charging and discharging cannot be ignored, and in this case, the response speed becomes slow.

Furthermore, since the gate current flowing into the driver FET 7b is large, there is an increased possibility that electromigration will occur in the gate electrode of the driver FET 7b, leading to a decrease in reliability.

Furthermore, when the outputs of inverters 2a and 2b are at H level, the stability of this level depends on the stability of the power supply line VOO, so the H level of the output is likely to become unstable due to fluctuations in the power supply voltage, and the next stage There is also a concern that the inverter 2b may malfunction.

Therefore, the present invention reduces power consumption by clamping the level when the output of the previous stage is at H level, and shunting and bypassing the current flowing into the next stage to reduce the current flowing into the next stage. The purpose is to increase speed without increasing power supply voltage, improve reliability, and reduce dependence on power supply voltage.

[Means to solve the problem]

In order to achieve the above object, the logic circuit according to the present invention is composed of Schottky barrier gate type field effect transistors, and has a small number of switching means for switching and outputting a high potential or a low potential according to the input logic level (both are arranged in two or more stages). In this logic circuit, when the output of one switching is at a high potential, the core high potential is clamped to a predetermined constant value, and the current flowing from the output to the next stage switching means is diverted to a predetermined value. A bypass means is provided to bypass the constant power supply.

[For production]

In the present invention, when the output of one switching means becomes a high potential, the high potential is clamped to a predetermined constant value by the bypass means, and the current flowing from the output to the next stage switching means is shunted and bypassed. be done.

Therefore, the current flowing into the switching means at the next stage of response speed is reduced without increasing power consumption, increasing the speed, improving reliability, and reducing the dependence of the high potential output level on the power supply voltage. .

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 is a diagram showing an embodiment of a logic circuit according to the present invention.

First, the configuration will be explained. In the same figure, 11 is 5DFL
The logic circuit 11 has two stages of inverters (switching means) 12a and 12b connected to each other.
Consisting of Here, since the configurations of the inverters 12a and 12b are the same, the members constituting the two will be designated with the symbols a and b, respectively, so that one inverter 12a will be explained and the other will be omitted. . Further, the same reference numerals are given to the same constituent members as those of the conventional example shown in FIG. 2, and the explanation thereof will be omitted.

The inverter 12a has a level shift circuit 5a and an inverting logic circuit 6a, and diodes 13a and 1 are connected between the output of the inverting logic circuit 6a and the power supply line Vss (constant potential).
Bypass means 15a consisting of 4a is connected. That is, the bypass means 15a is connected between the drain and source of the driver FET 7a, and each diode 13
a and 14a are connected in series with their respective cathodes located on the power supply line Vss side. Each diode 13a, 1
Reference numeral 4a is for clamping the voltage level between the drain and source of the driver FET 7a to a potential (clamp potential) that matches the sum of the forward drop voltages of the respective diodes 13a and 14a, and the clamp potential is the same as that of the level shift diode 3b.
The shape and dimensions of each part of the logic circuit 11 may be appropriately determined so that the sum of the forward voltage drop of Vth and the threshold potential (Vth) of the pull-down FET 4b is approximately equal to or greater than the sum. In this case, it is preferable that the specific shapes and dimensions of each component are shown in Table 2 below.

Table 2 However, Lg: gate length Wg: Gate width Vth: threshold voltage Next, the effect will be explained.

Now, when the input signal Din is at H level, the driver FET7a
When the inverter 12a turns on, the output of the inverter 12a becomes L level, and the output signal Dout of the inverter 12b becomes H level. Further, when the input signal Din is at the L level, the output signal Dout of the inverter 12b is also at the L level,
These logical operations are similar to the conventional example.

Here, the present invention is characterized by the operation of the bypass means 15a when the output of the inverter 12a is at H level, and this will be explained in detail below. The output of inverter 12a is H
When the current reaches the level, a current flows from the output of the inverter 12a to the input of the inverter 12b, as in the conventional example.If the inflow current is fin, the current fin is supplied by the inverting logic circuit 6a of the inverter 12a. Further, if the output current of the inverting logic circuit 6a is Iout, the current 1out is determined by the load FET 8a as in the previous Ji. However, when the output of the inverter 12a becomes H level, each of the diodes 13a and 14a becomes conductive, and the output level of the inverter 12a becomes the same as that of each diode 13a.
It is clamped to the forward voltage drop of a and 14a. That is, a part of the current 1ouAt is shunted by the bypass means 15a and bypassed to the power supply line Vss, and the relationship (I o'ut > I in) is established. Here, the current bypassed by the bypass means 15a is I! When it is +, the following formula (■) holds true.

I in= 1out -T th --■ As is clear from the above formula (■), the current 1 in has a smaller value than the current 1 out, and the level decreases due to the decrease in the current flowing through the level shift diode 3b of the inverter 12b, that is, the current 1 in. The time Δt required for charging and discharging the interelectrode capacitance of the shift diode 3b decreases according to the above equation 0. In this case, by bypassing the output current 1out of the inverting logic circuit 6a by the bypass means 15a, the inverter 12
Since the input current of a is reduced by 1 inch, logic circuit 1
1, the power consumption is the same as when the bypass means 15a is not provided. Therefore, the current flowing from the inverter 12a to the inverter 12b can be reduced without increasing power consumption, and the charging and discharging time of the interelectrode capacitance of the hell shift diode 3b is reduced, thereby increasing the speed of the logic circuit 11. be able to.

Further, it is clear that the gate current of the dry FET 7b decreases as the current fin decreases, so that the tendency of electromigration to occur can be lowered, and reliability can be improved.

Furthermore, since the H level output of the inverter 12a is clamped to the forward voltage drop of each diode 13a14a by the bypass means 15a, the power supply line (2). Even if the potential of 0 fluctuates, the H level output of the inverter 12a is hardly affected by the fluctuation, and the dependence of the H level output on the power supply voltage can be reduced.

On the other hand, when the output of the inverter 12a is at the L level, the output level almost matches the potential of the power supply voltage Vss, so the bypass means 15a does not function, and the operation is the same as the conventional one.

(Effects) According to the present invention, when the output of one switching means becomes a high potential, the high potential is clamped and the current flowing from the output to the next switching means is shunted and bypassed. Since the means is provided, it is possible to reduce the current flowing into the next stage switching means without increasing power consumption, increasing the response speed, improving reliability and reducing dependence on power supply voltage. It is possible to reduce the

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a logic circuit according to the present invention, and FIG. 2 is a circuit diagram showing a conventional logic circuit. 1...Logic circuit, 12a, 12b...Inverter (switching means), 15a, 15b...Bypass means.・Koni 11; Logic 0 - orange l/l da E 瀉Kaimigu U consultation B Figure 1

Claims (1)

[Claims] A logic circuit comprising Schottky barrier gate field effect transistors and having at least two stages of switching means for switching and outputting a high potential or a low potential depending on an input logic level, comprising: When the output of the switching means is at a high potential, a bypass means is provided which clamps the high potential to a predetermined constant value and diverts the current flowing from the output to the next stage switching means to bypass it to a predetermined constant power source. A logic circuit characterized in that: