JPH01228036A - Cache memory - Google Patents

Abstract

PURPOSE:To make unusable only ways including defective bits and to function only with ways having normal bits by providing a means to show whether respective ways are effective or ineffective for respective ways. CONSTITUTION:A checking bit 13 is provided for respective ways. Respective checking bits 13 are connected with an address tag comparator 8 of the corresponding way and connected with an LRU bit memory 12. As the result of testing, when a defective bit is discovered, the checking bits 13 of the way including the defective bit are ineffectively set by a laser cut, etc., from an external part. The address tag comparator 8 is controlled so as not to output a hitting signal. Thus, an address tag memory 5 of the way to set the ineffectiveness can be removed from the referring object at the time of deciding the hitting.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory, and particularly to a set associative type cache memory having multiple ways.

[Background Art] Cache memory has emerged as an effective means for realizing high-speed memory as microprocessors enter the era of full-fledged high-speed microprocessors.

The access time to main memory has a significant impact on system performance. The speeding up of microprocessors is
Although there is an inevitable need to shorten memory access time, the demand has recently exceeded that of improving the performance of DRAM chips used in main memory.

Furthermore, it is becoming difficult to shorten memory access time not only due to the performance of DRAM chips but also due to the expansion and diversification of system scale, such as the configuration of multiprocessor systems.

One way to solve this problem is to hierarchize memory. One of them is a cache memory method.

For example, as shown in FIG. 2, the cache memory method stores data in a frequently used area of the main memory 2 in a high-speed buffer in response to a request from the CPU 1.
This method stores the data in a cache memory 3, which is a memory, and reads/writes the data at high speed in place of the main memory 2 when accessed by the CPU 1.

The cache memory 3 does not store fixed data, but the area of the main memory 2 that stores data changes in response to requests from the CPUI.

However, there is locality in the memory access area from the CPUI in data processing. Therefore, the CPU
The data retrieved from the main memory 2 and stored in the cache memory 3 in response to a request from I is likely to be accessed for some time thereafter. Therefore, once the data in the main memory 2 is stored in the cache memory 3, the effect of high-speed memory is exhibited, and the memory of the CPU 1
(No wait) is realized without waiting time for access. That is, the CPUI does not have its processing operations delayed by memory access time.

As CPU processing progresses, the memory access area moves. Accordingly, cache memory 3
Then, the area of the main memory 2 to be stored is also switched. However, if the evicted area is accessed again, the cache memory 3 will need to be replaced again.
If this happens frequently, system performance will deteriorate.

Generally, the hit rate is used to indicate the effectiveness of the cache memory 3. The hit rate is the probability that data in the access area exists in the cache memory 3 in response to a memory access from the CPUI. If it exists, it is called a hit; if it does not exist, it is called a cache miss.

In the case of a cache miss, a chunk of data including the word of the requested address from the CPUI is fetched from the main memory 2 to the cache memory 3 in preparation for the next CPU access. This chunk of data is called a data block.

The hit rate of the cache memory 3 does not simply increase as the capacity increases, but it largely depends on the configuration of the cache memory. An example of increasing the hit rate is an N-way set associative method.

Figure 3 shows Interface August 1987 issue No. 1.
23 is a block diagram showing a four-way set associative cache memory shown on page 250 of No. 23; FIG. In the figure, a CPUI request address 4 is divided into an address tag 4a, a set select 4b, and a word select 4c and input to the cache memory. Address tag 4a is provided to address tag comparator 8. The set/select 4b is the address/tag memory 5. Data memory 7 and LRU bit memory 12
given to. Word select 4C is applied to word selector 9. The address/tag memory 5 is already CP
It stores a plurality of address tags for address 4 requested by the UI. The data memory 7 also stores data blocks that have already been read out from the main memory 2 (for example, 4
It stores multiple words (consisting of words).

The address/tag memory 5 and the data memory 7 have corresponding address spaces, each storing an address tag of an address forming a corresponding storage area and a data block read from the main memory 2 according to the address. . Address/tag memory 5 and data memory 7
Access is performed based on set select 4b. That is, the address/tag is retrieved from the storage area of the address/tag memory 5 selected by the set/select 4b.
The tag is read and applied to address tag comparator 8. Further, the data block is outputted from the storage area of the data memory 7 selected by the set select 4b and applied to the word selector 9. The word selector 9 selects one or more words from a plurality of words included in one data block based on the applied word select 4c and provides the selected words to the way selector 1o.

On the other hand, the address tag comparator 8 compares the address tag 4a of the address 4 currently requested by the CPU with the address tag read from the address tag memory 5, and determines whether they match or not. Detect. If there is a match, the address/tag comparator 8 derives a hit signal and applies it to the way selector 1°.

By the way, since the cache memory shown in FIG. 3 is of a 4-way set associative type, the address/tag memory 5. Data memory 7, address/tag comparator 8.
The word selector 9 and the way selector 10 are each provided for four ways. Therefore, the address
The tag memory 5 and the data memory 7 can simultaneously store up to four address tags and data blocks for each set address fixed by the set type select 4b. Further, since each way performs the same operation in parallel, four address tags are simultaneously referenced for a set address when determining a hit. That is, the address tag comparator 8 simultaneously compares the address tag of each way read from the address tag memory 5 with the address tag 4a of address 4 currently requested by the CPUI. and determines hits/cache and misses.

On the other hand, in the data block of each way read from the data memory 7, a word is selected by the word selector 9, and finally the way selector 10 receives a way selection signal from the address/tag comparator 8 indicating which way has been hit. , one or more words are determined and routed to the output data bus 11.

As mentioned above, if there is a hit, the data is immediately read from the cache memory 3 and used by the CPUI, but
In the case of a cache miss, access to the main memory 2 is executed using address 4, and data is read from a predetermined area of the main memory 2 and used. At this time, data is replaced in the cache memory 3, and the address tag 4a of the address 4 used for access and the data block read from the main memory 2 are stored in the address tag memory 5 and the data memory 7, respectively. written. At the time of this data replacement, the LRU bit memory 12
It controls in which way the address/tag memory 5 and data memory 7 are to be rewritten according to the ed algorithm.

[Problems to be Solved by the Invention] In the conventional set-associative type cache memory as described above, if even one defective bit exists in the address/tag memory 5 or the data memory 7, there is a risk of malfunction. . Therefore, before using a cache memory, a test is performed, and if even one bit is found to be defective, the cache memory is treated as a defective product, and the entire cache memory must be replaced. As described above, conventional cache memories have had the problem of extremely low yield.

This invention was made in order to solve the above-mentioned problems, and even if there is a defective bit, it is possible to prevent malfunctions caused by it, and as a result, it is possible to make a defective product into a non-defective product. The purpose is to provide memory.

[Means for Solving the Problems] The cache memory according to the present invention is provided with means for indicating whether each way is valid or invalid, and when the means is set to a state indicating invalidity, This method does not use the way.

[Operation] In this invention, by providing a means for indicating whether each way is valid or invalid, only ways containing defective bits are made unusable, and only ways having normal bits are made to function. I have to.

[Embodiment] FIG. 1 is a block diagram showing a 4-way set contention associative cache memory according to an embodiment of the present invention. The configuration of this embodiment is the same as the conventional example shown in FIG. 3 except for the following points, and corresponding parts are designated by the same reference numerals and their explanations will be omitted. A feature of this embodiment is that a check bit 13 is provided for each way. This check bit 13 indicates whether the corresponding way is valid or invalid, and can be set by, for example, laser cutting. The check bit 13 of each way is connected to the address and tag comparison 258 of the corresponding way, and is also connected to the LRU bit memory 12.

In the above configuration, for example, if it is discovered through a test that a defective bit exists in the address/tag memory 5 or data memory 7 of a way, the check pit 13 of the way containing the defective bit is laser cut from the outside. etc., it is set to invalid. The address/tag comparator 8 of the way whose check bit 13 is set to be invalid will not respond even if the address tag 4a of the currently requested address 4 matches the address tag read from the address/tag memory 5. , is controlled so as not to derive a hit signal. Such control can be achieved very easily by providing a gate means that prohibits the derivation of the hit signal by the invalid setting output of the check pit 13, for example. As a result, the address/tag memory 5 of the way set as invalid in the check pit 13 can be removed from the reference target at the time of hit determination. On the other hand, even if a data replacement request is generated in the cache memory due to a cache φ miss, the LRU bit memory 12 always excludes ways set as invalid in the check pit 13 from data replacement detection. by this,
Address tags and data blocks are no longer written to ways that are set to be invalid by the check pit 13.

As is clear from the above description of the operation (in the embodiment shown in FIG. 1, check pick), the way set as invalid in 1B becomes unusable, and the cache memory operates only with other normal ways. Therefore, even if a defective bit exists, by setting the way to be invalid in the check pit 13, the cache memory can function normally.

In the above embodiment, a 4-way set associative cache memory has been described, but the present invention can be applied to a set associative cache memory having an arbitrary number of ways.

Further, in the above embodiment, the check pit 13 is set by laser cutting, but a self-test circuit that tests the cache memory in a test mode may be provided inside the cache memory chip. The check pit 13 of the way including the method can be fixed invalidly inside the chip.

[Effects of the Invention] As described above, according to the present invention, by disabling a way containing a defective bit discovered during a test, only that way is made unusable, and only a way having only normal bits can be used. Since the cache memory can be made to function, products that were conventionally treated as defective can be made into good products, and as a result, yield can be improved.

4. Brief Description of the Drawings FIG. 1 is a block diagram showing a 4-way Φ set associative type cache memory according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a processor system using a cache memory.

FIG. 3 is a block diagram showing a conventional 4-way set associative type cache memory.

In the figure, 1 is a CPU, 2 is a main memory, 3 is a cache memory, 4 is an address, 4a is an address tag,
4b is set select, 4c is word select, 5
1 is an address/tag memory, 7 is a data memory, 8 is an address/tag comparator, 9 is a word selector, 10 is a way selector, 12 is an LRU bit memory, and 13 is a check pit.

Claims (1)

[Claims] In a set-associative cache memory having multiple ways, means is provided for each way to indicate whether each way is valid or invalid, and when the means is set to indicate invalidity, the It is characterized by not using a way,
cache memory.