JPH01227268A - Filing device - Google Patents

Abstract

PURPOSE:To contrive the synchronization of the transfer of data by generating a signal to operate an interface part synchronously with a recording and reproducing part. CONSTITUTION:The data on a memory 33 are transferred to an interface circuit 34 through a data bus 34, parallel/serial-converted and recorded by a recording and reproducing part 1. The data reproduced by the reproducing part 1 are serial/parallel-converted by the circuit 10 and stored in the memory 33. An interface control circuit 20 is equipped with an address decode circuit 21, an I/O timing control circuit 22 and a timing control circuit 23 and controls the operating timing of the circuit 10. Thus, by generating the synchronizing signal to transfer the data synchronously with the operation of the recording and reproducing part only at a data transfer interval, the data are transferred completely synchronously.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a file device that transfers data to and from a recording medium.

(Conventional technology) In systems using computers, etc.

Various recording media are used to enable recording, reproduction, and erasure of large amounts of data. In such a system, a file device is formed by a recording/reproducing means in a format suitable for the type of recording medium, a computer, etc., and data is exchanged between the computer and the recording medium. ing.

For example, in a file device using a compact cassette as a recording medium, a synchronization character is inserted at the beginning of a file recorded on the recording medium. When reading data, the file device uses this synchronization character as a clue to detect the beginning of the file and reads the data within the file.

(Problems to be Solved by the Invention) Usually, a plurality of files are often recorded on one recording medium. Therefore, if the file device starts detecting a synchronization character from the middle of a file, and the same data as a synchronization character exists in the file, the file device will determine that the data is a synchronization character. , and it is treated as if a file exists after that data. As described above, conventional file devices may not be able to perform normal data reading operations.

Furthermore, when using a synchronization character, a synchronization means 2, such as a serial communication LSI, is required, which is equipped with a complicated circuit to synchronize and convert the parallel data to be recorded supplied from the computer into serial data. be.

Therefore, there is a problem that the configuration of the file device becomes complicated and the device becomes expensive.

Furthermore, the timing of recording data to or reading data from a recording medium by a file device.

In order to synchronize the timing of data transmission and reception by the computer, special software such as B1-5 sync is required.

The present invention was made in view of the current situation, and
The purpose of this is to enable normal data recording and playback regardless of the file detection start position, even when multiple files are recorded on the same recording medium, and to ensure that the configuration is consistent. It is an object of the present invention to provide a file device that is simple and allows complete timing synchronization without using special software.

(Means for Solving the Problems) A file device of the present invention records data on a recording medium,
and a recording/reproducing section that reproduces recorded data.

Parallel data to be recorded supplied from the outside is converted into serial data and transmitted to the recording/reproducing section.

an interface unit that receives the serial data reproduced by the recording/reproducing unit, converts it into parallel data, and sends it to the outside; and a synchronization signal for operating the interface unit in synchronization with the operation of the recording/reproducing unit. a timing generation section that generates a timing based on a signal output from the reproduction section, and the interface section transmits and receives serial data in units of words containing a predetermined number of bits to and from the recording and reproduction section according to the synchronization signal. It is a device that performs
This achieves the above objective.

(Example) The present invention will be described below with reference to Examples.

FIG. 1 shows a block diagram of an embodiment of the present invention.

The file device of this embodiment includes a recording/reproducing section 1. It has a timing generation logic 7, an interface circuit 10, and an interface/ζ\ control circuit 20.

The interface circuit 10 and the interface control circuit 20 constitute an interface section.

Interface circuit 10 and interface control circuit 20 are connected to a system bus (including data bus 34, address bus 35 and control bus 36) of computer system 30, which includes a microprocessor 31.degree. DMA controller 32 and memory 33. The data on the memory 33 is transferred to the interface circuit 10 via the data bus 34, subjected to parallel/serial conversion by the interface circuit 10, and recorded by the recording/reproducing section 1.

The data reproduced by the recording/reproducing section 1 is serial/parallel converted by the interface circuit 10 and stored in the memory 33. The interface control circuit 20 controls the operation timing of the interface circuit 10.

In this embodiment, an R-DAT (rotary head type digital audio tape recorder) used in audio recording and reproducing devices is used for the recording and reproducing section 1. R-
A DAT uses a rotating drum equipped with two magnetic heads to record data on tracks formed on a magnetic tape at a predetermined angle with respect to the tape running direction.

The recording format is schematically shown in FIG. Each track 41 on the magnetic tape 40 has two subcode areas 42 in which control information during playback, sub-channel signals, etc. are recorded, two ATF areas 43 in which tracking control information is recorded, and these areas. It has a PCM area 44 sandwiched between the ATF area and in which data is recorded.

The R-DAT drive 2 is a unit having a rotary head, a tape drive motor, etc. for recording and reproducing data on a magnetic tape. Error correction circuit 3 is R
- It is connected to the DAT drive 2, and includes a circuit for error correction during reproduction, as well as a tracking circuit, a hand amplifier, a circuit for controlling interleaving, and the like.

Servo circuit 4.

R-DAT Controls the drive mechanism of the capstan and rotating drum of the drive 2. The A/D and D/A interface 5 is a serial data input/output section.

Input serial data (TxD) is D/A converted by A/D and D/A interface 5 and sent to R-DAT.
Sent to drive 2. Furthermore, the data reproduced by the R-DAT drive 2 is A/D converted by the A/D and D/A interface 5 and sent out as output serial data (RxD). The mechanical control 6 controls the mechanical part of the R-DAT drive 2 based on the sensor signal from the R-DAT drive 2, and also controls the subcode.

The timing generation logic 7 generates a word pulse (to be described in detail later) based on a signal sent from the error correction circuit 3 or the like.
field).

The interface circuit 10 has various registers for performing serial/parallel and parallel/serial data conversion. 16bit shift register 11
is a transmission register for converting recording data from parallel to serial and sending it to the A/D and D/A interface 5. The 16-bit parallel register 12 is a transmission buffer that temporarily stores recording data to be sent to the shift register 11. The 16-bit shift register 13 is A
/D and D/A These are reception registers that perform serial/parallel conversion on reproduced serial data sent from the interface 5. The 16-bit parallel register 14 is a receiving buffer that temporarily stores parallel data output from the shift register 13. parallel register 14
The data is read onto the data bus 34 by the three-state buffer 15. The 16-bit number configuration circuit 16 is a circuit that compares the data on the memory 33 and the data recorded by the R-DAT drive 2 and confirms that they match.

The interface control circuit 20 includes an address decoding circuit 21 . I10 timing control circuit 22. and a timing control circuit 23. The address decoding circuit 21 is a circuit for identifying a device number sent to the address bus 35 by the microprocessor 31 and specifying a single file device. The I10 timing control circuit 22 transmits a write signal and a read signal to the recording/reproducing section 1, and also supplies a signal indicating the data transfer timing to the interface circuit 10.

Is the timing control circuit 23 D? This is a circuit for matching the timing of the IA and the operation timing of the microprocessor 31.

FIG. 3 shows a timing chart of data transfer during recording and reproduction in the file device. Figure 3 (A) shows signals used during recording and playback, and Figure 3 (A) shows signals specific to recording.

The same figure (c) shows the signal peculiar to the reproduction|regeneration.

Each signal will be briefly explained. BCK (bit clock) is a clock for bit synchronizing serial data during recording/reproduction. BCK is obtained by dividing the reference clock provided in the timing generation circuit in the error correction circuit 3 during recording.
It is output to the timing generation logic 7 via the A/D and D/A interface 5. During reproduction, the demodulation circuit in the error correction circuit 3 distinguishes the reproduced data from the reproduced data and outputs it via the A/D and D/A interface 5.

BCK is also applied to shift registers 11 and 13, and shift registers 11 and 13 transmit and receive serial data in synchronization with BCK. -CM (word clock) has a period 32 times that of BGK, and switches from H level to L level or from L level to H level every 168 CK. -CM is output from the interleave circuit in the error correction circuit 3, and may output serial data (TxD) when it is at H level.

Alternatively, it indicates that serial data (RxD) may be imported. DIJCKI and DLWCK2 are signals in which W(J is delayed by 2ABCK and 31BfJ, respectively, in the timing generation logic 7.The correction (start signal) is a signal obtained by delaying REC/J from the microprocessor sensor 31 when accessing the file device. Based on the activation command given together with the PLAY signal, it is generated by the I10 timing control circuit 22 and supplied to the timing generation logic 7.

During reproduction, based on the detection of the ATF (see FIG. 2) by the ATF sync detection circuit in the error correction circuit 3, the signal is supplied to the timing generation logic 7 at the start of reproduction of each track. During recording, EXSYN is generated by the error correction circuit 3 at the start of recording of each track.

The signal is supplied to the timing generation logic 7. EN is a signal generated from other signals inside the timing generation logic 7, and indicates that data transfer is possible when the level is H.

The beans are generated by a logic circuit within the timing generation logic 7, as described below. The timing of data transfer is determined by the trick. Rain is a DMA request signal from the timing control circuit 23.

DACK is an acknowledgment signal from the DMA controller 32.

Dn++ TxB, TxR and TxD are only related to recording. Dn+ is the data on the data bus 34 that is input to the parallel register 12, TxB is the data held by the parallel register 12, TxR is the data held by the shift register 11, and TxD is the serial data output from the shift register 11. It is.

RxD, RxB and Dnz are only related to playback.

RxD is serial data input to the shift register 13, RxB is data held by the parallel register, and Dnz is data read from the 3-state buffer 15 onto the data bus 34.

Signals during recording will be explained using FIGS. 3(a) and 3(b). During recording, after ■ becomes L and EXSYN becomes L, the IBCK interval becomes L in synchronization with the rising edge of WCK (El in Figure 3), and 1) rack recording is started. DM^ is activated by sending a DRQ from the timing control circuit 23 to the DMA controller 32 at the rising edge of A (E2). The DMA controller 32 transfers the first one from the memory 33 to the data bus 34.
A word, that is, 16 bits of data a is read out, and a picture is output. Data a is latched into the parallel register 12 when DACK rises (E3). At the first rise of DLWCKI after τ goes low, EN goes high (E4). next.

While DLWCK2 is H and enemy CK is L, the beans become L (ES). Data a is taken into the shift register 11 at the rising edge of WP and shifted in synchronization with BCK.

Outputs one bit at a time. The next DMA is activated by the above-mentioned WP (Es), and transfer of the second one word of data b is started. Data b is 9th when WP becomes L (
E,) is converted into serial data and output from the shift register 11.

Signals during reproduction will be explained using FIGS. 3(A) and 3(C). Even during playback, from BCK to E in Figure 3 (a)
The signals up to N are the same as those during recording.

One word of data d is serially output from the A/D and D/A interface 5 in synchronization with the rising edge of W (J) (E7).
3, DLWCK2 becomes L, and the IBCK interval until WCK becomes L becomes L (E8). Data d converted into parallel data by the shift register 13 is latched into the parallel register 14 at the rising edge of -P. At the same time, DMA is activated,
Data d is transferred from the 3-state buffer 15 to the memory 33.

FIG. 4 shows a logic circuit for generating word pulse marks. This logic circuit is an AND game) ANI~AN5.

NAND gate NAI ~NA4. NOR gate NO
I~N03.

It includes NOT gates NTI to NT7, 8-bit serial input/parallel output shift registers SRI and Si20, and a down counter CTI. shift register S
RI inputs a signal obtained by inverting WCK by NOT gate NT5, shifts the input signal using BCK, and outputs a signal DLWCKI in which WCK is delayed by 24 BCK. Shift register SR2 is
It takes DIJCKI as an input and generates a signal DLWCK2, which is WCK delayed by 31 BCK. The presettable down counter CTI switches the position of the word pulse (last) during recording and playback. The preset value is 1 during recording and 3 during playback. A countdown is performed, and when all of the output terminals Q0 to Q3 become O, the output terminal "'0" becomes H.

REC/PLAY is set to H during recording. When corrected and EXSYN becomes L, NOR gate NO2 becomes H. Therefore, AND game 1- AN3 is
W (becomes H from the rise of J to IBCK, and God becomes L during that time.

This is designated El in FIG. Next, EN becomes H at the rising edge of DLWCKI output from the shift register SRI. Once EN goes high, it is kept in the high state by NAND gates NAI and NAND gate NA3. By EN becoming H, AND
Gate AN2 becomes H. Enemy GK = L, DLWC
When K2=H, AND gate AN5 becomes H, and the third
Word pulses (sub) shown as E and E6 in the figure are generated.

During playback, REC/PLAY is set to L. Therefore.

When WC=H and DIJCK2=L, the AND gate 8N becomes H, and the word pulse shown by Ha in FIG. 3 is generated.

(Effects of the Invention) As described above, the file device of the present invention generates a synchronization signal for performing data transfer in synchronization with the operation of the recording/reproducing unit only in valid data transfer intervals without using synchronization characters. , data transfer can be performed completely synchronously. Therefore, it is possible to transfer data without using synchronization characters, and even if a plurality of files are recorded on the same recording medium, the data can be reliably read. Moreover, since the file device of the present invention can be synchronized using only the above-mentioned synchronization signal, it does not require any special synchronization means or synchronization software used in conventional devices, and can be easily configured. Yes, the equipment is cheaper. In the present invention, although the configuration of the recording/reproducing section of the file device is not particularly limited, the present invention is applicable to a recording/reproducing system using a magnetic tape as a recording medium capable of handling a large amount of data, especially an R-D.
Application of the present invention to a file device that uses an AT as a recording/reproducing section is particularly advantageous.

Figure 1 is a block diagram showing an embodiment of the present invention and a computer system to which it is connected, and Figure 2 is an R-DAT.
FIG. 3 is a timing chart for recording and reproducing data in the above embodiment, and FIG. 4 is a logic circuit that generates word pulses (snores). It is a diagram.

1... Recording and reproducing section, 7... Timing generation rosinc.

DESCRIPTION OF SYMBOLS 10... Interface circuit, 20... Interface control circuit, 30... Computer system.

that's all

Claims (1)

[Claims] 1. A recording and reproducing unit that records data on a recording medium and reproduces the recorded data, and a recording and reproducing unit that converts parallel data to be recorded supplied from the outside into serial data and transmits it to the recording and reproducing unit. an interface unit that receives serial data reproduced by the converter, converts it into parallel data, and sends it to the outside; and outputs a synchronization signal from the recording and reproducing unit to operate the interface unit in synchronization with the operation of the recording and reproducing unit. a timing generation unit that generates data based on the synchronization signal, and the interface unit transmits and receives serial data in units of words containing a predetermined number of bits to and from the recording and reproducing unit according to the synchronization signal. .