JPH01226211A - Clock pulse generation circuit - Google Patents

Abstract

PURPOSE:To improve resolution and measurement precision by providing a liquid crystal oscillation circuit which always generates a clock pulse measuring the time interval of a measurement gate having the connection of timing with a synchronizing signal and a control circuit which controls the output signal level of the liquid crystal oscillation circuit since impedance changes due to the energization of the synchronizing signal. CONSTITUTION:In a clock pulse generation circuit, the synchronizing signal outputted from a synchronous circuit 1 is supplied to a measurement gate generation circuit 2, etc., and it controls the timing of the action of a whole system, whereby it is simultaneously supplied to the base circuit of a second semiconductor 6 generating a control circuit 5. The base current of the liquid crystal oscillation circuit 3 is controlled by the action of the second semiconductor 6. Namely, the emitter of the second semiconductor 6 comes to a level H and a large base current flows in a first semiconductor 4 through a resistor R2 when the synchronizing signal is in the level H. When a counting action is not executed on the other hand, the synchronizing signal is held in a level L and the liquid crystal oscillation circuit 3 oscillates at the low level, whereby consumption power is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used, for example, to measure the propagation time of radio waves, ultrasonic waves, etc., or to generate a pulse pulse.

In particular, it concerns power saving and the generation of clock pulses that are asynchronous with the measurement gate.

[Prior Art] Figure 3 is a circuit diagram showing an example of a conventional clock pulse generation circuit, in which 2 is a measurement gate generation circuit that generates a gate signal related to the propagation time of radio waves and ultrasonic waves, and 2 is a crystal generator. circuit, 4 is a crystal oscillation circuit, a is formed by a first flat conductor, 7 is a crystal oscillator,
8 is a resonant circuit adjusted to the oscillation frequency of the crystal oscillation circuit; 10 is an AN[) circuit; 11 is a counter for counting clock pulses; 12 is a transformer forming the resonant circuit 6;
R2 is a resistor, and C and Go are capacitors.

The conventional L1 pulse generation circuit is constructed as described above, and includes a first semi-power body 4, a resonant circuit 8 consisting of a crystal oscillator 7.1 to a lance 12, a dopasitor Co, and a capacitor C.
By forming a Lupitz-type crystal oscillation circuit, constant frequency and constant amplitude pulses are generated and outputted via a transformer 12. Measuring circuit 2
The measurement gate and clock pulse 1 are A No
The logical product of both signals applied to the circuit 10, that is, the clock pulse selected by the measurement gate is counted by the counter 11, and the propagation time is measured. The first semiconductor 4 continues to oscillate even when the counter 11 does not count the number of clock pulses (h1). or get bigger.

In particular, if the frequency of the clock pulse is increased in order to improve the resolution of the counter 11, the above-mentioned edge will increase significantly.

Figure 4 is a circuit diagram showing another example of the conventional clock pulse generation circuit.
o is the same as the conventional circuit described above, 1 is a synchronous circuit that outputs a synchronous signal 111 that determines the timing of radio wave or ultrasonic radiation, and 13 is a synchronous circuit that is operated by the synchronous circuit 1 and is connected to the crystal oscillation circuit 3 that includes the first semiconductor 4. There is a switch that controls the power supply.

The conventional clock pulse generation circuit is constructed as described above, and power is supplied to the crystal oscillation circuit including the first semiconductor 4 via the switch '13 which is operated by the synchronization signal from the synchronization circuit 1. When the counter '11 is in operation, the crystal oscillator circuit 3 is in operation and paused to reduce the power consumption, or the crystal oscillator circuit outputs a pulse pulse and synchronization from the synchronization circuit 1. A constant phase relationship is formed between 'I'jj jj, and since the phase of the measurement group i~ is also related to the synchronization signal, the phase relationship between these phases q is constant.

Therefore, if sampled at multiple measurement gates, l'
It is impossible to measure the resolution and measurement accuracy of the h1 measurement button obtained from one cycle of the l clock pulse.

[Invention or Problem to be Solved] In the above J, conventional glue [-1 Tsuta pulse oscillation 41- circuit], does the crystal oscillation circuit product using the first semiconductor 4 constantly oscillate? Since it outputs a high clock pulse, the counter 11
If it is not counted, a pulse is applied to the logic element, increasing power consumption.

Furthermore, power consumption is gradually reduced by controlling the opening and closing of the power supply to the crystal oscillator circuit in synchronization with the synchronization signal, but since the synchronization signal g, the measurement gate, and the clock pulse have a fixed phase relationship with each other, the measurement signal g Even if we increase the sampling frequency of tarokku pulses by ~ and calculate the measurement data from the average value,
There was a problem that a predetermined resolution and measurement accuracy could not be obtained.

This invention was made to solve this problem, and the output signal level of the crystal oscillator circuit product is adjusted to a high level when the counter is in the warm-up operation, and is kept at a low level when the h1 number operation is not performed. The constant oscillation operation is maintained and the synchronization (
The purpose is to obtain a clock pulse generation circuit that has a phase relationship with the U and measurement gate L-1 tsuta pulses that is asynchronous with each other, improving resolution and measurement accuracy, and reducing power consumption [To solve the problem] Means 1 The clock pulse generation circuit according to the present invention includes a crystal oscillator circuit that constantly generates a clock pulse for measuring the time interval between the measurement gates related to the timing of the synchronization signal, and a crystal oscillation circuit whose impedance changes depending on the (=J force) of the synchronization signal. A control circuit for adjusting the output signal level of the crystal oscillation circuit is provided.

[Function 1] In this invention, since the impedance of the base circuit of the first semiconductor forming the crystal oscillation circuit is changed by the control circuit activated by the signal of the synchronous circuit, the light of the crystal oscillation circuit ( The signal level of the output or clock pulse is adjusted.

Accordingly, the cock pulse can be at a high level when performing force r kunta or classical movements, and can be at a low level during other J3 operations, so power consumption can be reduced even if it is constantly oscillated. Since the phase relationship with the clock pulse can be made asynchronous with each other, the resolution and measurement accuracy can be further improved by increasing the frequency of the clock pulse, sampling it with multiple measurement gates, and not averaging the clock pulses. can.

[Embodiment] An embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, 1, 2. Dan, 4, 7, 8, 10° 11, R
2, C, and Co are the same as the conventional circuits mentioned above, and each is a control circuit that controls the output signal level of the crystal oscillation circuit product at the timing of the synchronization signal, and 6 is a second semiconductor that operates according to the positive force of the synchronization signal. , 9 is a diode for limiting the output signal amplitude of the crystal starting circuit, and R1 is a resistor provided in the base circuit of the first semiconductor 4.

Figure 2 shows an example of the operating waveforms of this invention, where ■ is the synchronization signal output from the synchronization circuit 1, ■ is the body side gate, ■ is the clock pulse output from the crystal oscillation circuit, and ■ is the measurement group.
Closing clock pulses selected from 1 to 3 indicate the threshold value for identifying the output level of the clock pulse.

The clock pulse generation circuit configured as described above is configured such that the synchronization (M'tv) output from the synchronization circuit 1 is supplied to the measurement pulse generation circuit 2, etc., and controls the timing of the operation of the entire system. the second forming the circuit 5;
It is supplied to the base circuit of the semiconductor 6.

The operation of the second semiconductor 6 controls the base current of the crystal starting circuit. That is, when the synchronization signal (■) is at Torbel, the emitter of the second cliff assembly 6 is at 1 Lebel, and a large base current flows through the resistor R2 to the first semiconductor 4, so that the output signal level of the crystal oscillator circuit and sword becomes low. becomes so large that the amplitude exceeds the threshold value (■) of the AND circuit 10.

On the other hand, when the synchronization signal ■ is at the trubel level, the second semiconductor 6 is turned off, and the base current of the first semiconductor 4 is supplied through the series circuit of resistors R1 and Rz, so the base current is small. Become.

Therefore, the output signal level of the crystal oscillator circuit product C1 at this time becomes so small that it does not exceed the threshold value (2) of the AND circuit 10, so that it is not output. However, the base current value of the crystal oscillation circuit formed by the first semiconductor 4 is adjusted so that the oscillation effect is maintained at all times.

The AND circuit 10 generates a counter 11 by the logical product of the oscillation output signal amplitude-modulated via the second semiconductor 6 by the synchronizing signal ■, that is, the 1'' pulse ■ and the measurement gate ■.
When the count is 1, a counting clock pulse (2) is formed. The measurement gate ■ is controlled so that the synchronization signal ■ is generated at the timing of the torque, so the gates of measurement goo 1 to ■ =
9- When performing a word count operation using a clock pulse to measure the width, the crystal oscillation circuit product is always in a high-level oscillation state, and the clock pulse ■ at that time exceeds the threshold value ■ of the logic circuit. The word count operation of measurement gate ■ is possible.

--'lj, When no counting operation is performed, the synchronizing signal ■ is kept at the [- level, and the crystal oscillation (the dragon circuit) oscillates at a low level, and the oscillation does not exceed the threshold value ■ of the logic circuit. This becomes the output clock pulse ■.Therefore, at this time, the power consumption of the crystal oscillator 7 is also reduced, and the logic circuit that receives the signal does not exceed the 'bb threshold ■, so the current will no longer flow. The power consumption of the clock pulse generation circuit can be reduced.

The phase relationship of the synchronous circuit 1 is that the clock pulse ■ is constantly oscillating at the frequency and phase unique to the crystal oscillator 7, so it is random and the h1 number clock pulse ■ corresponds to the time of the measurement gate ■ multiple times. It is expected that the resolution and viscosity of the measured data will be improved by counting.

Furthermore, without increasing the frequency of the second pulse (2), the resolution and accuracy can be increased by -.

This invention uses radio waves and ultrasonic waves to measure measurement gates related to propagation time, i.e., to measure the distance to an object, the thickness of the object, etc. (J-method measurement, measurement of the moving speed of the object, etc.) I'm using it too much.

Instead of the crystal oscillator circuit, it generates a constant frequency signal.
The same effect can be achieved using a conventional oscillation circuit.

[Effects of the Invention] As described above, the present invention can be realized by a simple circuit that includes a cf'3 [1 pulse] generation crystal oscillation circuit and a control circuit for adjusting the output signal level of the crystal oscillation circuit. Since the bias current of the first semiconductor forming the crystal oscillator circuit is controlled by the synchronizing signal applied to -C through the second semiconductor, the output signal level of the crystal oscillator circuit is adjusted3, so that the counter The reason for outputting a high level signal when counting clock pulses and a low level signal at other times is to reduce the power consumption of the clock pulse generation circuit.

In addition, the crystal oscillator circuit is always continuously excavated, and the phase relationship between the clock pulse, the synchronization signal, and the measurement gate is asynchronous. By averaging 11p, the resolution and accuracy of the measurement data can be further improved.
However, increasing the frequency of the clock pulse has the effect of further improving resolution and accuracy.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is an example of the operating waveforms of the present invention, Fig. 3 is a circuit diagram showing an example of a conventional clock pulse generation circuit, and Fig. 4 is a circuit diagram showing an example of the conventional clock pulse generation circuit. Conventional glue
FIG. 7 is a circuit diagram showing another example of a one-pulse generation circuit. In the figure, 1 is a synchronous circuit, 2 is a measurement gate generation circuit,
1 is a crystal oscillation circuit, 4 is a first semiconductor, 5 is a control circuit, and 6 is a crystal oscillation circuit.
is a second semiconductor, 7 is a crystal resonator, 8 is a resonant circuit, 9 is a diode, 10 is an AND circuit, 11 is a counter, R1,
R2 and R3 are resistors, and C and Co are capacitors. The same reference numerals in each figure indicate the same or corresponding parts. Patent applicant Tokyo Co., Ltd. R4 equipment rf)l L
fl-Otori Saθ @ ■ ■

Claims (1)

[Scope of Claim] A clock pulse generation circuit that uses clock pulses to measure the time interval of measurement gates that are generated in synchronization with a synchronization signal, comprising: a crystal oscillation circuit that constantly generates clock pulses; and energization of the synchronization signal. A clock pulse generation circuit comprising: a control circuit that adjusts an output signal level of the crystal oscillation circuit by changing impedance, and wherein the synchronization signal and the clock pulse are asynchronous.