JPH01226067A - Hierarchical multiprocessor data transfer method - Google Patents

Abstract

PURPOSE:To speed up data transfer between separated hierarchical processors by providing respective processors with by-pass switches in a hierarchical type multiprocessor system. CONSTITUTION:At the time of starting a processor group in a 3rd layer, a host 11 turns on the by-pass switches 3 of the processors in 1st and 2nd layers through a control bus 6. Since the processor of the 3rd layer is directly connected to a data bus 5 through the by-pass switches 3 of the processors of the 1st and 2nd layers, a starting program can be directly transferred through the data bus 5. Thereby sequential data transfer for transferring data from the host to the 1st layer processor and from the 1st layer processor to the 2nd layer processor can be omitted and data transfer can be rapidly executed.

Description

[Detailed Description of the Invention] [Summary] Regarding a data transfer method for transferring data to processors constituting a hierarchical multiprocessor, a bypass switch is provided in each processor to bypass a communication path between an upper layer and a lower layer. , the purpose is to transfer data directly to the corresponding processor and perform the transfer process N times and quickly.In addition to connecting multiple processors in a hierarchical structure through communication paths, communication paths are installed in upper and lower layers within each processor. A bypass switch is provided for bypassing between the lower processor and the lower processor.
0FF control so that data can be transferred all at once to all lower processors, all processors in a predetermined hierarchy, or directly to a designated processor in a designated hierarchy.

(Field of Industrial Application) The present invention relates to a data transfer method for transferring data to processors forming a hierarchical multiprocessor.

[Problems to be solved by conventional technology and invention] Conventionally,
A hierarchical multiprocessor system has a structure as shown in FIG. Each processor 12 has a local memory (primary memory) and is connected to the upper and lower layer processors 12 by a communication path 13. Here, when the host 11 starts up, for example, a group of third-layer processors, it is necessary to download (IPL) a program to these processors 12.

For this download, first, the host 11 downloads and boots to the first layer processor 12, then this processor 12 downloads, loads and boots to the 2Nth processor 12, and then the second layer The third layer processor 12 downloads the data to the third layer processor 12 and starts it.

For this reason, there is a problem in that when the number of stages of 1illi increases, processing such as initialization becomes complicated and requires a lot of time.

The present invention aims to provide a bypass switch in each processor that bypasses the communication path between the upper layer and the lower layer, to directly transfer data to the corresponding processor, and to perform the transfer process simply and quickly. .

[Means for solving problems]

FIG. 1 shows a basic configuration diagram of the present invention.

In FIG. 1, a processor 2 is a processor forming a hierarchical structure and performs various types of processing.

A bypass switch 3 is provided in each processor 2,
This bypasses the upper layer communication path 4 and the lower layer communication path 4.

The communication path 4 is a communication path through which the processors (2) exchange data with each other.

[Effect]

As shown in FIG. 1, the present invention provides a bypass switch 3 in the processor 2 of each layer to bypass the communication path 4 of the upper layer and the communication path of the lower layer, so that one processor 2 can communicate with the processor 2 of another layer. By controlling the bypass switch 3 of the processor 2 to ON, data is directly transferred to the corresponding processor 2. For this transfer, all lower processors (2)
There are modes in which data is directly broadcast (transferred) to all processors (2) in a certain lower layer, or data is transferred directly to a specified processor (2) in a specified layer.

Therefore, by providing a bypass switch 3 in each processor 2, one processor 2 can directly transfer data to the corresponding processor 2 in a different layer, making it possible to perform data transfer processing easily and quickly. Become.

〔Example〕

Next, the configuration and operation of one embodiment of the present invention will be explained in detail using FIGS. 2 and 3.

In FIG. 2, each processor 2 has a bypass switch 3 and is interconnected by a data bus 5 and a control bus 6 to form the illustrated hierarchical structure.

The bypass switch 3 connects the upper layer data bus 5 and the lower layer data bus 5.

This bypass switch 3 is directly connected to 0 by the own processor 2.
N10FFW+111311 or other upper N/lower layer processors connect 0N1 via control bus 6.
It is configured to be able to perform 0FF control.

Using the flowchart in Figure 3, host 1 in Figure 2
The operating procedure for simultaneously broadcasting (transferring) data to all processors 2 in a layer will be explained.

In FIG. 3, the host 1 specifies the 111i-th address and controls the bypass switch 3 to turn on.

This is done by the host 1 sending the address assigned to the bypass switch 3 of the corresponding first-layer processor 2 to the control bus 6, turning on the bypass switch 3 of the corresponding 1N processor 2, and turning on the data bus 5. It means to bypass it.

In the figure, the host 1 specifies the second layer address and instructs the bypass switch 3 to oNt4i1. This is host 1
sends the address assigned to the bypass switch 3 of the corresponding second-layer processor 2 to the control bus 6, and turns the bypass switch 3 of the corresponding second-layer processor 2 to O.
This means that the data bus 5 is set to N and the data bus 5 is bypassed.

In the figure, ■ indicates that the host 1 broadcasts (transfers) data to all processors in the third layer. Since the processor 2 is directly connected to the processor 2 by the data bus 5, this means that data is directly transferred to the third layer processor 2 via the data bus 5.

As described above, the host 1 (or the upper layer processor 2) turns on the bypass switch 3 of the lower layer processor 2, and the host 1 directly communicates with the processor 2 of the desired layer via the data bus 5. It is possible to directly transfer data via this data bus 5. Note that the flowchart in FIG. 3 shows that the host l directly transfers data to all processors 2 in the third layer, but
It is also possible to designate an address and transfer data only to a specific processor 2. Furthermore, data may be broadcast not only to all processors 2 in the third layer, but also to all processors 2 in layers from the host 1 to the third layer. This is convenient when downloading to multiple processors at once.

In addition, when starting up a hierarchical multiprocessor system, the bypass switch 3 is turned on in advance by hardware for processors that attempt to load the same initial program.
The data bus 5 is directly connected to the corresponding processors, and the host 1 directly loads the processors 2 connected to the data bus 5.

After the loading is completed, each processor may turn off the bypass switch 3 by an M control signal from itself or the host 1 (or the upper layer processor 2) to return to the hierarchical structure.

(Effects of the Invention) As explained above, according to the present invention, each processor 2
A bypass switch 3 is provided inside the processor, and this is controlled by 0N10FF@ based on instructions from an upper layer processor, etc., and the communication 94 is directly connected to the corresponding processor to transfer data. , data can be transferred quickly and easily between processors in different hierarchies.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a flowchart explaining the operation of the present invention.
FIG. 4 shows an explanatory diagram of the prior art. In the figure, 1 is a host, 2 is a processor forming a hierarchical structure, 3 is a bypass switch, 4 is a communication path, 5 is a data bus, and 6 is a control bus t-it. Operation explanation flow of the present invention → Yard Figure 3

Claims (1)

[Claims] In a data transfer method for transferring data to processors constituting a hierarchical multiprocessor, a plurality of processors (2) are connected in a hierarchical structure by a communication path (4), and a A bypass switch (3) is provided to bypass the communication path (4) between the upper layer and the lower layer, and a certain processor (2) controls ON/OFF of the bypass switch (3) of the lower processor (2). The configuration is such that data can be transferred all at once to all lower processors (2), all processors (2) in a predetermined hierarchy, or directly to a specified processor (2) in a specified hierarchy. A data transfer method for hierarchical multiprocessors that is characterized by: