JPH01225996A - Display device - Google Patents

Abstract

PURPOSE:To prevent the entire circuit being affected by defective part by controlling the direction of transmission signal voltage by means of switch circuits provided between unit circuits, and transmitting the signal voltage to the unit circuits if a poor operation part or defective part is detected, thereby going around the part. CONSTITUTION:If defect arises, a circuit C32 cannot obtain a normal output from a circuit S32; therefore, the detecting circuit 9 decides the circuit C32 is defective. When this detecting operation is completed, the information, decided by the detecting circuit 9, is input to an inspection circuit 11, and this circuit 11 decides where the defect arose in the circuit. In the actual operation of the circuit, a switch control circuit 10 controls the switch circuits 3 and 5 on the basis of the information on the defect so that the circuits is operated to go around the part where the defect aroused. Thus, in a large-scale circuit having a large number of circuits, defective part is salvaged and the entire circuit is normally operated by means of a small number of additional circuits.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to large-scale semiconductor circuits and devices, and particularly to large-scale semiconductor circuits and devices such as wafer scale integration devices (WSI devices) and active matrix liquid crystal displays using thin film transistors (TPT). This invention relates to circuits and devices suitable for scale elements.

[Conventional technology]

In recent years, with the increase in the scale of semiconductor devices, there has been an increase in technology for configuring circuits on large-area chips on semiconductor wafers, and so-called active matrix technology in which TPT is formed on large-area glass substrates and displayed in combination with liquid crystals. Displays are being actively researched. One of the biggest problems with increasing scale is a decrease in yield due to increasing scale. In particular, if the built-in drive circuit of a WSI or active matrix display malfunctions due to a disconnection, short circuit, or damage to a transistor, the functionality of the entire device may be impaired, or damage may occur during the manufacturing process. If a defect occurs, the element is considered defective and cannot be used as a product.

As a way to remedy this problem, there are methods to provide multiple necessary parts of the circuit and transfer the signal to the circuit that operates normally so that there is no problem with the overall operation, and also to create multiple parts for a single transistor. A method has been devised to restore normal operation by connecting devices in parallel or series to compensate for failed elements.

For example, as a method for realizing these methods,
64394, JP-A-60-82870.

JP-A-60-164791, JP-A-62-106
Examples include Publication No. 96.

[Problem to be solved by the invention] These conventional techniques have a simple configuration in which the circuit configuration is multiplexed to repair defective parts, but when the scale of the circuit increases, the scale of the spare circuit also increases. As the size increases, there is a problem that the overall circuit scale becomes too large. Further, when identifying the location where a circuit defect occurs and taking necessary countermeasures, it is not possible to automatically execute the countermeasures, which makes the process complicated.

An object of the present invention is to propose a circuit configuration in which even if a defective part occurs, the defective part is automatically avoided by using a small number of spare circuits, and the defective part does not affect the operation of the entire circuit.

[Means to solve the problem]

The above purpose is to divide the circuit into multiple small circuits (hereinafter referred to as circuit units), and to
Circuits with the same configuration as the unit circuits, which are significantly fewer in number than the unit circuits, are arranged, and the switch circuits installed between the unit circuits control the direction of signal voltage transmission, and if there is a malfunctioning or defective part, the signal voltage is transferred to the unit. This is accomplished by a method that avoids defective parts.

[Effect]

To detect defective parts, the output status of each unit circuit is automatically inspected when the entire circuit is operated, and based on that information, the switch circuit is automatically controlled to avoid the position of the defective part. Therefore, detection of a defective part and avoidance of a defective part can be performed automatically, and the circuit can be used without worrying about the presence or absence of a defective part.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. A large number of unit circuits 2 are C5tt Cxzt...

They are arranged in an array like C84, and are connected by bus line 1. A switch circuit 3 is connected between each unit circuit to control the direction of signal voltage transmission. When all the unit circuits are operating normally, the signal voltage is from Bll to Cztt on the bus line.
Czzt ・=* Cal and output to BOl, B
tzt Bta-t Bta are also B 0
2. Bos...Output to Boδ. Alternatively, the transmission direction of the signal voltage does not need to be transmitted through one bus line in an orderly manner as described above, but the transmission direction may be transmitted to another bus line by each switch, or the operation of the unit circuit may be bidirectional. For example, an operation in which a signal voltage is transmitted from the BO side to the 81 side is also possible. Control of these transmission directions can be realized by sending switch control signals generated from the switch control circuit 10 to each switch via the switch control line 4 and controlling the switches.

For example, consider a case where a defect occurs in a circuit.

If the circuit Caz in the figure does not operate normally, Bsz
The signal voltage input from C1zt S1z.

It is transmitted to C22 and Szz, stops at Csz, and is no longer output to saz. Here, input a pulse train whose output can be tested experimentally as the input voltage of Bsz, and set S1z to 5.
ttt The switch is set so that it can also be output in the S & 1 direction, and the signal is input to the detection circuit 9 via the detour line 6 and becomes C1.
Check whether z works normally. The voltage output from C12 is also applied to the circuit Czz, and the output of Czz is applied to the switch circuits Szz and Szx.

Saw is set to pass through the detour line 6, inputted to the detection circuit 9, and inspected to see if Czz operates normally. The circuit is inspected by repeating these operations one after another. It depends on the configuration of the circuit whether the switching timing of the switch is performed in a time-division manner according to the transmission of the signal voltage, or whether it is detected by connecting the bus lines in parallel and keeping the switch in the always-on state. If a defect occurs in Cat, a normal output cannot be obtained from Ssz, so the detection circuit can determine that C32 is defective. When this test operation is completed, the judgment information obtained from the detection circuit 9 is input to the test circuit 11, and is compared with information in a memory circuit into which normal judgment information has been input in advance. The method determines in which part of the circuit the defect has occurred. Various hardware or software methods can be considered for this determination method.

Based on this defect information, during actual operation of the circuit, the switch circuits 3 and 5 are controlled by the switch control circuit 10, and the circuit is operated so as to bypass the defect occurrence area. For a defect in the circuit CSX, if the signal voltage of the switch Szz is Szz→Sat→Saa→Sa4→C5ub→
By transmitting along the path Sb4→Sbs→Saa→S31→5az−+Caz, the defect in C32 can be avoided. The spare circuit unit is made with the same configuration as the circuits C11 to C34, and even if a defect occurs in any of these circuits, it can be repaired using the same method.

FIG. 2 shows a specific example of the configuration of the switch circuit 5. This is a method in which two switch elements 12 are connected to a bus line 1 and controlled by a switch control line 4. In normal use, close switch b and
performs the operation of transmitting a signal voltage to the circuit. In addition, when the circuit is inspected and the next stage circuit does not operate normally, switch a is closed and the output signal voltage of the previous stage circuit is transmitted to the detour line 13. At this time, switch b is set to indicate the state of the next stage circuit. Close or open depending on The voltage applied to the switch control line 4 is output from the switch control circuit.

To specifically realize the switch 12, a three-terminal device such as a MOSFET element, a transistor element, a TPT element, or an analog switch circuit is used.

FIG. 3 is an example showing the configuration of a switch circuit when there are a plurality of bus lines 1. In FIG.
Each of them has a structure in which they are opened and closed by a common switch control line, but a configuration in which each switch can be controlled individually is also conceivable, if necessary.

FIG. 4 is a modification of FIG. 2. switch control line 4
This is a system in which the output of the inverter circuit 14 and the two switches 12a and 12b are controlled together with the voltage. In addition to the inverter circuit, various logic circuits can be connected to the switch control line to efficiently control a large number of switches.

FIG. 5 is a modification of FIG. 4. switch control line 4
By holding the output in the memory circuit 15, it is possible to maintain the state once input, and it becomes easy to generate the control voltage to be applied to the switch control line.
This can be achieved at lower frequencies. A flip-flop circuit or the like can be considered as the memory circuit.

FIG. 6 shows a configuration in which a memory circuit 15 is attached to each of a plurality of switches 12 for control. With this configuration, the state of the switch is determined by transmitting the switch control signal by -degrees through the switch control line 4, so the number of switch control lines 4 can be significantly reduced. All that is left to do is to change the direction of signal transmission as needed by applying a switch control signal only to the part where the state of the switch is to be changed.

FIGS. 7 and 8 show examples of switch circuits in which switches 12 are arranged in a matrix. In FIG. 8, a memory circuit 15 is used to control the switch.

With this matrix configuration, the connection between the bus line 1 and the detour line 13 can be freely set by selecting the switch 12, so the detour line can be used effectively.

FIG. 9 shows the configuration of a defect detection circuit. The detection circuit is
Input buffer circuit 16 for inputting signals input from each circuit unit through detour line 6.7. Memory circuit 17 for storing detection signal information. A memory circuit 18 in which normal detection signal information is input in advance.
, a comparison circuit 19 for comparing the contents of two memories.
．． It consists of an output buffer for outputting the output information of the comparison circuit.

The input buffer circuit has functions such as amplifying, waveform shaping or decoding the signal voltage from the detour line 6.7, and temporal storage, and transfers the operating state of the circuit to the memory circuit 17. The memory circuit 17 has a function of storing information sent from the input buffer circuit, such as the state of occurrence of a defect and its location. The comparison circuit 19 reads and compares the information of the two memory circuits, and detects differences in the current circuit state from the output of the memory circuit 18, which has input information assuming normal operation. It has the function of extracting and outputting. The output buffer 20 shapes the waveform of the output voltage and forms output information.

The memory circuit 18 may be ROM (read only memory) or RAM (random access memory).
The operating state of the circuit is stored, and information to be stored in accordance with the target circuit is input.

By having this memory circuit, even if the circuit configuration changes, the contents of the memory circuit can be matched to the configuration of the target circuit, so there is no need to make a major change in the circuit configuration of the detection circuit 9.

Alternatively, it is also possible to input a plurality of circuit patterns into the memory circuit 2 and extract information about the target circuit by changing the way the memory is read.

FIG. 10 is a modification of the configuration shown in FIG. 1. The method for detecting a defective part is the same as in the case of FIG. 1, except that when bypassing the defective part, the switch circuit is detoured to a circuit unit that is not operating. In order to achieve this, at least one of the target circuit units must be inactive, but it is necessary for the circuit units to sequentially transmit signal voltages, as in the case of a shift register. In the case of a function in which the signal voltage is transmitted, the circuit unit is in a state of halting operation after the signal voltage is transmitted, and the signal voltage can be detoured using such a circuit unit.

The method shown in Figure 10 cannot be applied to all circuits, but as shown above, if the target circuit is not operating (it is operating normally but is not receiving any signals, etc.) This is an effective method because it simplifies the circuit configuration because there is no need to form a spare circuit if a circuit unit (referring to 1) is present.

Next, a flowchart of defect inspection up to normal circuit operation in a circuit configured according to the present invention will be explained with reference to FIG.

First, when the power is turned on and circuit operation begins, a test pulse voltage is generated within the circuit. This can be achieved by reading inspection information that has been previously input into a memory or the like and generating a voltage. A switch control pulse is generated in accordance with the transmission of this test voltage pulse, and the switch circuit is set so that the output of each circuit unit is input to the detection circuit via a detour line. Through this operation, information on each unit circuit is sequentially input to the detection circuit, and the position of the defective part is stored in the memory circuit. By comparing this information with previously input information, the configuration of the switch to be corrected is determined by the inspection circuit or a higher-level CPU. Here, if more defects occur than the number of defects that can be corrected, the circuit is discarded as a defective product. This determination is made at the inspection stage immediately after the circuit is manufactured, and the circuit configuration of the present invention can also realize the function of inspecting large-scale circuits. If correction is possible, a switch control pulse is generated to bypass the defective part, and the switch circuit is set so that the defective part does not become a problem in normal use. After this setting is completed, normal use begins.

This test describes the method to be performed when the power is turned on, but if an abnormality occurs in the circuit operation while the circuit is in use, it is also possible to temporarily stop using the circuit and perform a similar test. can.

All of the above-described inspection methods and methods for avoiding defective parts can be executed by controlling electrical switches, so that inspection and correction can be realized at high speed.

FIG. 12 shows an example of a circuit configuration to which the flow of defect detection and switch setting described in FIG. 11 is applied. Circuit block B11゜Bzz,...Baa
are circuits having defect detection and repair functions as described in FIGS. 1 and 10, and are connected to each other by a signal bus line 25.

In addition, from each circuit block, a bus line 2 is used to transmit a determination signal to notify that the detection of internal defects and the setting of switches for bypassing the defective parts have been completed.
4 is output, and this is input to the judgment circuit 23.The 0 judgment circuit receives judgment signals from all the circuit blocks, and after judging that the entire circuit is ready, sends the start signal to the input/output circuit (I10 An input signal to be sent to the circuit) 27 and processed is input, and normal circuit operation is started.

If one circuit block outputs a determination signal that cannot be set, either set the signal voltage transmission direction so that the signal voltage is not input to that block, or if a defect occurs in that block. Either set the transmission direction of the signal voltage within the block so that no signal is input to the unit circuit that is inoperable, or output an inoperable signal voltage from the judgment circuit assuming that the entire circuit is inoperable. Make sure to do the following.

As shown in Figure 12, by inspecting the inside of a large-scale circuit and repairing defects in small blocks,
The advantage is that these functions can be executed in a short time and efficiently.

Further, since the defect detection and inspection circuits formed in each circuit block can be configured relatively easily and on a small scale, there is an advantage that the circuit configuration as a whole can be simplified.

FIG. 13 shows an example in which the embodiments described above are applied to a specific circuit. This configuration shows a shift register circuit that generates a scanning voltage for an active matrix display, generates a scanning voltage for a line sensor, and sequentially transfers signal voltages in a WSI or LSI. Figure 1 shows a multi-stage shift register circuit.
Multi-stage shift register circuits S Rx-1, S Rt, S R +1, etc. corresponding to the unit circuits described in
and an amplifier circuit Al-1, At for amplifying its output.
y Al+1... The signal bus line 1 inputs a signal voltage FST for starting scanning or inputs a signal pulse train. As a spare circuit, 5Rsub having the same configuration as each shift register circuit is provided. The operation of this circuit will be explained based on the flow diagram shown in FIG. First, a pulse voltage for testing is applied to the signal bus line 1 by the control circuit 28.

The control circuit also generates a transfer lock for each shift register circuit, and sequentially turns on and off the switch circuits 5 in accordance with the timing at which test pulses are output from 5RI-1, 5Rtt, . . . . As a result of this operation, each output of the shift register circuits S Rs -11S Rit . . . is input to the detection circuit 9 via the detour line 6 or the detour line 7 . Here, it is assumed that a defect exists in this circuit, for example, a defect exists in SRi. At this time, even if the test pulse voltage is input and the test pulse voltage is output from 5Ri-t, no output is obtained from SRi because the next stage SR1 is a defective circuit. In this case, it is determined in the detection circuit that SR1 is a defective circuit, and the set voltage of the switch circuit is transmitted from the switch control circuit 10 to each switch through the switch control line 4.

If a defect occurs in SR1, 5RI-1 output → S
1 → Detour line 6 → Reserve shift register 5 Rsub input → Reserve shift register 5 Rsab output → Detour line 7 →
sl and Ss are controlled so that signal voltages are transmitted in the order of input S2→SRt+. Since the spare shift register has the same configuration as each shift register, it can operate exactly the same as the SRs, and it is considered that 5Rsub has replaced the position of SRi.

At this time, the control circuit 28 again generates a test pulse voltage, and tests of the circuits below SRt+z are performed in the same order. After this series of defect detection and defect bypass switch settings are completed, the control circuit 28 outputs a voltage for actually displaying information on the display section. At this time, since SRi does not operate normally, the output voltage of each stage of SRs cannot be obtained, so here, the output of each stage of the spare shift register circuit 5Rsub is connected to switches Ss and
By switching 4°Ss, the voltage is applied to the display section from the amplifier circuit A1, so that a completely normal display can be realized.

Here, as the switch circuit used in this embodiment, any suitable one among the switch configurations shown in the examples shown in FIGS. 2 to 8 may be used.

The configuration shown in Figure 13 is a redundant design method for conventional shift register circuits, because it can significantly reduce the number of spare circuits compared to a configuration in which two or more columns of shift register circuits with the same configuration are formed in parallel. This has the advantage that the circuit can be easily configured.

Further, although FIG. 13 shows a configuration using one backup shift register, a configuration in which two or more backup shift registers are formed is also easily conceivable within the scope of this embodiment. In this case, there are a plurality of shift register circuits that can be bypassed in the target circuit, and it is possible to further improve the reliability of the circuit. In addition, the number of stages of each shift register circuit and the number of shift register circuits in the target circuit can be arbitrarily changed and set depending on the frequency of defect occurrence, improving the reliability of each circuit and reducing defects during the manufacturing process. If the probability of occurrence is significantly reduced, the number of spare circuits can be significantly reduced relative to the number of target circuits, which increases the effectiveness of this embodiment.

FIG. 14 shows an example in which the present invention is applied to a signal side drive circuit of an active matrix display.

Various known configurations have been proposed for the configuration of the signal side drive circuit, but in the example shown in FIG. 14, the signal input bus line 1 is connected to SG1. SG2. ..., and by switching the signal drive circuit selection voltage that is sequentially applied to the signal drive circuit selection line within each signal side drive circuit block, the signal voltage of the signal input bus line is sequentially changed. The input method is shown, and the configuration of each signal drive circuit includes switch elements installed in parallel to input voltage from the signal input bus line, line memory to hold the input signal voltage, and voltage control circuit. It consists of an output buffer circuit for applying voltage to the display section. The major difference in function between FIG. 14 and FIG. 13 is that in FIG. 13, the signal voltage is transferred sequentially through the shift register circuit, whereas in FIG. However, the signal voltage is applied all at once, and there is no function to transfer the signal voltage.

Here, for example, a case where a defect occurs in the signal drive circuit SO2 will be described. At this time, the voltage of the signal bus line is applied to all circuits of the 5GIP 5Gzt SGa, but some or all of the outputs of the SGz are no longer output. The detection circuit 9 detects this, and the switch control circuit 10 switches Sz, Szx to Szs, and switches 82 so that the signal drive circuit selection voltage is applied to the spare signal circuit 5Gsub instead of SGz, and SGx+ab Szt to Szs are switched so that the output of is applied to the display section 30. This action causes SG
The defect occurring in section a no longer affects the display section, and normal display can be realized.

In addition to the configuration shown in Fig. 14, SGi, SGzp
A method of providing a spare circuit for each circuit, that is, for each output card or multiple output cards, to compensate for the defective part for each output card or multiple output circuits, or for each block of the signal circuit. A method for compensating for defective areas can be realized.

FIG. 15 is a modification of the embodiment shown in FIG. In the shift register circuits SR1 and SRz, the former is the main circuit, and the latter is a spare circuit.The output is transmitted to the switching detection circuit by the switch circuit 3 to inspect the characteristics of the shift register circuit, and also to detect defects during SRI. If exists, S
Switch 3 is changed to apply more voltage than Rz. The switch array circuits SAz, SAz, . . . SA4 have a function of switching the output of the shift register circuit so that a scanning voltage is applied to the display section. The control circuit 28 has the function of generating voltage for switching switches and generating a scan start voltage.

By providing the switch array circuits SA1 to SA4 at the output section of the shift register circuit as in this circuit configuration,
This has the effect of significantly reducing the number of circuits to be inspected.

FIG. 16 shows an example in which the present invention is applied to the active matrix display described above.

Circuit unit Czxt C1! , ・=Ctz, Cz
zt-CzstCzs, . . . tcss is a circuit that executes processing such as logical operations. These are connected by a signal bus line, and a switch circuit 3 and a detour wiring 6 are arranged and connected in the middle of the bus line. The switch circuit 3 is controlled by a switch control circuit 10 and a switch control line 4 for transmitting its signal voltage. Signal voltages between circuit units are transmitted bidirectionally or unidirectionally to the signal bus line. In addition, the spare circuits C5ubty and C5ubz are connected to circuit units C11 to C.
The circuit configuration has the same functions as the SS and also has a circuit inspection function.

To operate the circuit, first, before normal operation, a test signal is generated to test the function of each unit circuit, and the results are input to C5ub1t Cs*bz to locate the defect in the two circuits. After checking, the switch control circuit 10 sends a signal voltage to each switch so as to set the switch circuit 3 to bypass the defective circuit. For example, if a defect occurs in Czz, the signal voltage to Cat will be routed to C5u through the switch circuit 3 and detour wiring 6.
as input to bi, and the voltage from Czs is C5
Set to be input to ubz* C5ubxt
Each C5ubz is configured to have the same functions as the Cxx, and when viewed from the C2l side or the Cxx side, operations can be realized as if data were being exchanged with the Cxx.

C5ubx and c Sub! Wiring 36 is used to exchange data with
Run using

FIG. 17 shows an example of the circuit configuration of Cs ring bx and C3ubz. Switching circuit 3 that switches input of detour wiring 6
7 and a plurality of circuits receiving the outputs of the circuit 37, here, for example, a detection circuit 41 .corresponding to the circuit configuration shown in FIG. The circuit 38 having the functions of C1x to CBI and C18 to CSa is connected to the circuit 39 having the functions of CXZ to Csz, and if necessary, data can be input to another preliminary circuit via the output buffer circuit 40. Wiring 36 for output
may be provided.

With such a configuration, the spare circuit can support many functions.

The configuration shown in FIG. 18 is a modification of the configuration shown in FIG. 16. That is, the circuit units 2 are arranged in a matrix, a switch circuit is provided between the signal bus lines connecting each circuit unit, the output is detoured to the detour wiring 6, and the inspection circuit 9 and the preliminary circuit unit 8 perform defect inspection and defect detection. This is a configuration that realizes a bypass of the section. The matrix configuration not only reduces the number of detour wires and switch circuits, but also shortens the length of wires when signals are detoured, making it possible to achieve higher speeds.

FIGS. 20(a) and 20(b) show an embodiment in which the present invention is applied to a liquid crystal display in which a drive circuit and a display portion are formed on the same substrate. Po1y-S using materials such as glass
Circuit units 2. Switch circuit 3. A scanning side drive circuit and a signal side drive circuit 45 composed of an auxiliary circuit 31 and the like. Controller 11. A detection circuit and the like are formed around the display section 30. The scanning side drive circuit has a function of generating vertical scanning voltages for a large number of display pixels 47 in the display section 30, and is shown in FIG. 20(b).
In the known configuration using TFTlooO for the display pixel 47 shown in , a voltage is generated to scan the gate electrode of the TPT element in the display section. On the other hand, the signal side drive circuit 45 has a function of generating a signal voltage corresponding to display information to the signal wiring of the display section. In the embodiment shown in FIG. 20, the scanning side drive circuit is provided with defect detection and repair functions, and its detailed configuration and operation will be described below.

FIG. 21 shows an example of the configuration inside the circuit unit. The circuit unit 2 has a terminal DIN to which a data voltage such as a vertical scanning start pulse is input, and an output terminal V0uT1p which generates an output voltage to the scanning wiring of the display section.
V Out! tV 0uT3... and a terminal Dour that generates a voltage to drive the next stage circuit unit, and an example of its internal configuration is as shown in the figure (b), a shift register 52... It consists of a buffer or level shifter 53. The shift register 52 sequentially transfers the voltage input from DIN and outputs the voltage one stage at a time. The output of each stage is amplified by the buffer circuit 53, and the voltage for driving the display section is VoutztVourzeV.
Output from O1IT8 terminal.

FIG. 21 shows an example in which the circuit unit is formed by three stages of shift registers and two stages of buffers per output of one stage of shift registers, but the number of stages of shift registers,
The number of buffer stages can be freely designed depending on the circuit specifications. For example, in order to reduce the number of circuit units, the number of stages in a shift register can be designed to have a large number of stages, and the number of stages in a buffer depends on the load capacitance of the display section being driven. It can be designed accordingly.

FIG. 22 shows an example in which a switch circuit and an auxiliary circuit 31 are added to the circuit unit shown in the configuration of FIG. 21 to configure a defect relief circuit. In the configuration shown in Figure 22,
The region surrounded by the broken line is the region operated by one circuit unit 2, and by forming a large number of these, a scanning side drive circuit can be formed.

Switch SW shown in FIG. 22 1. S W z
, . . . The states of SWs indicate that the circuit unit 2 operates normally. Here, if a defect or the like occurs inside the circuit unit 2, the Vourit Voutzt Vour
a.

Assume that a normal voltage different from the reference signal is not output to DouT. At this time, SW 1 .

Close SWx and pass the auxiliary line 6 to the DI of the auxiliary circuit 31.
Bypass the voltage to N and connect the auxiliary circuit 31. Voltage can be applied from uT to the next circuit unit via SW2 via auxiliary line 7. In addition, the Vo of circuit unit 2
The voltage of utxt Voutzt Vouva is SWa,
By switching between SWa and SWa, the auxiliary circuit 31
The voltages Voutxt VOut2y Vouts can be output to the scan electrodes of the display section through the auxiliary line 54. That is, by operating the five switches around the circuit unit 2 in which the abnormality has occurred, the function of the scanning circuit as a whole can be maintained normally.

In other words, the scanning electrode includes an electronic switch SWa.

Depending on SWa and SWs, either the output of the circuit unit 2 or the auxiliary circuit 31 is selectively applied. Here, the switch elements SW1 to SW5 may be electrically controllable switch elements, mechanically controllable switch elements, or thermally controllable elements such as a heater.

FIG. 23 shows a modification in which the connection position of the detection circuit 9 in FIG. 20 is connected to the auxiliary line 51.

With this configuration, for example, even if the shift register in the circuit unit is operating normally, but a normal voltage is not applied to the display section 30 in a defect mode such as when an abnormality occurs in the buffer section, The auxiliary circuit 31 makes it possible to apply a voltage to the abnormal part using the auxiliary line 51.

In this circuit configuration, when an initial abnormality is inspected, the switch control circuit 10 is configured so that the voltage of each circuit unit is applied to the auxiliary line 51.
Set it accordingly. Then, a test voltage pulse is generated from the controller 11, the output of each circuit unit is passed through a switch circuit, and the operation of each unit circuit of the detection circuit is inspected via an auxiliary line.

FIG. 24 shows a time chart of voltages at various parts during an initial test in the circuit configuration of FIG. 23. Vs
t is the voltage output from the controller and first input to DIN of the circuit unit.

Circuit unit 12 Circuit unit 2. From ..., VS
The voltage VoutztVouriVOI where T is sequentially transferred by the shift register and amplified by the buffer circuit
IT3 is output. When this voltage is input to the detection circuit 9 through the auxiliary line 51, V dingsz, V
Like dingsz*Vt5s, respectively, V 0IIT1
This becomes a pulse train in which pVowtz and Volts are connected. The detection circuit 9 inputs the voltage waveform of this pulse train, checks the voltage value, pulse width, etc., and inspects the operating state of each circuit unit.

FIG. 25 shows a circuit configuration in which the configuration of the circuit unit is realized by TPT elements. The shift register 52 and the buffer 53 can use a known circuit configuration. In the case of Fig. 25, six TPs are used as shift registers.
Using a two-phase clock dynamic type using a T element,
The buffer is composed of two inverters.

All of the TPT elements are shown to have a configuration using an enhancement type, but the circuit configuration may be 0MO3 or E/D type, and the shift register and buffer may be configured other than the above, and the same effect of the present invention can be obtained. It will be done.

The switch circuit is configured to use one TPT element each to apply voltage to the auxiliary lines 6 and 7 and route it to the auxiliary circuit. As described above, this switch circuit can have many configurations, but as described in FIG. 22, any configuration may be used as long as it is possible to switch the voltage.

FIG. 26 is a modification of FIG. 22 in which the connection method of the switch for bypassing the auxiliary lines 6 and 7 is changed. When there is an abnormality in the circuit unit 2, switching SWl to the auxiliary line side and closing SWz to bypass the voltage from the auxiliary line 7 to the next stage circuit unit allows the same operation as shown in FIG. 22 to be realized.

Figure 27 shows the first circuit that bypasses the malfunctioning part by using other unit circuits that are not operating, without using the auxiliary circuit unit.
This is a specific application example of the configuration described in FIG. FIG. 28 shows the driving waveforms of this circuit.

The control voltage of SW1~5Wto is high level t.
It is assumed that these switches change to the state shown by the broken line in FIG. 27 during the on-on period. Here, circuit unit C1
It is assumed that a malfunction has occurred.

Before the input voltage DIN is input to the circuit unit CI (or in synchronization with DIN), the switch control voltage is set to high level, and SW1 to Svt.

Leave it in the state shown by the broken line. As a result, DIN is not input to CI but is input to CJ via auxiliary line 6, and is input from SWe to CJ. The output of CJ is sent from SW7 via auxiliary line 7 and SWz to the circuit unit at the next stage of ci. is input. On the other hand, at this time, the output voltages to the pixel portions of CI and CJ are S W a t SWl tSWs and SWs, 5
Since Wst 5W10 is in the state shown by the broken line, the outputs of Ca are SWl, SWl, 5WIO, and the auxiliary line 54 and SW s , respectively.

Voutt+ through SW a, SW 11
Voutz and Vouta are output. and Cs
After bypassing, the switch control voltage becomes low level, so 8w1~SW! o returns to the state shown by the solid line, and the voltage transferred to cJ is VOII from C4.
T1'*V o u t z ' t V o 11
It is output to T a '.

In this way, by using C4 twice during one operation, it is possible to avoid the malfunction that occurs in C1. According to this method, no auxiliary circuit is required;
The circuit configuration becomes simple, and even if there are two or more malfunctioning parts in the circuit, by repeating the detour operation, the circuit as a whole can operate normally.

FIG. 29 shows a circuit configuration in which the configuration shown in FIG. 14 is formed using TPT elements. This circuit shows an example of a signal-side drive circuit, and the circuit configuration in each circuit unit is, as is well known, including sampling TPT elements 56 . Line memory capacity 57. Inverter 58. It has a configuration in which a multiplexer 59 is connected, and data is input by sequentially switching unit selection terminals 60 on a data bus line 55 common to a plurality of circuit units. This operation differs from the configuration using the shift register described above in that the voltage is transferred within the circuit unit. However, even in this operation, abnormalities in operation can be compensated for by providing an auxiliary circuit 31 and a switch circuit having the same configuration as each circuit unit.

In this case, since the data bus line is commonly connected between the circuit unit 2 and the auxiliary circuit 31, the detour line 6.7 is not necessary, and instead of the malfunctioning circuit unit, the auxiliary circuit By applying a selection voltage to the unit selection terminal of the unit, it is possible to compensate for the operation of the malfunctioning part.

FIG. 30 shows an example in which this embodiment is applied to a data processing device such as a personal computer.

It is also possible to form part of the circuit that has been described as being formed on a TPT substrate, for example, inside the control circuit 50 of a personal computer. Here, an example is shown in which the defect information memory 48 is made of ROM and formed in the control circuit 50. The defect information memory can be created separately according to the scale and configuration of the display section, so it can be used with a wide variety of displays.

In addition, it is also possible to provide a defect information display 51 separately outside the display to facilitate maintenance, and to effectively utilize the display's defect detection function to improve the reliability of the device. can.

Furthermore, even if the various circuits described above cannot be integrated within the substrate due to operational speed or manufacturing process considerations, it is of course possible to form them externally.

Note that 49 is an arithmetic processing unit (CPU) that executes instructions for detecting malfunctions, executes instructions for remediating malfunctions, and supplies control signals to the switch controller 11. .

FIG. 31 shows that two or more display panels 52 to which the present invention is applied are provided in a device or system, and when a defect occurs and display is impossible, the control circuit 51 switches the display to a spare display panel. It is the composition.

This is an effective configuration especially when high reliability is required because the display can be automatically switched without the need for user judgment.

FIG. 19 is an embodiment showing a configuration in which the present invention is applied to a liquid crystal display. Scanning circuit 56, signal circuit 5
In order to improve the reliability of the circuits such as 7, etc., these circuits are placed inside the liquid crystal seal 53, and a seal is also provided between the circuit section and the display section to prevent deterioration due to the flow of the liquid crystal. By immersing the circuit in pure organic matter,
This has the effect of preventing circuit deterioration caused by impurities.

FIGS. 32(a) and 32(b) show another embodiment of the present invention.

The difference from the embodiment shown in FIG. 20 is that the scanning side circuit unit 2
The reason is that a resistor 200 connecting between the outputs of the switch is provided instead of the switch group. Due to this group of resistors, the data of the surrounding electrodes is always applied to the electrodes, so even if any of the outputs of the circuit unit 2 malfunctions, it is difficult for the human eye to discern the problem. No display is obtained.

〔Effect of the invention〕

According to the present invention, in a large-scale circuit with a large number of circuits,
It is possible to repair the defective part and restore the normal functioning of the entire circuit with a small number of additional circuits, and it is possible to improve the reliability and yield of large-scale circuits and display devices.

Furthermore, since the circuit has the function of detecting and determining defects, it has the advantage that it can be easily inspected not only immediately after the circuit is manufactured, but also while it is in use.

[Brief explanation of the drawing]

1, 10, 12, 13, 14, 15, 16, 18 to 32 are circuit block diagrams showing embodiments of the present invention, and FIG. 8 is a configuration diagram of the switch circuit, FIGS. 9 and 17 are internal configuration diagrams of the detection circuit, and FIG. 11 is a flowchart showing the inspection process. 1... Bus line, 2... Circuit unit, 3, 5...
...Switch circuit, 4...Switch control line, 6,
7... Detour line, 8... Reserve circuit unit, 9...
...Detection circuit, 10...Switch control circuit, 11...
- Inspection circuit, 12... Switch element, 13... - Detour line, 14... First port 22 - Figure 3 Figure 4 Figure 5 Figure 7 Figure 3 Figure 517/ BInBes Bo4 Figure 12 Figure 13? g 150 Fig. 76 Fig. 1'/Ko 5S No. 20 (0L) No. 21 (0L) νOur 22nd country'iA Fig. 23 Fig. 240 5T Vju 3 Fig. 25 Fig. 28 Vouγ3 Vou13' 83Z Fig. 1OθO

Claims (1)

[Scope of Claims] 1. A display panel in which a display body is arranged at the intersection of a plurality of scan electrodes and a plurality of signal electrodes, a scan-side drive circuit that generates a signal to be applied to the plurality of scan electrodes, and the above-mentioned In a display device having a signal-side drive circuit that generates signals to be applied to a plurality of signal electrodes, at least one of the scanning-side drive circuit and the signal-side drive circuit applies signals to at least one electrode in response to an input signal. It has a plurality of circuit units that generate signals to be applied, and at least one auxiliary unit that has substantially the same operational function as the circuit unit, and at least one of the circuit units malfunctions. In this case, the input signal to the malfunctioning circuit unit is applied to the auxiliary unit, and the auxiliary unit applies a signal to at least one electrode corresponding to the malfunctioning circuit unit. A display device characterized in that it occurs when 2. A display panel in which a control terminal is provided as a scanning electrode at the intersection of a plurality of scanning electrodes and a plurality of signal electrodes, a pair of main terminals are provided between a display body and a signal electrode, and transistors are arranged; In a display device in which a scanning-side drive circuit that generates a signal to be applied to an electrode and a signal-side drive circuit that generates a signal to be applied to the plurality of signal electrodes are formed on a single substrate, the scanning-side drive circuit and At least one of the signal-side drive circuits includes a plurality of circuit units that generate a signal to be applied to at least one electrode in response to a distributed input signal among continuous input signals of a predetermined number of bits. do,
and at least one auxiliary unit having substantially the same operational function as the circuit unit, and when at least one of the circuit units malfunctions, an input signal to the malfunctioning circuit unit is provided. is applied to the auxiliary unit, and the auxiliary unit generates a signal to be applied to at least one electrode corresponding to the malfunctioning circuit unit. 3. A display panel in which a display body is arranged at the intersection of a plurality of scan electrodes and a plurality of signal electrodes, a scan-side drive circuit that generates signals to be applied to the plurality of scan electrodes, and a signal to be applied to the plurality of signal electrodes. In a display device having a signal-side drive circuit that generates a signal, at least one of the scanning-side drive circuit and the signal-side drive circuit generates a divided input signal of a continuous input signal of a predetermined number of bits. It has a plurality of circuit units that generate a signal to be applied to at least one electrode in response to is applied to the other circuit unit so that the other circuit unit generates a signal to be applied to at least one electrode corresponding to the circuit unit in which the malfunction has occurred. 4. A display panel in which a display body is arranged at the intersection of a plurality of scan electrodes and a plurality of signal electrodes, a scan side drive circuit that generates signals to be applied to the plurality of scan electrodes, and a signal to be applied to the plurality of signal electrodes. In the display device, at least one of the scanning side driving circuit and the signal side driving circuit generates a signal to be applied to at least one electrode in response to an input signal. the circuit unit, at least one auxiliary unit having substantially the same operational function as the circuit unit, and storage means for storing malfunction of at least one of the circuit units. , applying an input signal to the malfunctioning circuit unit to the auxiliary unit based on the output of the storage means, and applying the signal to the at least one electrode corresponding to the malfunctioning circuit unit; A display device characterized in that it is generated by an auxiliary unit. 5. A display panel in which a display body is arranged at the intersection of a plurality of scan electrodes and a plurality of signal electrodes, a scan side drive circuit that generates signals to be applied to the plurality of scan electrodes, and a signal to be applied to the plurality of signal electrodes. In a display device having a signal-side drive circuit that generates a signal, at least one of the scanning-side drive circuit and the signal-side drive circuit generates a divided input signal of a continuous input signal of a predetermined number of bits. 1. A display device comprising a plurality of circuit units that generate a signal to be applied to at least one electrode in response to a signal, and resistor means for connecting outputs of the circuit units. 6. A data processing device comprising the display device according to claim 1 and an arithmetic processing device that transmits a control signal to the display device. 7. A display panel in which a display body is arranged at the intersection of a plurality of scan electrodes and a plurality of signal electrodes, a scan-side drive circuit that generates signals to be applied to the plurality of scan electrodes, and a signal to be applied to the plurality of signal electrodes. a display device having a signal-side drive circuit that generates a signal; and an arithmetic processing device that processes an instruction to detect malfunction of at least a portion of the scanning-side drive circuit and the signal-side drive circuit. Processing equipment. 8. A display panel in which a display body is arranged at the intersection of a plurality of scan electrodes and a plurality of signal electrodes, a scan side drive circuit that generates signals to be applied to the plurality of scan electrodes, and a signal to be applied to the plurality of signal electrodes. a display device having a signal-side drive circuit that generates a signal; and a display device that processes an instruction to detect malfunction of at least a portion of the scanning-side drive circuit and the signal-side drive circuit, and an instruction to remedy the malfunction. A data processing device comprising an arithmetic processing device. 9. A scan-side drive circuit for driving a display panel in which a display body is arranged at the intersection of a plurality of scan electrodes and a plurality of signal electrodes, and that generates a signal to be applied to the plurality of scan electrodes; at least one of the signal-side drive circuit that generates a signal to be applied to the signal electrode of the signal electrode has a plurality of circuit units that generate a signal to be applied to the at least one electrode in response to an input signal, and It has at least one auxiliary unit that has substantially the same operational function as the circuit unit, and when at least one of the circuit units malfunctions, the input signal to the malfunctioning circuit unit is transmitted to the auxiliary unit. A semiconductor integrated circuit device for driving a display panel, characterized in that the auxiliary unit generates a signal that is applied to the unit and applied to at least one electrode corresponding to the circuit unit that has malfunctioned. 10. A display panel in which a display body is arranged at the intersection of a plurality of scan electrodes and a plurality of signal electrodes, a scan side drive circuit that generates signals to be applied to the plurality of scan electrodes, and a signal to be applied to the plurality of signal electrodes. In the display device, at least one of the scanning side driving circuit and the signal side driving circuit generates a signal to be applied to at least one electrode in response to an input signal. and at least one auxiliary unit having substantially the same operational function as the circuit unit, and when the output of at least one of the circuit units differs from the reference output, An input signal to a circuit unit different from the reference output is applied to the auxiliary unit, and the auxiliary unit generates a signal to be applied to at least one electrode corresponding to the circuit unit different from the reference output. display device. 11. A display panel in which a display body is arranged at the intersection of a plurality of scan electrodes and a plurality of signal electrodes, a scan-side drive circuit that generates signals to be applied to the plurality of scan electrodes, and a signal to be applied to the plurality of signal electrodes. In the display device, at least one of the scanning side driving circuit and the signal side driving circuit generates a signal to be applied to at least one electrode in response to an input signal. and an electronic switch for selecting one of the plurality of circuit units, and the at least one electrode has an output of the circuit unit selected by the electronic switch. A display device characterized by applying a signal. 12. In a circuit configuration in which a plurality of circuit units having similar functions are arranged, a switch circuit having a function of changing the transmission direction of a signal arranged between the circuit units, a signal wiring for controlling the switch circuit, A bus line for transmitting the voltage output from each switch circuit, and one or more spare circuits having the same function as each of the above circuit units connected to the bus line and connected to the same bus line. A circuit that processes signals from each switch circuit and a circuit that judges the output data of this signal processing circuit are provided to detect the presence or absence of defects in the circuit when the entire circuit starts operating or during a certain period of operation. The detection operation is performed, and information on the presence or absence of a defect is output from each switch circuit. If there is a defect, the switch circuit is configured to bypass the defective part and bypass the signal voltage to the backup circuit during normal operation of the circuit. A semiconductor integrated circuit device that generates signals to control. 13. The semiconductor integrated circuit device according to claim 12, wherein the switch circuit arranged between the circuits has a memory function and has a function of holding information on voltages for controlling the switch circuit. 14. The semiconductor integrated circuit device according to claim 12, wherein at least two types of each circuit are formed on the same substrate or the same glass substrate. 15. The semiconductor integrated circuit device according to claim 12, wherein at least a portion of the same wiring is used as the testing wiring and the signal detour wiring. 16. A semiconductor integrated circuit device according to claim 12, characterized in that at least a portion of the switch circuit for testing and the switch circuit for signal detouring are shared. 17. A semiconductor integrated circuit device as set forth in claim 12, characterized in that the method for determining a defective portion is a method of comparing captured information with determination information that has been input in advance.