JPH01223505A - Sequence controller - Google Patents

Abstract

PURPOSE:To immediately execute the sequence processing of a sequence controller by reading and decoding contents of a sequence extended memory of a program memory before execution by a multibit processor. CONSTITUTION:An 8-bit microcomputer 8 reads out and decodes a first sequence extension instruction in a microcomputer memory 9 at the time of the start of execution of the sequence processing and is held. When a sequence extension instruction is read out from a program memory 3, the control right of an I/O 6 on a microcomputer bus 4 is transferred from a one-bit processor 1 to the microcomputer 8 by a switching circuit 7, and the held microcomputer 8 immediately executes the processing of the first sequence extension instruction for the I/O 6. The microcomputer 8 waives the control right, and the control right is transferred to the processor 1 by the circuit 7. Meanwhile, the microcomputer 8 which waives the control right reads out and decodes a second sequence extension instruction in the memory 9, and the microcomputer 8 is held till the control right is transferred to it by the circuit 7.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a sequence controller comprising a combination of a 1-bit processor and a multi-bit processor (generally an 8-bit processor or a 16-bit processor).

Conventional technology Sequence controllers using 1-bit processors are not good at processing arithmetic instructions or making complex decisions, while sequence controllers using multi-bit processors have a higher number of steps to execute sequence instructions than 1-bit processors. There is a problem in that the processing time is two to three times longer than in the conventional case.

Therefore, attempts have been made to configure a sequence controller by combining a 1-bit processor and a multi-bit processor so as to combine the advantages of both. Fourth
The figure shows a conventional example of such a sequence controller.

This conventional example combines a 1-bit processor 11 and a multi-bit processor 12, and has a program memory 13.
Normally, the 1-bit processor 11 executes sequence basic processing according to instructions from 10), the controller is configured to release control of the processor 1016 on the microcomputer bus 14 and wait until the multi-bit processor 12 finishes processing the sequence extension instruction. Note that 16 is a data superimposition circuit that superimposes the processing result of the 1-bit processor 11 on the data on the microcomputer bus 14, and 17 is a switching circuit that switches the processors 11 and 12 that process l1016 on the microcomputer bus 14 according to a sequence instruction. be.

Problems to be Solved by the Invention According to the above-mentioned conventional example, when the instruction in the program memory 13 is a sequence extension instruction, the multi-bit processor 12 that is interrupted by the 1-bit processor 11 executes the sequence in the program memory 13. After reading the extended instruction and decoding its contents, the l101e on the microcomputer bus 14 must be controlled, which poses a problem in that extra time is required to read and decode the instruction.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention has a program memory for storing a sequence program, a 1-bit processor that executes sequence basic processing according to instructions from the program memory, and a 1-bit processor 1. A data superimposition circuit that superimposes the processing result with data on the microcomputer bus, I/O on the microcomputer bus 4 processed by the data superimposition circuit, and sequence extension processing when the instruction in the program memory is a sequence extension instruction. The method comprises a multi-bit processor for execution, and means for switching processors for performing sequence processing according to the instructions in the program memory, and the multi-bit processor prereads and decodes the contents of the sequence extension instructions in the program memory before executing them. The present invention is characterized in that the multi-bit processor is configured to eliminate the time required for reading and decoding sequence extension instructions from the program memory when the control of sequence processing is switched to the multi-bit processor by the processor switching means. shall be.

Effect According to the above configuration, when the content of the program memory is a sequence extension instruction, when the control right of sequence processing is transferred from the 1-bit processor to the multi-bit processor by the means for switching processors, the multi-bit processor It does not require time to read and decode instructions, and can be sent to Ilo on the microcontroller bus immediately.
Sequence processing can be performed.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG. The embodiment shown in FIG. 1 shows a sequence controller in which a general-purpose microcomputer 8 equipped with an 8-bit processor and a 1-bit processor 1 are combined. 2 shows an example of the content of sequence instructions stored in the program memory 3, and FIG. 3 shows an example of the content of sequence extension instructions stored in the microcomputer memory 9.

The sequence controller of this embodiment includes a 1-bit processor 1 that executes sequence 7 basic processing, a data superimposition circuit 5 that superimposes the processing result of the 1-bit processor 1 on data on a microcomputer bus 4, and a sequence expansion process. The 8-bit microcomputer 8, the microcomputer memory 9 that stores only sequence extension instructions, the switching circuit 7 that switches the processor that processes the process 106 on the microcomputer bus 4 according to sequence instructions, and the 1-bit processor 1 and the 8-pin microcomputer 8 process A program memory 3 is provided to store all the sequence instructions to be executed.

Before the sequence controller executes sequence processing, the 8-bit microcomputer 8 sequentially reads out the contents of the program memory 3 shown in FIG. Store it in.

When the sequence controller starts executing the sequence processing mt-, the 8-bit microcomputer 8 reads and decodes the first sequence extension instruction stored in the microcomputer memory 9, and the control right of the sequence processing is switched by the switching circuit 7. via) Waits until the data is transferred from the processor 1 to the 8-bit microcomputer 8. Normally, the 1-bit processor 1 sequentially transfers data to the microcomputer bus 4 according to instructions in the program memory 3.
Sequence basic processing is executed for the above l10s.

When the instruction in the program memory 3 becomes a sequence extension instruction, the switching circuit 7 causes the ! 106
The control right is given to the 1-bit processor 16 to execute processing of the first sequence extension instruction stored in the microcomputer memory 9. Next, the 8-bit microcomputer 8 relinquishes all control of sequence processing, and the switching circuit 7 transfers control to the 1-bit processor 1.
again executes the sequence basic processing in accordance with the program memory 3.

On the other hand, the 8-bit microcomputer 8, which has relinquished the control right, reads and decodes the second sequence extension instruction stored in the microcomputer memory 9, and one control of the sequence processing is transferred to the switching circuit 7. , 1-bit processor 1 to 8
It waits until it is transferred to the bit microcomputer 8.

Sequence expansion processing is performed on the sequence.

According to this embodiment, when the instruction in the program memory 3 is a sequence extension instruction, the 8-bit microcomputer 8 to which control is transferred from the 1-bit processor 1 executes the sequence extension for OI; 106iC on the microcomputer bus 4. When executing processing, no extra time is required to read the sequence extension instruction from the program memory 3 and decode its contents.

Effects of the Invention According to the present invention, it is possible to provide a sequence controller that allows a multi-bit processor to eliminate the time required for reading and decoding sequence extension instructions from a program memory.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing one embodiment of the present invention, and FIG. 4 is a circuit configuration diagram showing a conventional example. 1... 1-bit processor, 3... Program memory, 4... Microcomputer bus, 6...
...Data superimposition circuit, 6...Ilo, 7.
...Switching circuit, 8...8-bit microcomputer. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Map area 0 only 7

Claims (1)

[Claims] In a sequence controller that is a combination of a 1-bit processor and a multi-bit processor, there is a program memory that stores a sequence program, a 1-bit processor that executes basic sequence processing based on instructions from this program memory, and a 1-bit processor that processes the processing results of the 1-bit processor. A data superimposition circuit that superimposes data on the microcomputer bus, I/O on the microcomputer bus that is processed by the data superimposition circuit, and a multi-bit that executes sequence extension processing when the instruction in the program memory is a sequence extension instruction. The multi-bit processor prereads and decodes the contents of the sequence extension instructions in the program memory before execution, and the processor switching means switches the processor to perform sequence processing according to the instructions in the program memory. A sequence controller characterized in that the multi-bit processor is configured to eliminate the time required for reading and decoding sequence extension instructions in a program memory when control of processing is switched to the multi-bit processor.