JPH01222469A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the area that a capacitor electrode occupies and to enhance high integration of DRAMs by a method wherein a titanium nitride film is provided between a capacitor electrode built of polycrystalline or single-crystal silicon and a dielectric film high in relative dielectric constant. CONSTITUTION:A dynamic memory (DRAM) capacitor of this design employs a highly dielectric film of tantalum oxide or hafnium oxide. A titanium nitride film is positioned between a polycrystalline or single-crystal silicon electrode and the tantalum oxide dielectric film. In the case that one of the capacitor electrodes is made of a high melting-point metal such as W or Si-added W, a W or Si-added W film is selectively deposited on an Si substrate, which is useful in flattening the surfaces on which highly dielectric material is deposited. In this way, a film can be formed very thin, which contributes to the enhancement of capacitor capacity or to the reduction of the capacitor area.

Description

[Detailed Description of the Invention] [Summary] The present invention typically relates to the structure and manufacturing method of a capacitor portion of an ITr type DRAM, and aims to reduce the area of capacitor electrodes and thereby increase the integration of DRAM. A dielectric film of T a 20. Or HfO
A high dielectric constant material selected from Z, and a conductive layer in contact with the high dielectric constant material film are made of TiN.

The TiN layer is connected to the capacitor electrode or poly-Si.
It functions as a barrier film to prevent the reaction of zos, and
In a manufacturing method in which the electrode on the substrate side is formed by selective growth of W, the W layer is formed thickly, and the coverage of the upper layer is improved.

[Industrial application field]

The present invention typically relates to a one-transistor type dynamic memory device (DRAM), and particularly relates to the structure and manufacturing method of a capacitor thereof.

DRAM, which consists of one MOS transistor and one capacitor, is one of the most highly integrated ICs, and 1M bit memory devices are being put into practical use, and 4M bit and 16M bit memory devices are being put into practical use. It is believed that the development of bit ICs will not be far in the future.

High integration is accompanied by miniaturization of elements, and 1Tr type D
In RAM, the most important point in miniaturization is how to miniaturize the capacitor. This is because when the capacitance of a capacitor becomes small, soft errors are more likely to occur and the stored contents become less reliable, so miniaturization is required without reducing the capacitance value. It is.

The same situation applies to memory cells made up of a plurality of transistors and capacitors.

[Conventional technology]

A technique that has been developed in the past to meet these unmatched demands is a trench-type capacitor technique in which a capacitor is formed using a surface perpendicular to the substrate surface. That is, in order to reduce the area occupied within the substrate plane and increase the electrode area,
It attempts to obtain usable surfaces in the depth direction, and RIE
This has been made possible by advances in anisotropic etching technology such as .

However, in order to further improve the integration density, this type of shape improvement alone is not sufficient, and other measures must be used in combination.

A possible solution to this problem is to reduce the electrode area by using a material with a high dielectric constant for the dielectric film of the capacitor. The dielectric film of a normal DRAM is a combination of SiN and SiO□, but if this could be replaced with tantalum oxide (Ta Mio) of the same thickness, the dielectric constant would be approximately S times as large. It becomes possible to reduce the electrode area to about 115. Like TazOs, HfOz is a material with a high dielectric constant.

In reality, Ta and O3 do not have any good insulating properties, and it is necessary to increase the film thickness, so it is difficult to expect the electrode area to be reduced by the above numerical value.

[Problem to be solved by the invention]

When attempting to use Ta, O, as a dielectric film of a capacitor, in addition to the fact that the insulation properties are insufficient, consideration must be given to suppressing the reaction with St. Ta
Although zOs is a relatively stable substance, when a capacitor electrode is formed of an active substance such as Si, a reaction gradually progresses and the dielectric strength decreases. Therefore, as shown in FIG. 4, it is not possible to realize a good RAM simply by changing the dielectric film of a normal DRAM capacitor to Ta or O. In the figure, 1 is a MOS transistor, 2 and 4 are capacitor electrodes, and here polyS
i, 3 is a T at Os dielectric film.

Further, although the TazOs film is usually deposited by sputtering, this Ta, 0. The film has poor coverage and DR
When it has to be deposited on a highly uneven surface, such as in an AM capacitor, it is difficult to obtain sufficient insulation. The same situation applies to HfOz.

An object of the present invention is to provide a DRAM capacitor in which reaction with St does not proceed even when a high dielectric constant material is used as a dielectric film and poly-Si is used as an electrode material, and other objects It is an object of the present invention to provide a method for manufacturing a RAM capacitor that reduces the undulations of a surface to be formed by depositing a high dielectric constant material as a dielectric film, and provides good insulation even with a material that does not have sufficient covering properties.

[Means to solve the problem]

To achieve the above object, the DRAM capacitor of the present invention has a dielectric film made of a high dielectric material film selected from tantalum oxide or hafnium oxide, and a polycrystalline or single crystal silicon electrode of the capacitor and the tantalum oxide dielectric film. The structure is such that a titanium nitride film is interposed between the film and the film.

In addition, in a manufacturing method in which one electrode of a capacitor is made of a high melting point metal such as W or Si-doped W, W or Si-doped W is selectively deposited on the Si substrate surface by the CVD method, and a high dielectric constant material is deposited. This is done to reduce the undulations in the desired area.

[For production]

The titanium nitride film provided between 5tJii and tantalum oxide or hafnium oxide functions as a barrier film and suppresses the reaction between the two. Also, selective CVD deposition of W is
Since it is performed on a depression such as an exposed part of the i-substrate surface, the undulations of that part are reduced, and even if a material with poor coverage is deposited, non-uniformity in thickness is less likely to occur.

〔Example〕

FIG. 1 is a schematic cross-sectional view showing a first embodiment of the device of the present invention, in which 1 is a MOS transistor portion, 2 and 4 are poly-Si
Electrode 3 is a 20g Ta film. The difference from the DRAM of FIG. 4 is that thin films 5 of TiN are interposed between the upper and lower poly-Si electrodes and the Ta, O, and films, respectively.

When a thin film of TiN is interposed between the poly-Si[ and Ta, O, . Since this reaction is suppressed, the withstand voltage of the dielectric film does not decrease, resulting in high reliability.

The film thickness of Ta, O, and the like is about 150 to 200, and the TiN thin film is effective as a barrier when the thickness is about 500 to 1,000.

The thickness of the poly-Si layer is 3000-4000. Ta
, 03 have a large dielectric constant, and when formed to have the same capacity as a conventional element, the element area can be reduced.

FIG. 2 is a schematic cross-sectional view showing a second embodiment of the device of the present invention, in which 1 is the same as the one in FIG. 1 in that it is a MOS transistor. The electrode is a Ti layer 6, and there is a Ti layer between Ta, O, and the film 3.
A thin film 5 of N is provided. The upper electrode of the capacitor is a TiN layer 5' formed thicker than the TiN thin film 5. The specific resistance of TiN is about 100 μΩ, and it can be formed to have the same electrical conductivity as that of ordinary poly-Si, and the surface flatness can be slightly improved.

FIG. 3 shows a DRAM formed by the manufacturing method of the present invention.
FIG. 2 is a schematic cross-sectional view showing the structure of an element. The method for manufacturing the device will be described below, but since the MOS transistor portion is manufactured using the same method as usual, only the method for manufacturing the capacitor portion will be described.

The insulating film on the surface of the capacitor region 7, which is also the S/D of the MO3I-transistor, is removed, and a CVD process is performed using tungsten hexafluoride and monosilane (WF4+S i Ha) as raw materials and Hz as a carrier gas.
Since St-doped W is selectively deposited only on the exposed surface, the depressions above the capacitor region 7 are covered with deposited WJti8.
filled with. This Si-added layer can be deposited to a thickness of about 3000, and this becomes the lower electrode of the capacitor.

The TiN thin film 5, the TazO dielectric film 3, and the Ti film 3, which is the upper electrode of the capacitor, are then deposited by a known deposition method.
By forming the N layer 5', an element having the structure shown in FIG. 3 is completed.

In the DRAM device formed by the manufacturing method of this embodiment, the Taxes film is deposited on a relatively flat surface, which reduces coverage problems and allows for a thinner film. Therefore, it is possible to increase the capacitance of the capacitor or reduce the area of the capacitor.

〔Effect of the invention〕

As explained above, the DRAM element of the present invention has a smaller element area and a capacitor of the same capacity than the known element. Further, according to the method of manufacturing a DRAM element of the present invention, a DRAM element that is smaller than known DRAM elements can be manufactured.
M element is realized.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional diagram showing the structure of the device of the first embodiment, FIG. 2 is a schematic cross-sectional diagram showing the structure of the device of the second embodiment, and FIG. 3 is a schematic cross-sectional diagram showing the structure of the device of the second embodiment. Fig. 4 is a schematic cross-sectional view of a DRAM element in which the constituent materials of a known element are changed; 5 is a TiN thin film, 5' is a TiN layer, 6 is a Ti layer, 7 is a capacitor region, and 8 is a W layer. FIG. 1 is a cross-sectional schematic diagram showing the structure of the device of the first embodiment. FIG. 2 is a schematic cross-sectional diagram showing the structure of the device of the second embodiment. FIG. Figure 3 I Schematic cross-sectional diagram of a DRAM element in which the constituent material of the known element in the MOSTr part is changed Figure 4

Claims (3)

[Claims] (1) In a semiconductor memory device composed of a MOS transistor and a capacitor, the dielectric film of the capacitor is a film of a high dielectric constant material selected from tantalum oxide or hafnium oxide, and the dielectric film of the capacitor is a polycrystalline or monocrystalline material film selected from tantalum oxide or hafnium oxide. 1. A semiconductor memory device comprising a titanium nitride film interposed between a crystalline silicon electrode and the high relative permittivity dielectric film. (2) In a semiconductor memory device composed of a MOS transistor and a capacitor, the dielectric film of the capacitor is a high dielectric material film selected from tantalum oxide or hafnium oxide, and one electrode of the capacitor is made of titanium nitride. A semiconductor memory device, wherein the other electrode is a high melting point metal, and a titanium nitride film is interposed between the high melting point metal electrode and the high relative dielectric constant material film. (3) After depositing a layer containing tungsten as a main component by selective CVD on a silicon substrate in a region where the capacitor of a semiconductor memory device composed of a MOS transistor and a capacitor is formed, a titanium nitride film and the above-mentioned 1. A method for manufacturing a semiconductor memory device, comprising the steps of sequentially depositing and patterning a dielectric constant material film, and further depositing a titanium nitride electrode layer.