JPH01221727A - Optical logic element - Google Patents

Abstract

PURPOSE:To make an optical logic element more advantageous for integration by employing pnpn elements for a bistable element. CONSTITUTION:The anodes 24 of the pnpn elements A11 and B12 and their cathodes 25 are directly connected, and a resistance 15 and a power source 16 are serially connected. Unless input light 8 is made incident, output light 10 is emitted, whereas when the light 8 is made incident, the output light 10 is not emitted. Since information is held until a negative reset signal is impressed, the input light is made incident only in a short time. Therefore, a light source consumes power in small quantities. The title element is composed of only two pnpn elements of the same structure, which is advantageous for integration. Since optical feedback, etc., between constitutes are not needed, strict optical isolation is not required.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to an optical logic element with high photosensitivity.

(Prior Art) It is expected that light will be used for large-capacity, high-speed processing of information, and in recent years, research and development of optical functional elements that can be integrated have been actively conducted for this purpose.

Among these, optical bistable devices have attracted attention as a fundamental element of optical signal processing devices, and various types of devices have been proposed and studied. Here, if there is an optical input/output inverter and an AND element, all optical input/output logic devices can be configured in principle by combining them. Various types of AND elements have been proposed, but a proposal for an inverter was made by Coloph et al. in the Journal of the Institute of Electronics and Communication Engineers No. J-66 (
5), 1983, pp. 393-400.

FIG. 9 shows the configuration of a conventional optical input/output inverter element. The light receiving element 1 and the feedback LED 2 are connected in series,
A part of the current flowing through the light receiving element flows to this LED, and its output light is positively fed back to the light receiving element 1 as feedback light 9.

Therefore, optical bistability occurs in this system. Return LE
D2 and the light output LED 3 are connected in parallel so that their output characteristics are reversed. The resistor 5 is a resistor for giving the output a saturation characteristic, and the resistor 6 is a resistor for changing the threshold for causing a jump between the two heirloom states. The diode 4 is a diode required to reduce the optical output when the optical output is in the OFF state.

(Problems to be Solved by the Invention) In the conventional inverter element described above, a part of the photocurrent generated by the input light 8 incident on the light receiving element 1 is transferred to the feedback LED.
Positive feedback is applied to the light receiving element 1 as feedback light 9 flowing to 2,
Optical bistability occurs due to optical feedback. However, there are many types and quantities of light-receiving elements, LEDs, diodes, resistors, and circuit components, and a large number of them are integrated into a monolithic structure, resulting in a complicated problem. In addition, since it is optically bistable using feedback of light, the optical eye relation was extremely difficult for integration. Furthermore, when the human power light 8 is turned off, the output light 10 also disappears. Therefore, pre-input light is always required for output from the inverter, and when inverter elements are arranged in a planar matrix, there are problems of increased power consumption by the light source and temperature rise.

An object of the present invention is to provide an optical logic element that can solve the problems of the prior art, such as the large number of parts due to integration, optical isolation problems, and power consumption problems.

(Means for solving the problem) The present invention has a pnpn junction and has a light-emitting layer having a first forbidden band width inside, and the light-emitting layer has a forbidden band width of the first bandgap.
In an optical logic element including a pnpn element having a structure in which both sides are sandwiched between semiconductor layers wider than the forbidden band width of the pnpn element, two pnpn elements with different switching voltages and these elements for driving the pnpn element are used. The present invention provides an optical logic element characterized by comprising a common power source and a resistor connected in series to this power source.

Furthermore, if a resistor is connected in series to at least one of the pnpn elements, an optical logic element with a wide range of uses can be provided, as will be described later.

(Function) Since the optical logic element of the present invention is composed of only a pnpn element and a resistor, it can be easily integrated. Furthermore, since optical feedback is not used, there is no need to consider optical isolation issues.

Furthermore, by utilizing the holding mechanism in the ON state, which is a characteristic of the pnpn element, it is possible to maintain the inverter operation with low power consumption.

FIG. 7 and FIG. 8 are diagrams for explaining the bistability of the pnpn element. FIG. 7 is a circuit configuration diagram, and FIG. 8 is a current-voltage characteristic diagram.

A resistor 21 and a power supply 20 are connected to the anode 24 of the pnpn element 28.
are connected in series (Fig. 7), the power supply 20
When a positive voltage is applied to the anode 24 side and the voltage is increased without incident light, a current-voltage characteristic 26 without incident light shown in FIG. 8 is obtained.

In FIG. 8, switching occurs when the voltage is So. The operating point is the intersection of the load resistance line 1 (33) determined by the resistor 21 and power supply 20 and the current-voltage characteristic 26 shown in FIG. 7, but as the voltage is increased, it moves from point A 29 to point 8 30. At this time, light is emitted from the pnpn element and output light 10 shown in FIG. 7 is emitted to the outside. When the input light 8 is incident, the current-voltage characteristics of the pnpn element 28 become the current and voltage characteristics 27 with incident light shown in FIG. 8, and the switching voltage becomes S.
becomes. Therefore, when the voltage of the power supply 20 in FIG. 7 is set to the voltage v1 between S and So and the input light 8 is incident on the pnpn element 28, it moves from the 0 point 31 in FIG. 8 to 0 on the load resistance line 2 (33). Moving to point 32, light emission occurs. Then, output light 10 shown in FIG. 7 is emitted to the outside. The pnpn element is the seventh
The light emitting state can be maintained until the voltage of the power supply 20 shown in the figure is set to Vh or lower. Therefore, even if the input light 8 disappears, the output light 10 continues to be emitted.

As can be seen from the above, such a pnpn element emits optical output along with input light, and can obtain optical bistable characteristics that also have a holding function. The state in which optical output is emitted is stored in the element even if the voltage is lowered to the holding voltage V. Therefore, by doing so, it becomes possible to maintain the light emitting state with low power consumption. The inverter configuration and its effects will be described in detail in Examples below.

(Example) FIG. 1 is a diagram showing a first embodiment of the present invention.

The pnpn element All and the pnpn element B12 are pnpn elements having the structure described above, and the anodes 24 and cathodes 25 of each are directly connected, and the resistor 15 (50Ω in this embodiment) and the power supply 16 are further connected in series. It is connected.

Although an AlGaAs/GaAs based pnpn element was used as the pnpn element, the pnpn element is not limited to this material type. pnpn elements All and pnpn
Element B12 has current-voltage characteristics shown in FIG.

When there is no radiation in the pnpn element A element, the switching voltage is 80 and the holding voltage is V (20).

Then, by inputting 10 μW of light with a wavelength of 0.8 pm, the switching voltage becomes S3 (22). When there is no light emitted from the pnpn element B, the switching voltage is 82, the holding voltage is vh, and the holding current is Ih (21). When voltage S1. S2
．． S3. ■H is set so that vh<S3<S2<So (in this embodiment, V=1.5V, 53=2V).

52=3v, 53=5v). In addition, in the ON state, when the voltage is higher than vh, both pnpn element A element - 5
It has a differential resistance of Ω. In addition, ■ and were 500 pA. Here, a voltage pulse shown in FIG. 3(a) is applied from the power supply 16 in FIG. 1. At this time, V is a voltage of S, >V, >S2 (in this embodiment, V5: 4V). Also the first
In FIG. 3, when the optical input shown in FIG. 3(b) is input to the pnpn element All shown in the figure, the voltage applied from the power supply 16 increases from Vr (<O) to V at time t1. At that time, since the pnpn element A in the OFF state also exhibits high resistance, almost all the applied voltage is applied to the pnpn element A.
join. When the voltage increases to 82, it becomes the same voltage as the pnpn element B element photo-etching voltage, so that the pnpn element B element enters the optical state. Along with this, the pnpn element B element starts emitting light and emits optical output (Fig. 1).The power supply voltage increases to V, but the pnpn element B element optical voltage is almost fixed at about V in the ON state. pnpn element A element cannot be in the state. Until time t2, the power supply voltage is 5, and the pnpn element B remains in the optical state and continues to emit optical output. At time t2, the power supply voltage drops from vb to vr. When (2) becomes a negative voltage, the pnpn element A is reset and returns to the OFF state. Further, at time t3, the power supply voltage rises from vr to V, and light is incident on the pnpn element A11 (FIG. 1) at this timing. Then, when the power supply voltage exceeds 83, p
The npn element becomes the A element-state. Power supply voltage is from S3 to v
However, this time, since the pnpn element A hardly increases from the pnpn element B element, the pnpn element B cannot enter the optical state and cannot emit light. From the above, if the input light 8 in FIG. 1 is not incident, the output light 10 is emitted, and conversely, if the input light 8 is incident, the output light 10 is not emitted. This shows that an optical inverter has been realized. Further, since information is retained until a negative reset signal is applied by the power supply voltage, input light only needs to be incident for a short period of time. From now on, at least the power consumption by the light source will be eliminated. In the above story, pnpn
Element A Element - no series resistor connected, anode 2
4 and the cathode 25 are connected to each other.

As shown in Figure 4, a resistor R0 is connected in series with the pnpn element All.
13. When a resistor is connected in series to the pnpn element B12, it is necessary to set R1 and R2 so that when S2 is V>81, V<81. Here, V is the power supply voltage, VhA is the pnpn element A element-ruding voltage, vhB is the pnpn element B element photo-ruding voltage, and RFA is the differential resistance above the holding voltage in the pnpn element A element state. RFB is the differential resistance above the holding voltage in the pnpn element B element optical state.

In the first example, since Sl<v<81, (1), (
3) Use the formula. By substituting the values of the elements used in the first embodiment, R1<70Ω, and any value will work well for the bird.

In the first embodiment, the cathode and anode are each short-circuited, so R1=H=0Ω, and the R1 actually used
．． It can be seen that the value of R2 satisfies the conditions of equations (1), (2), and (3).

FIG. 5 is a diagram showing a second embodiment of the present invention.

A resistor 14 (1 in this embodiment) is connected in series with the pnpn element B12.
Ω) is connected to pnpn element All and pnpn element B
12 anodes 24 are connected to each other, pnpn elements All
The cathode 25 of the resistor 14 is connected to a terminal opposite to the cathode 25 of the pnpn element B12 of the resistor 14, and the resistor 15 and the power supply 16 are connected in series thereto. Here, the same components as those used in the first embodiment were used except for the resistor 14.

Here, the power supply voltage shown in FIG. 6(a) is applied from the power supply 16 of FIG. 5. The input light shown in FIG. 6(b) is input to the pnpn element All. From FIG. 6, the voltage applied from the power supply 16 increases from Vr to V in tlo. PNPN element B1 with low switching voltage as in the first embodiment
3 becomes ON and output light 10 is emitted (Fig. 5)
. tl when input light 8 does not enter pnpn element All
When voltage vb continues to be applied until , optical information is retained and output light continues to be emitted. At that time, pnpn element All has p
A voltage equal to the sum of the holding voltage of the npn element B13 and the voltage drop across the resistor 14 is added, and in this embodiment, this value is approximately 2.4V. When the input light 8 is incident on the pnpn element All, a voltage of 83 or more (2V in this example) is applied, so it becomes ON.When the pnpn element All becomes ON, the voltage across the pnpn element All is almost in the holding state. In order to reach the voltage VhA (1.5V in this example), the current flowing through the pnpn element B12 and the resistor 14 decreases to about 230 V in this example.
It became pA. At this time, the elbow of pnpn element B12 is 230
If it is more than 11A, it will not be possible to maintain the ON state and O
It becomes an FF state, and the output light 10 is no longer emitted at time t14 as shown in FIG. 6(e).

1. Of the elements used in the examples. was 500 pA.

This state continues until reset at time Ltt.

At time t1□, the power supply voltage increases again to V, and the output light is 10
is emitted. During the period from time t□2 to time t□3 when the power supply voltage V is applied, no input light is incident, so the output light 10 continues to be emitted. Further, the output light A17 is not emitted. From the above, the second embodiment performs the operation of the first embodiment, and further enables resetting by light, making it possible to apply it to other applications than inverters. The above is R in Figure 4.
1: We took the example of connecting O, R, , = IKΩ, but
Generally speaking, it is necessary to satisfy certain conditions. In this example, equation (4) is 1.5<3.9<5, and equation (5) is 1.51<1507.
Therefore, the above conditions are satisfied.

The pnpn element A used in this example is S,
=5V, V)lA=1.5V, pnpn element B is S
2:3V, ha = 1.5V.This is a device with the characteristics of 2:3V, ha=1.5V.This is a device that uses the same device and connects a resistor between the n gate and the cathode. 1 by connecting Ω to
2-185926. ) Here, formulas (1) to (5)
Since the effects of the present invention can be obtained as long as the pnpn element satisfies the above conditions, other specifications are not specified. The device of the present invention uses the threshold characteristics of a pnpn device in addition to an inverter, and allows multiple input lights to enter the device to perform NAND or NO.
R can be realized. Also, pnpn element A and pnpn element B
By changing the forbidden band width of the light-receiving layer and the light-emitting layer, optical calculations and optical information memory using light of any wavelength can be realized.

In the pnpn element of this example, 1 pJ (for example, 0.1 mW
It is possible to perform optical calculations and write optical information using light with a light energy of 10 ns incident for 10 ns.

This embodiment is advantageous for integration because it can be configured with only two pnpn elements having the same structure.

Furthermore, since there is no need for light feedback between component parts, the light efficiency is improved.

(Effects of the Invention) As explained above, according to the present invention, by using a pnpn element as a bistable element, it is advantageous for integration.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an optical logic element according to a first embodiment of the present invention;
FIG. 2 is a current-voltage characteristic diagram of the pnpn element used in FIG. 1, FIG. 3 is a diagram explaining the driving method of the optical logic element of the first embodiment shown in FIG. 1, and FIG. 5 is a diagram for explaining the components of the present invention. FIG. 5 is a configuration diagram of an optical logic element according to a second embodiment of the present invention. FIG. 6 is a diagram illustrating the optical logic element according to a second embodiment shown in FIG. Figure 7 is a diagram for explaining the driving method, Figure 7 is a diagram for explaining the operation of the pnpn element, Figure 8 is a current and voltage characteristic diagram of the pnpn element shown in Figure 7, and Figure 9 is an optical inverter according to the prior art. It is a block diagram of an element. In the figure, 1... Light receiving element, 2... LED for feedback, 3... LED for light output, 4... Diode, 5, 6, 13, 1
4,15.21...Resistor, 7.16.20...Power supply, 8...Input light, 9...Return light, 10.17...
Output light, 11 pnpn element A element flow - pnpn element B
Element current... pnpn element A element current-voltage characteristics when there is no input light, 21... pnpn element B element current-voltage characteristic when there is no input light, 22... pnpn when there is input light Element A element current-voltage characteristics, 23...Load resistance wire 2.24...Anode, 25...Kalide, 26
...Current-voltage characteristics of the pnpn element when there is no incident light, 27...Current-voltage characteristics of the pnpn element when there is incident light, 28...pnpn element, 29...point A, 30 ... point B, 31...0 point, 32... point D,
33...Load resistance line 1.

Claims (2)

[Claims] (1) It has a pnpn junction and has a light-emitting layer having a first forbidden band width inside, and the light-emitting layer is sandwiched on both sides by semiconductor layers whose forbidden band width is wider than the first forbidden band width. In an optical logic element including a pnpn element with a structure of An optical logic element comprising: (2) The optical logic element according to item 1, wherein a resistor is connected in series to at least one of the pnpn elements.