JPH01217535A - How to control the additional processor unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a computer system, and particularly to an additional processor unit in a system in which a dedicated processor unit for an AI language such as PROLOG or LISP is added to a main processor unit. Regarding the control method.

[Conventional technology]

Conventionally, methods for processing AI language include (1) converting the AI language into machine language on a general-purpose processor and directly executing it; (2) converting the AI language into an intermediate language suitable for the AI language; Examples include a method in which the intermediate language is interpreted and executed by an interpreter.

Method (2) has advantages over method (1), such as a smaller amount of processing required for program conversion and a smaller program capacity after conversion.

Further, as a means for improving the processing speed of the interpreter in method (2), a method (3) has been proposed in which the interpreter processing is performed on a dedicated processor. The dedicated processor uses machine language as the intermediate word in method (2), and executes the machine language under microprogram control. Method (3) maintains the above advantages of method (2) and reduces the number of memory accesses for fetching instructions. Due to characteristics such as parallel processing of microinstructions on a field-by-field basis, processing speed is improved over method (2).

AI language processing systems that adopt method (3) include, for example, the Information Processing Society of Japan's Symbol Processing Study Group 23-1 (
(1983), pages 1 to 8.

[Problem to be solved by the invention]

In the above AI language processing system using a dedicated processor (3), in order to reduce the size and complexity of the dedicated processor, the main processor usually performs some of the interrupt processing, input/output processing, etc. I have no choice but to share.

In this case, it is necessary to pass parameters, control program startup, etc. between the main processor and the dedicated processor, and on the main processor side, there are many changes to the program, such as the input/output management section of the OS, the process management section, etc. The problem was that it extended to

An object of the present invention is to control the additional processor to localize changes in the processor so that when a dedicated processor for AI language is used as an additional processor as described above, it is easy to change the program on the main processor side. The goal is to provide a method.

[Means to solve the problem]

The above objectives are: (1) to connect the main processor and an additional processor that processes AI language via a bus, and to assign bus mastership priority to the additional processor by the bus control unit; The processor is started by a privileged mode program in the driver layer of the OS or the application layer. (:3) When an additional processor requests processing by the main processor while it is operating, the type of request processing etc. (4) If an interrupt request, bus error signal, etc. is input while the additional processor is operating, the main cause of the stop is determined. (5) When the attached processor stops operating, the main processor sets it in the memory or a register in the attached processor unit to stop its operation. This is achieved by determining the cause of the stop, the type of requested processing, etc., and branching to the necessary program.

[Effect]

When the main processor starts up the attached processor from a privileged mode program in the driver layer of the OS or the application layer, the attached processor requests bus mastership from the bus control unit.

Since the bus mastership assignment priority is set high for the attached processor, the bus control unit transfers the bus mastership from the main processor to the attached processor.

As a result, the additional processor starts operating, while the main processor. The operation of a privileged mode program in the S driver layer or application layer is suspended.

Next, the additional processor processes the AI language program.

During this time, if processing by the main processor is required, the additional processor sets the type of processing, arguments, etc. in the main memory or a register (hereinafter referred to as the request area) in the additional processor unit, and starts the operation. Stop. Also,
When an interrupt request or a bus error signal is input, the type is set in the main memory or a register in the additional processor unit (hereinafter referred to as the stop cause area).
Stop operation.

When the additional processor ceases operation, bus mastership is assigned to the main processor. As a result, the main processor is unable to perform any of the above operations at any of the interruption points (in the driver layer of the OS, or in a privileged mode program in the application layer).
Resume processing from.

Here, in the program, after the process of starting up the additional processor, the process of determining the contents of the stop cause area and the process of determining the contents of the request area are performed in succession, thereby allowing branching to necessary processes. After processing, the program is re-executed to restart the operation of the attached processor from the point where it stopped.

Continue processing AI language.

As described above, the portions of the main processor's program that are related to the operation of the additional processor are limited to privileged mode programs in the driver layer of the OS or the application layer. These programs can be easily added to existing programs, and changes to the main program are facilitated.

〔Example〕

Hereinafter, one embodiment (Example 1) of the present invention will be described with reference to FIGS. 1 to 8. Embodiment 1 relates to a logical language processing system on a computer system according to the present invention.

This system converts a logical language source program into an intermediate language program.

It is an interpreter-based system that performs interpretation and execution, and is an operating system with multi-process functionality (
(hereinafter referred to as OS).

First, the hardware configuration of this system will be explained with reference to FIG.

In this system, CPU10I, additional processor unit (hereinafter referred to as APU) 102. Bus stop unit 103. Memory management unit 104゜main memory 1
05 and an input/output control unit 106 are coupled via a bus 110, and an auxiliary memory 107 is connected to the input/output control unit 106. Also, from outside the CPU
There is an interrupt line 111 to 0I.

An interrupt line 112 is connected from the CPU 10I to the APU 102.

A control line 113 is connected from the memory management unit 104 to the main memory 105, and a signal line 114 for transmitting a bus error signal is connected to the bus arbitration unit 103. Signal lines 115 and 116 are connected from the bus arbitration unit 103 to the CPU 10I and the APU 102, respectively, for transmitting bus error signals. An interrupt mask 120 is provided within CPUl0I. The interrupt mask 120 has a function of determining whether or not the CPU 101 accepts an interrupt request from the interrupt line 111.

FIG. 4 is a block diagram showing the hardware configuration of the APU 102. Inside the APU 102 is an execution unit 401. Order control unit 402. Control memory 403. It is divided into a bus control section 404.

A microprogram that determines the operation of the execution unit 401 is stored in the control memory 403. The order control unit 402 reads the microprogram from the control memory 403 via the data line 423.

The operation of the execution unit 401 is controlled via a control line 422 .

The order control unit 402 includes a control register 411 and a status register 412 . Process number register 41
There are 3. Control register 411 is APU
There is a 1 bit in the 0 register (hereinafter referred to as the start bit) that is used to control the operation of the '102.
When ' is written, the order control unit 402 requests the bus arbitration unit 103 to allocate mastership of the bus 110, and after acquiring the mastership, the execution unit 401 starts operating. The status register 412 is for indicating the execution state of the APU 102. FIG. 8 shows the bit configuration of the status register 412. Bit 801 becomes 1' when sequence control unit 411 accepts an interrupt request from interrupt line 112 (hereinafter referred to as 1').

bit 802 becomes 1' when the sequence control unit 411 receives a bus error signal from the signal line 116 (hereinafter referred to as bus error bit), bit 803 indicates that the APU 102 executes the microprogram. When the operation is stopped by an instruction, it becomes 1' (hereinafter referred to as the end bit).

A process number is written into the process number register 413 by cputot.

A register file 410 is provided within the execution unit 401 to store work data and the like.

The bus control unit 404 transfers data between the execution units 401 , 402 , and the order control unit 402 and the bus 110 via data lines 420 and 421 .

From CPLIIOI, register file 410 . Control register 411° Status register 412. Process number register 413
access.

Next, the operation of the hardware of this system will be explained.

First, startup control of the APU 102 will be described.

While CPUl0I is operating, the control register 411
When 1' is written to the start bit of APU102
requests the bus arbitration unit 103 to allocate mastership of the bus 110. Bus arbitration unit 103
gives a higher priority in assigning the master right to APU]02 than CPU10I, and immediately assigns the master right to ^PU102. As a result.

The CPU 10I becomes unable to fetch instructions and interrupts its operation, and the 8PU 102 starts its operation.

As described above, the APU 102 always operates while the CPU 10I suspends its operation. For this reason, APUt0
2 stops operating and relinquishes the mastership, the CPU
L0I acquires the master right and resumes operation.

Next, APt! The operation when an interrupt request is generated from the outside while 102 is operating will be described.

An interrupt request from the outside enters the CPUl0I through an interrupt line 111. During the operation of APU1, 02, the interrupt mask 120 is in a state where interrupt requests can be accepted, and CPU10I
immediately accepts the interrupt request and sends the interrupt request to interrupt line 1.
12 to the APU 102.

When the APU 102 receives an interrupt request from the interrupt line 112 during operation, it sets the interrupt bit 801 of the status register 412.
is set to '1', the bus 110 is released, and the operation is stopped.

Along with this, CPUl0I resumes the suspended operation and performs interrupt exception processing. If the interrupt request is a timer interrupt, process switching processing is subsequently performed under the control of the OS. If the interrupt request is a signal interrupt, then an interrupt handler processing program is started under the control of the OS.

Next, the operation when a page fault occurs in the main memory 105 during the operation of the APU 102 will be described.

When a page fault occurs in the main memory 105, the memory management unit 104 sends a bus error signal to the bus arbitration unit 103 via the signal line 114. When the bus arbitration unit 103 receives a bus error signal from the signal line 114, it sends the bus error signal to the side of the CPU 10I and the APU 102 that holds the mastership of the bus 110 via the signal line 115 or 116.

In this case, since the APU 102 holds mastership of the bus 110, the bus error signal is sent to the APU 102. When the APU 102 receives a bus error signal from the signal line 116, it sets the bus error bit 802 of the status register 412 to '1' and stops operating.

Next, CPU10I resumes operation and performs page swap processing between main memory 105 and auxiliary memory 107 under the control of O5. In this case, auxiliary memory 107 is accessed via input/output control unit 106.

The above is the operation of the hardware of this system.

Next, the software configuration of this system will be described.

FIG. 3(1) is a diagram showing the configuration of areas within the main memory 105. The area within the main memory 105 is divided into an application layer 301 r os kernel layer 302 and an OS driver layer 303 .

The configuration of the application layer 301 is shown in FIG. 3 (2). The main program 311 is executed by cputot, converts a logical language source program into an intermediate language program, and outputs it to the main memory 105.
Perform processing such as moving 2 to 0. Built-in predicate A312 is C
Among the built-in predicates executed by PUl0I, these are called from the main program 311. Interrupt handler A313 is one of the interrupt handlers provided in this system.
This is executed by CPUl0I. The intermediate language program 314 is created by the main program 311 by converting the source program. AP
It is subject to processing by the interpreter on U102. The internal state save area 315 is an area where data representing the execution state of the APU 102 is saved. request area
.

316 is the application layer 301 of the driver layer 303
This is the area where processing requests for the program are written.

The configuration of the O5 kernel layer 302 is shown in FIG. 3 (3).

The input/output management program 321 is the driver program 33
1 start-up processing 9 Start-up processing of the interrupt handler A313, etc. are performed. Interrupt exception handling program 322. The process switching program 323 includes interrupt exception handling,
It performs process switching processing. The page management program 324 performs page swap processing between the main memory 105 and the auxiliary memory 107. A signal area 325 is an area in which the type of signal is registered by the 1-interrupt exception handling program 322 when a signal interrupt request occurs. 326 in the table is interrupt handler A
This table holds the types of signals that request processing of programs in 313 and the addresses of the corresponding programs. The process management table 327 is a table that holds the numbers of currently executing and waiting processes.

The configuration of the OS driver layer 303 is shown in FIG. 3 (4).
The driver program 331 performs startup processing of the APU 102, etc., and is executed by the CPU I0I. The built-in predicate D332 is called from the driver program 331 among the built-in predicates executed by cputot.

FIG. 6 is a diagram showing the configuration of the microprogram in the control memory 403 in the APU 102.

The interpreter 601 interprets and executes the intermediate language program 314 in the main memory 105.

The built-in predicate M602 is executed by the APU 102 among the built-in predicates included in this system. Interrupt handler M603 is A among the interrupt handlers provided in this system.
This is executed by PUI02.

FIG. 5 is a diagram showing the configuration of the area of the register file 410 within the APU 102.

The signal area M501 is an area where, when a signal requesting processing by the interrupt handler M603 is generated, the type of the signal is 5th. Table M502 is a table that holds addresses of programs corresponding to types of signals requesting processing by interrupt handler M603.

The request area M503 is an area in which request processing for the CPU 10I of the APU 102 is written. The working area 504 is an area used for work when the interpreter 601 is operating.

Next, the processing flow of this system will be explained with reference to FIGS. 2 and 7.

The processing flow shown in FIGS. 2(a) and 2(b) is divided into the following four parts. The first step is steps 201 to 206, which are executed by the program in the application layer 301.
It represents the processing flow of Ul0I.

The second step is steps 211 to 213, which represent the CPU10I processing flow by the program in the kernel layer 302 of the OS, and the third step is steps 221 to 236, which represent the CPU processing flow by the program in the driver layer 303 of the OS. Represents the old processing flow. The fourth step is step 240.

It represents the processing by the microprogram in the control memory 403 of the APυ102.

First, the processing flow of CPUl0I by the program in the application layer 301 (steps 201 to 2)
06) will be explained.

Steps 201 to 205 are the processing flow of the main program 311. The contents are described below.

Step 201: After initializing this system, a logic language source program is input, an intermediate language program 314 is created, and the intermediate language program 314 is output to the main memory 105.

Step 202: Write a value representing the initial state of the APU 102 to the internal state save area 315 in the main memory 105.

Step 203: Issue an io command to call the input/output management program 321 of the kernel layer 302 of the OS (proceed to step 211).

Step 204: A request from the OS driver layer 303 is read from the request area A316, and if the request is a system termination request, the process ends; otherwise, the process proceeds to the next step.

Step 205: After executing the built-in predicate A312 in response to the request, the process returns to step 2.03.

The above is the processing flow of the main program 311.

Step 206 represents the processing of interrupt handler A313. Interrupt handler A313 is input/output management program 321
After the processing is completed, the main program 3
11 (proceed to step 204).

Next, a program in the kernel layer 302 of the OS
The processing flow of puloi (steps 211 to 214) will be explained.

First, the processing flow of the input/output management program 321 will be described.

Step 211: Interrupt mask 12 in CPUl0I
0 so that no interrupt request is accepted, and the driver program 331 is called (proceed to step 221).

Step 212 After finishing the Nidriver program 331,
Refer to 325 in the signal area, and if the signal is registered, use 326 in the table to find the address of the program in the corresponding interrupt handler A313.

Start the program (steps) (Proceed to step 206), otherwise.

Main program 311 helicopter (proceed to step 204).

In any of the above cases, at the end of step 212,
The interrupt mask 120 is set so that it can accept interrupt requests.

The above is the processing flow of the input/output management program 321.

Step 213 represents the processing of the interrupt exception handling program 322. The program 322 is activated when the CPU 10I receives an interrupt request from the interrupt line 111, and when the interrupt request is a signal interrupt request, the type of signal is registered in the signal area 325. After the processing is completed, the reception of the interrupt request resumes the processing of CPUl0I from the current state.

Next, the processing flow of CPU10I by the driver program 331 in the driver layer 303 of the OS (step 22
1 to 236) will be explained. Driver program 3
31 is the startup process of the APU 102 and the subsequent APU 10
Processing for requests from 2 and interrupt requests 1 is performed in the following steps.

Step 221: Read the current process number in the process management table 327 and the value of the process number register 413 in the APU 102. If they do not match, the contents of the internal state save area 315 in the main memory 105 are read out. Write to register file 410.

Step 222: Set the interrupt mask 120 so that it can accept an interrupt request, and set the start bit in the control register 411 in the APU 102 to '1'. As a result, the APU 102 enters the execution state (step 240).

Step 223: After the operation of the APU 102 is stopped, the 1-interrupt mask 120 is set so that it is impossible to accept an interrupt request, and if the interrupt pit 801 of the status register 412 is 11', the process proceeds to step 231, and a bus error is detected. If the pit 802 is 11', the process proceeds to step 235; if the end bit 803 is 51', the process proceeds to the next step. If none of the bits is a mama or mama, repeat this step.

Step 224 Read the request for CPUl0I of AP old 02 from the request area M503 in the second register file 410. If the request can be processed within the driver program 331, proceed to the next step. If it cannot be processed, proceed to step 229. .

Step 225: If the request is a process that allows process switching, proceed to step 227; if the request is a process that does not permit, proceed to the first step.

Step 226: Processing for the request (built-in predicate D33
2) and returns to step 222.

Step 227: Write the current process number in the process management table 327 to the process number register 413, and write the value representing the execution state of the APU 102 in the register file 410 to the internal state save area 315 in the main memory 105.

Step 228: Processing for the request within the request area 503 (execution of built-in predicate D332, etc.) is performed. During this time, the interrupt mask 120 is set to a state where it can accept interrupt requests. After processing, the process returns to step 221.

Step 229: Write the contents of request area M503 to request area A316.

Step 230: Write the current process number in the process management table 327 to the process number register 413, write the value representing the execution state of the APU 102 in the register file 410 to the internal state save area 315, and return to the input/output control program 321 (step (Proceed to 212).

Step 231: Refer to 325 in the signal area,
If the type of signal is not written (that is, the cause of one interrupt request is a timer interrupt), the process advances to step 233. If the type of signal has been written and is registered in the table 326 (that is, processing of the program in interrupt handler A 312 is requested), the process advances to step 230. In other cases (that is, processing of the program in the interrupt handler M603 by the APU 102 is requested), the process advances to the next step.

Step 232: Write the contents of signal area 325 to signal area M501 in register file 410, and return to step 222.

Step 233: Write the current process number in the process management table 327 to the process number register 413, and write the value representing the execution state of APU+02 in the register file 410 to the internal state save area 315.

Step 234: Call the process switching program 323 of the kernel layer 302 of the OS to perform process switching processing. After the program ends, the process returns to step 221.

Step 235: Write the current process number in the process management table 327 to the process number register 413, and write the value representing the execution state of the APU 102 in the register file 410 to the internal state save area 315.

Step 236: The page management program 324 of the OS kernel layer 302 is called to perform page swap processing between the main memory 105 and the auxiliary memory 107. After the program ends, the process returns to step 221.

The above is the processing flow of the driver program 331. In this process, the APU 10
When CPU10I becomes active, CPU10I suspends operation. After that, when the APU102's vno work is finished, the CPU1
0I resumes operation from step 223. However, the signal interrupt is from interrupt line 1.1.1, 112 to Cl301.
01 and APU102, so when a signal interrupt occurs, after the operation of APUt02 is completed, C1) υ101
executes the interrupt exception handling program 322 (step 213), and then proceeds to the process of step 223.

Next, the flow of the process (step 240) of the APU 102 will be explained with reference to FIG.

The APU 102 controls the start of the control register 411.
When 11' is written to the bit, the interpreter 601 enters the operating state and starts executing the interpreter 601.

The processing flow of the interprinter 601 is shown below.

Step 701: If the type of signal is written in the signal area 501, refer to table M502, find the address of the program in the corresponding interrupt handler M603, and call the program (proceed to step 705). ). Otherwise, proceed to the next step.

Step 702: Read the intermediate language in the intermediate language program 314. If the intermediate language is a processing request to CPUl0I (that is, a system termination request or a processing request for built-in predicate A312 and built-in predicate D332), step 704 , otherwise proceed to the first step.

Step 703: Interpret and execute the above intermediate word, Step 7
Return to 02.

Step 704: Writes a processing request to CPUl0I to request area M503 and stops operation.

In this case, the status register The end bit 803 of 411 is is set to

The above is the processing flow of the interpreter 601.

Step 705 represents processing of the program within the interrupt handler M603. The program is an interpreter 601
After the processing is completed, the process returns to the interpreter 601 (proceeds to step 702).

The above is the processing flow of the eight PUs 102.

Finally, we will supplement the processing when the APtJ 102 receives an interrupt request or a bus error signal during operation.

First, when an interrupt request is received from the interrupt line 112,
The APu 102 sets the interrupt bit 801 of the status register 411 to 1' and ends the operation.

Further, when receiving a bus error signal from the signal line 116, the APU 102 sets the bus error bit 802 of the status register 411 to 1' and ends the operation.

The above is the description of the first embodiment.

Next, examples of systems (Example 2 to Example 8) that are partially modified from the system of Example 1 will be shown.

The second embodiment is a system in which the processing performed in the driver layer 303 in the first embodiment is executed in the application layer 301 in a privileged mode.

In the first embodiment, the io command is issued in step 203 of the main program 311 of the application layer 301 to transfer control to the driver program, whereas in the 1-hydro type, in the same step, the as command is used to shift to the privileged mode. After that, the control program for the APU 102 is called.

This control program performs the same processing as the driver program 311 (steps 221 to 236) of the driver layer 303 and the built-in predicate D332.

Furthermore, when the APu 102 ends its operation after accepting an interrupt request, the main processor 101 does not perform process switching processing in the interrupt exception handling program 322 in the kernel layer 302, and instead
Let us proceed to step 223).

The third embodiment is a system in which the processing performed in the privileged mode in the second embodiment is performed in the normal application layer execution mode.

This method can be used when the registers in the APU 102 are placed in a user address space or when the memory space is not protected.

The fourth embodiment is a system in which the processing in the driver layer 303 in the first embodiment is performed in the kernel layer 302. That is, in this method, the kernel layer 302 of the OS includes the driver program 331 and the built-in predicate D332.
change the program.

In the fifth embodiment, the process number register 4 in the first embodiment is
In this system, the process number is stored in the kernel M302 of the OS, with the exception of storing the process number in the OS kernel M302.

Embodiment 6 differs from Embodiment 1 in that the current process number is stored in the process number register 413 in step 227 after the operation of the APU 102 or in steps 230, 233 and 235, and the processing is performed before the APU 102 is started. This is a system in which the process is performed within step 221 of the process.

The seventh embodiment differs from the first embodiment in that the APU 102 is used by multiple processes.

APU10 is a system that limits the process using APU102 to a single process.
A mechanism is provided for prohibiting other processes from using the APU 102 while a certain process is using the APU 102.

On the other hand, it is not necessary to save the value representing the execution state of the eight PUs 102 to the main memory and to recover it from the main memory when the process is switched. That is, the driver program 33
Step 221 in 1, and 227, 230, 2
33,235 is omitted. Furthermore, the internal state save area 315 on the main memory 105 and the process number register 413 in the APU 102 are also omitted.

In the eighth embodiment, in the system of the seventh embodiment, the APU 10
This is a system that prohibits process switching during the operation of 2. In this method, step 234 (calling process of the process switching program 323) in the driver program 331 is omitted compared to the case of the seventh embodiment.

〔Effect of the invention〕

According to the present invention, when a dedicated processor for AI language is added to a computer system, changes in the program on the main processor side are localized. As a result, it becomes easy to add the dedicated processor, and it becomes possible to make it optional whether or not to add the dedicated processor.

Also, interrupt processing that occurs during AI language processing.

Since a part of the input/output processing etc. can be processed on the main processor side, the structure of the dedicated processor can be simplified.

In addition, when multi-process operation cannot be performed using the virtual memory method, when switching processes, register values of the dedicated processor can be transferred to the application program area (
In other words, it becomes possible to save the data into the virtual address area (virtual address area), which has the effect of reducing the amount of main memory used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the hardware configuration of a computer system according to an embodiment (Embodiment 1) of the present invention, and FIG.
), (b) are flow diagrams showing the operation of CPUl0I, FIG. 3 is a diagram showing the configuration of the area of the main memory 105, and FIG.
The figure is a block diagram showing the hardware configuration of the additional processor unit 102, and FIG.
FIG. 6 is a diagram showing the configuration of the area of the control memory 403.
7 is a flowchart showing the operation of the execution unit 401, and FIG. 8 is a diagram showing the structure of the bits in the status register 412.

Claims (1)

[Scope of Claims] 1. Consists of a main processor unit, an additional processor unit, a bus control unit, a memory management unit, and a memory that are connected via a bus, and the additional processor unit executes a built-in microprogram to In a computer system that processes a program in an AI language, the priority of bus mastership assignment of the additional processor is set higher than that of the main processor, and in response to requests for bus mastership assignment from each processor, Bus mastership is assigned to each processor based on the priority, and when the additional processor relinquishes bus mastership and stops operating, the main processor, which has lost bus mastership and is suspending execution, A method for controlling an additional processor unit, characterized in that the operation is restarted from the interrupted point. 2. The memory management unit receives a memory access request by specifying a logical address, and if the real memory is allocated to the specified address, accesses the memory; if not, sends a bus error signal to the specified address. A patent claim characterized in that the bus error signal is output to a bus control unit, and in the bus control unit, the bus error signal input from the memory management unit is output to the side that holds bus mastership among the main processor and the additional processor. A method for controlling an additional processor unit according to item 1. 3. The method of controlling an additional processor unit according to claim 2, wherein when the additional processor receives a bus error signal from the memory management unit, the additional processor relinquishes bus mastership and stops operation. 4. Directly input a common interrupt request to the main processor and the additional processor, or indirectly input the interrupt request common to the main processor to the additional processor via the main processor, and 2. The method of controlling an additional processor unit according to claim 1, wherein when the interrupt request is input in the additional processor, the bus mastership is relinquished and the operation is stopped. 5. If the main processor executes a multi-process operation and the attached processor stops operating, write the identifier of the current process in the main memory or a register in the attached processor unit, and check the execution state of the attached processor. When the attached processor is restarted, the process identifier written in the main memory or the register in the attached processor unit and the current The additional processor unit according to claim 1, wherein the additional processor unit compares the process identifier with the process identifier, and restores the values of the registers saved in the main memory only if they do not match. Control method. 6. In the main processor, under the control of the operating system (OS), execute the application layer program, move from the application layer to a privileged mode, start the additional processor, and as the additional processor starts, the bus mastership is granted. If execution is suspended due to transfer to an attached processor, and the attached processor relinquishes bus mastership and terminates its operation, it will acquire bus mastership again and resume execution in privileged mode from the point where it was interrupted. 2. A method for controlling an additional processor unit according to claim 1. 7. In the main processor, the application layer program is executed under the control of the operating system (OS) consisting of the kernel layer and the driver layer, and the driver layer is started through the execution of the kernel layer program from the application layer. When an additional processor is activated during execution of a layer, and the execution is suspended because the bus mastership is transferred to the additional processor as the additional processor is activated, the additional processor relinquishes the bus mastership and operates. 2. The method of controlling an additional processor unit according to claim 1, further comprising acquiring bus mastership again and restarting execution of the driver layer from the interrupted point. 8. In the kernel layer of the main processor, set the value of the mask register so that interrupt requests to the main processor are masked while the kernel layer and driver layer are operating, and in the driver layer, when starting the additional processor. , change the value of the mask register so that the interrupt request is unmasked, and when the attached processor stops operating, change the value of the mask register so that the interrupt request is masked. 8. A method for controlling an additional processor unit according to claim 7. 9. When the kernel layer of the main processor executes a multi-process operation, and the additional processor requests processing to the main processor and stops its operation, and the additional processor stops operating in the main processor. , the following operations (a) to (d) are performed depending on the type of request processing of the additional processor to the main processor: (a) After the request processing is performed in the driver layer, the operation of the additional processor is stopped; (b) Saving the values of registers that hold the operating state of the additional processor in the driver layer to main memory, and restoring the values of the registers after performing the request processing; (c) In the driver layer, save the values of registers that hold the operating state of the attached processor in the main memory, and in the kernel layer, issue a process switch and restart the operation of the attached processor from the point where it stopped. After restarting the process, the driver layer restores the values of the registers and restarts the operation of the attached processor from the point where it was stopped. (d) The driver layer restores the values of the registers that maintain the operating state of the attached processor After saving in memory and processing the request in the application layer, the values of the registers are restored in the driver layer, and the operation of the additional processor is resumed from the point where it was stopped. A method for controlling an additional processor unit according to claim 7. 10. The main processor performs interrupt handler processing for interrupt requests that are commonly input to the main processor and additional processors in the application layer, and if the additional processor stops operating after inputting the interrupt request, the kernel The layer sets a signal to remember that the interrupt request has occurred, and then resumes the operation of the driver layer from the point where it was interrupted.If the signal is set, the driver layer returns to the kernel layer, and the kernel 9. The method of controlling an additional processor unit according to claim 4, wherein the interrupt handler processing of the application layer is activated in the application layer. 11. If the additional processor performs interrupt handler processing for an interrupt request that is commonly input to the main processor and the additional processor, and the main processor inputs the interrupt request and the additional processor stops operating, At the kernel layer,
After setting a signal to remember that the interrupt request has occurred, restart the operation of the driver layer from the point where it was interrupted, and in the driver layer, if the signal is set, execute the interrupt handler processing. 9. The method of controlling an additional processor unit according to claim 4, further comprising activating the additional processor.