JPH01214168A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the reliability of semiconductor devices such as a MOS- FET and the like and facilities the favorable manufacture of them, by surrounding upper, side, and base faces of a principal conductor layer containing metals with a hydrofluoric-acid-resistant protective film and a polycrystal silicon layer. CONSTITUTION:The upper and side faces of a titanium silicide layer 106 containing metals which act as a gate electrode of a MOS-FET are surrounded with silicon nitride layers 107 and 108 of a hydrofluoric acid resistant protecting film and a polycrystal silicon layer 105 is provided below the layers 106 and 108. This configuration brings the layer 106 into direct contact with a layer insulation film 109 and further, the metals such as titanium and the like from going outside the gate electrode. This approach improve the reliability of a MOS-FET and makes it possible to use an etchant containing hydrofluoric acid and a favorable MOS-FET is thus manufactured easily.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to an MO3 field effect transistor that uses a high melting point metal, metal silicide, etc. for the gate electrode to improve reliability. and its manufacturing method.

[Conventional technology]

The conventional MO8 field effect transistor has a polycrystalline silicon film 404 and a titanium silicide film 405, as shown in FIG.
An electrode with a layered structure (titanium polycide electrode) was used for the gate electrode. In FIG. 4, a semiconductor substrate 401
MO8 is placed in the element region surrounded by the element isolation film 402 on the surface.
It forms a field effect transistor. The gate electrode is
It has a laminated structure of a titanium silicide layer 405 and a polycrystalline silicon layer 404 doped with impurities.

Further, the source/drain regions 408, 408' are connected to source/drain electrodes 407, 407' via contact holes provided in the interlayer insulating film 406.

Next, FIGS. 5(a) to 5(d) show a method of manufacturing the titanium polycide gate transistor shown in FIG. 4. As shown in FIG. 5(a), first, an element isolation film 502 is formed on the surface of a silicon substrate 501, and after exposing the substrate surface in the element region surrounded by the element isolation film 502, a gate oxide film 502 is formed.
Form 03. Thereafter, a polycrystalline silicon film 504 into which impurities are introduced and a titanium silicide film 505 are formed. Next, as shown in FIG. 5(b), after forming a resist pattern 508 by photolithography or the like, the titanium silicide film 505 and the polycrystalline silicon film 504 are etched by a method such as reactive ion etching. A gate electrode consisting of layer 507 and polycrystalline silicon layer 506 is formed. Subsequently, as shown in FIG. 5(C), after removing the resist pattern 508, source/drain regions 509 are formed by ion implantation.
, 509'. Further, as shown in FIG. 5(d), after depositing an interlayer insulating film 510, contact holes are formed in the interlayer insulating film 510 to provide direct contact with the source/drain regions, and source/drain electrodes 511, 51
1' is formed.

[Problem to be solved by the invention]

The conventional MO8 type field effect transistor described above has a fourth
The titanium silicide layer 405 in the figure is directly connected to the interlayer insulating film 405.
6, titanium in the titanium silicide diffuses within the interlayer insulating film 406 and reaches the source/drain regions 408, 408', increasing junction leakage current or causing the source/drain electrodes 408, 408 to ', leading to insulation failure and other instability in transistor characteristics.

In addition, in a normal polycrystalline silicon gate transistor,
After forming the gate electrode by dry etching and etching, the source/
The gate oxide film on the drain region is removed using hydrofluoric acid, and then an oxide film is formed using a thermal oxidation method to serve as a protective film during ion implantation. However, since titanium silicide easily dissolves in hydrofluoric acid, fluorine was not used. The gate oxide film on the source/drain regions cannot be removed using the conventional method. Therefore, the source/drain regions 509 and 50 in FIG. 5(c)
9' is formed by ion implantation, the portion of the gate oxide film 503 above the source/drain region, which served as a stopper film for dry etching to form the gate electrode, is used as it is as a protective film during ion implantation. . For this reason, organic substances attached to the surface of the oxide film during dry etching and heavy metals mixed into the oxide film are implanted into the silicon substrate during ion implantation, resulting in a leakage current at the Pn junction between the source/drain region and the substrate. This has been a cause of deterioration of transistor characteristics, such as an increase in the amount of carbon dioxide and poor insulation between the gate electrode and the source/drain regions.

As described above, the conventional titanium silicide gate MO
The 8-type transistor has a drawback in that it does not have a structure that can prevent the phenomenon that titanium is lost from the titanium silicide layer.

[Means to solve the problem]

The semiconductor device of the present invention includes a main conductor layer containing a metal, a protective layer having hydrofluoric acid resistance formed so as to surround the upper surface and side surfaces of the conductor layer, and the entire lower surface of the conductor layer and the protective layer. It has a polycrystalline silicon layer disposed to cover it.

As this main conductor layer, a refractory metal, a refractory metal silicide, a refractory metal nitride, or an alloy thereof is used.

According to the present invention, the upper surface and side surfaces of the main conductor layer containing metal such as titanium silicide are covered with a protective film having hydrofluoric acid resistance such as silicon nitride, and the lower surface is covered with polycrystalline silicon. The metal does not diffuse outside the gate electrode, and the silicon oxide film on the surface of the source/drain region can be removed using an etching solution containing hydrofluoric acid.

The manufacturing method of the present invention also includes a step of forming a polycrystalline silicon layer, a main conductor layer containing metal, and a first protective layer having hydrofluoric acid resistance on the gate oxide film in this order. , a process of etching only the protective layer and the main conductor layer to form a wiring pattern, a process of forming a hydrofluoric acid-resistant second protective film, and an anisotropic etching to form the second protective film. A step of leaving only the side surface of the conductor film and removing other parts, and further removing the main conductor layer which has become like a wiring and the second conductor layer.
The method includes a step of etching the polycrystalline silicon layer using the protective layer as a mask to form a gate electrode.

According to the present invention, since the width of the polycrystalline silicon layer on the lower surface of the main conductor layer becomes the width of the gate electrode, it is possible to prevent offset between the gate electrode and the source/drain electrode.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a first embodiment of the invention. In this embodiment, an element isolation film 102 on a silicon substrate 101,
This is an MO8 type field effect transistor formed within the element region surrounded by 102'.

The gate electrode of the MO8 type field effect transistor of this example has silicon nitride layers 107 and 108 on the top and side surfaces, respectively, so as to surround the titanium silicide layer 106, which is the main conductor layer, and the bottom surface is made of titanium silicide. Silicide layer 1
It has an impurity-doped polycrystalline silicon layer 105 that is wider than 06. Moreover, the silicon oxide film layer 112,
112' electrically insulates the gate electrode and the source/drain regions 104 and 104'. Source/drain electrodes 110 and 111 are connected to source/drain regions 104 and 1 through contact holes provided in interlayer insulating film 109.
04'.

According to the present invention, since the titanium silicide layer, which is the main conductor layer, is surrounded by the silicon nitride film that has barrier properties against impurity diffusion, titanium diffusion is suppressed and transistor characteristics are stabilized. Ru. Further, since the silicon nitride film has hydrofluoric acid resistance, the silicon oxide film on the source/drain region can be removed using hydrofluoric acid. Furthermore, the polycrystalline silicon layer 105 on the lower surface of the titanium silicide layer 106
Since the width is wider than the width of the silicon nitride layer 108 and extends to the vicinity of the outer edge of the silicon nitride layer 108, a so-called offset in which a non-inverted region occurs between the source/drain region and the channel region does not occur, so that good transistor characteristics can be obtained.

FIGS. 2(a) and 2(b) show an example of a method for manufacturing the MO8 field effect transistor shown in FIG. First, Figure 2 (a)
As shown in FIG. 2, an element isolation film 202 is formed on the surface of a silicon substrate 201, and gate silicon acid (tJ203) is formed in the element region by thermal oxidation. Thereafter, a polycrystalline silicon film 204 into which impurities have been introduced is formed. .A titanium silicide film 205 and a silicon nitride film 206 are formed.Next, as shown in FIG. 2(b), a resist pattern is formed using a photolithography method, and reactive ion etching (RIE) is performed. The silicon nitride film 206 is then etched to form a silicon nitride layer 208.Next, the polycrystalline silicon film 204 is etched using a process for titanium silicide, a process for which the etching rate is higher than that for polycrystalline silicon, and RIE. , the titanium silicide film 205 is etched to form a titanium silicide layer 207. Next, as shown in FIG.
Form 09. Next, as shown in FIG. 2(d), RI
The silicon nitride film 209 is etched back using E to form sidewall nitride film layers 210 and 210', and then the polycrystalline silicon film 204 is also etched to form the polycrystalline silicon layer 21.
form 1. Next, as shown in FIG. 2(e), the gate silicon oxide film on the source/drain region is removed using hydrofluoric acid, and the silicon oxide film 213, 213', which serves as a protective film during ion implantation, is thermally oxidized. After forming the source/drain regions 214, 214' by ion implantation,
form.

What is particularly noteworthy about this manufacturing method is that when etching the titanium silicide film 205, the polycrystalline silicon film 204 is etched, leaving the polycrystalline silicon film 204 intact. It can be extended to below the silicon nitride film 210, and offset can be prevented from occurring. When etching is performed without leaving the polycrystalline silicon layer 204, the gate oxide film 203 on the surface of the source/drain region is removed from the polycrystalline silicon layer 204.
Since the silicon nitride film 209, which becomes the sidewall protection layer, is exposed to etching twice, if over-etching is performed, the gate oxide film 203 will be removed and the source/drain region 209 will be etched twice.
14, 214' may be etched, but in the case of the present invention, the gate oxide film layer 203 on the surface of the source/drain region is etched only when the polycrystalline silicon layer 204 is etched. This has the effect of preventing the above-mentioned problems.

FIG. 3 is a longitudinal sectional view of a second embodiment of the invention. In this embodiment, an element isolation film 302 on a silicon substrate 301,
This is an MO3 field effect transistor formed within the element region surrounded by 302'.

The gate electrode of the MO3 type field effect transistor of this example has polycrystalline silicon layers 306 on the top, side and bottom surfaces so as to surround the titanium silicide layer 306 which is the main conductor layer.
07, 308 and 305. In addition, the silicon oxide film layer 312 has a gate electrode and a source/drain region 3.
04 and 304' are electrically insulated. Electrodes 310 and 311 connected to the source/drain are connected to source/drain regions 304 and 304' via contact holes provided in the interlayer insulating film 309.

According to the present invention, the titanium silicide layer 3 which is the main electrode layer
06 is surrounded by the polycrystalline silicon films 305 and 306°3Q7, diffusion of titanium is suppressed and transistor characteristics are stabilized. Furthermore, since the polycrystalline silicon film is resistant to hydrofluoric acid, the silicon oxide film on the source/drain regions can be removed using hydrofluoric acid. Furthermore, since the polycrystalline silicon layer 305 under the titanium silicide layer 306 is wider than the width of the titanium silicide layer 306, so-called offset does not occur between the source/drain regions 304, 304' and the channel region, resulting in good transistor characteristics. can get.

〔Effect of the invention〕

As explained above, the present invention provides a structure in which a gate electrode or a wiring is formed by a main conductor layer containing a metal, and a hydrofluoric acid-resistant material formed so as to surround the upper surface and side surfaces of the main conductor layer. By including a protective layer and a polycrystalline silicon layer formed to cover the entire lower surface of the main conductor layer and the protective film, the upper and side surfaces of the main conductor layer containing metal such as titanium silicide can be protected. is covered with a hydrofluoric acid-resistant protective film such as silicon nitride, and the lower surface is covered with polycrystalline silicon, so metals such as titanium do not come out of the gate electrode, and an etching solution containing hydrofluoric acid is used. This has the effect that the gate silicon oxide film on the surface of the source/drain region can be removed.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;
2(a) to 2(e) are cross-sectional views showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of main steps, and FIG. 3 is a cross-sectional view showing the semiconductor device according to the second embodiment of the present invention. 4 is a sectional view of a conventional semiconductor device, and FIGS. 5(a) to 5(d) are sectional views showing a conventional method of manufacturing a semiconductor device. 101... Semiconductor substrate, 102... Element isolation, 103... Gate oxide film, 104...
...Source/drain region, 105... Polycrystalline silicon layer, 106... Titanium silicide layer, 107... Silicon nitride layer, 108...
... silicon nitride layer, 109 ... interlayer insulating film, 110, 111 ... source/drain electrode,
112, 112'... Silicon oxide film layer, 20
1...Silicon substrate, 202...Element isolation, 203...Gate oxide film, 204...
...Polycrystalline silicon L205...Titanium silicide film, 206...Silicon nitride film, 207
...Titanium silicide layer, 208...
silicon nitride layer, 209...silicon nitride film,
210, 210'... Sidewall silicon nitride layer, 2
11... Polycrystalline silicon layer, 212...
- Gate silicon oxide film, 213...Silicon oxide film, 214.214'...Source/drain region, 301...Semiconductor substrate, 302...
...Element isolation, 303...Gate oxide film,
304, 304'...source/drain region,
305... Polycrystalline silicon layer, 306...
...Titanium silicide layer, 307...Polycrystalline silicon layer, 308...Polycrystalline silicon layer, 30
9... Interlayer insulating film, 310, 311...
・Source/drain electrode, 312, 312'...
・Silicon oxide layer, 401...Semiconductor substrate, 4
02゜402'...Element isolation, 403...
... Gate oxide film, 404 ... Polycrystalline silicon layer, 405 ... Titanium silicide layer, 406 ...
...Interlayer insulating film, 407°407'...
Source/drain electrode, 408, 408'...
Source/drain region, 501...Silicon substrate, 502...Element isolation, 503...
Gate oxide film, 504...polycrystalline silicon film,
505...Titanium silicide film, 506...
... Polycrystalline silicon layer, 507 ... Titanium silicide layer, 508 ... Photoresist, 50
9,509'...source/drain region, 51
0... Interlayer insulating film, 511... Source/drain electrode. Agent Patent Attorney Hara Uchi

Claims (2)

[Claims] (1) The structure of the electrode portion of the MOS device includes a first conductor layer, a hydrochloric acid-resistant protective film formed to surround the top and side surfaces of the first conductor layer, and the first conductor layer. and a polycrystalline silicon layer formed on the lower surface of a protective film provided on the lower surface of the conductor and the side surface portion of the first conductor layer. (2) A step of forming a polycrystalline silicon layer, a main conductor layer containing metal, and a first protective layer resistant to hydrofluoric acid on the gate silicon oxide film, and only the protective layer and the conductor layer. A process of etching and processing it into a wiring pattern, a process of forming a second protective film that is resistant to hydrofluoric acid, and an anisotropic etching process, leaving the second protective film only on the side surface of the conductive film and removing the other parts. a step of removing a portion of the polycrystalline silicon layer, and a step of etching the polycrystalline silicon layer while masking the conductor layer shaped like a wiring and the second protective layer to form a gate electrode; and a step of etching the polycrystalline silicon layer with an etching solution containing hydrofluoric acid. A method for manufacturing a semiconductor device, comprising: removing a portion of the gate silicon oxide film not covered by the gate electrode to expose the substrate.