JPH01211397A - Refresh device for storage device - Google Patents

Abstract

PURPOSE:To shorten busy time caused by the refresh of a storage device whose mounting capacity is little by setting only a specified block among plural blocks to be a mounting state and changing time required for refreshing without executing the refresh for the block which is not set to be the mounting state. CONSTITUTION:A mounting capacity setting switch 51 sets only the specified block among the plural blocks of the random access storage device to be the mounting state and controls a refresh cycle changing circuit 53 not to give refresh timing signals 62-65 for the block which is not set to be the mounting state by the switch 51. Thus, the busy time caused by the refresh of the storage device whose mounting capacity is little can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage device, and more particularly to a refresh device for a storage device that makes refresh cycle time variable.

[Conventional technology]

Among the memories that are the main components of micro combi coaters, static random access memory (hereinafter referred to as SRAM) and dynamic random access memory (hereinafter referred to as DRΔM) occupy a very high proportion. SRAM is characterized by ease of use and low power consumption, and DRΔM is characterized by low cost. S.R.
Since AM uses bistable flip-flops as storage cells, it can continue to retain stored information as long as power is supplied. On the other hand, D
RAM requires refresh control, which makes its handling more troublesome, and various countermeasures for refresh are being considered.

This refresh control can be briefly explained as follows. Taking as an example an element-type cell composed of one transistor and one capacitor cell, stored data is held by this capacitor.

When storing data, this capacitor is in either the "H" state, where a small amount of electrons are stored, or the "L" state, where a large amount of electrons are stored.
condition must be maintained. However, since the "H" state is in a thermally non-equilibrium state, as time passes (the number I
Qms~several S) Transition to the "L" state, which is a state of thermal equilibrium. Therefore, it is necessary to periodically restore the information in the memory cells to the correct level, and this is called refresh.

Conventionally, such a refresh operation could be performed on all memory chips on -substrates because the number of memory chips mounted on -substrates was small. However, recently, mounting technology has improved, and the number of memory chips mounted on one board has increased. For this reason, the supply of peak current when performing refresh has become a problem. To solve this, R
A method is known in which the peak current is reduced by dividing the AM section into a plurality of blocks and performing refresh at different times for each block. Further, as mounting technology has improved, the mounting capacity per board has increased, but in some cases it is possible to change the mounting capacity per board in order to reduce the unit of expansion. In any case, in such conventional storage devices, refreshing was performed regardless of the installed capacity.

[Problem to be solved by the invention]

As described above, the conventional refresh method has the drawback that refresh time is consumed even for blocks in the RAM section that are not mounted, resulting in wasted refresh cycle time.

SUMMARY OF THE INVENTION An object of the present invention is to provide a refresh device for a storage device that can change the time required for a refresh operation in accordance with the installed capacity of the memory, thereby shortening the busy time.

[Means to solve the problem]

The refresh device for a storage device according to the present invention has an address register that once sets a manually entered address and outputs it to a random access storage device divided into a plurality of blocks, and an address register that once sets the data input at the time of writing. A data transfer circuit that sends data to a random access storage device and once sets and outputs read data from the random access storage device at the time of reading, and a refresher.

A refresh control unit that generates a timing signal and executes refreshing at different times for each of the plurality of blocks of the random access memory described above, and a refresh control unit that implements only a specific block for the plurality of blocks of the random access memory device described above. A mounting capacity setting switch is set to the mounted state, and the mounting capacity setting switch is used to control not to send a refresh timing signal to blocks that are not set to the mounted state. The refresh cycle changing circuit reduces the effective refresh time depending on the state.

Therefore, when the storage device refresh device according to the present invention is used, the installed capacity setting switch sets only a specific block among the plurality of blocks of the random access storage device to the installed state, and the installed capacity setting switch sets only a specific block to the installed state. By controlling the refresh cycle change circuit so as not to apply a refresh timing signal to blocks that have not been set, it is possible to shorten the busy time due to refresh of a memory device with a small mounting capacity.

〔Example〕

The present invention will be described in detail with reference to Examples below.

FIG. 1 is a block diagram showing the refresh device of the storage device of this embodiment, and FIGS. 2 and 3 are timing diagrams of the refresh operation when the RAM section is fully mounted, and when the RAM section is partially mounted. FIG. 6 is a similar timing diagram when implemented.

In FIG. 1, address register 11 has input terminal 1
The received manual address 13 is once set in 2, and this input address 13 is sent to each of blocks 15 to 18 of A to D of the RAM section 14.

Similarly, the data transfer circuit 20 receives manual data 2 at the input/output terminal 21 when writing to the RAM block 14.
2 is set once, and this manual data 22 is sent to each of blocks 15 to 18 of A to D of RAM block I4. Also, when reading from the RAM section 14, A-D
Read data 23 from blocks 15 to 18 is set once and output to input/output terminal 21. Request reception circuit 2
5 accepts and controls the request signal 27 received at the input terminal 26 by receiving a control signal 29 from the busy management circuit 28 . Then, when the receiver is attached, it is sent to the control section 30.

The control unit 30 uses the request signal 27 from the request reception circuit 25 and the command input signal 32 input to the input terminal 31 to control the address register 11, data transfer circuit 20, busy management circuit 28, and A to D, respectively.
Control signals 38-41 are sent to block timing signal generation circuits 33-36. Then, writing or reading is executed and controlled according to the command human input signal 32. The refresh control block 43 generates a refresh timing signal 44 using a built-in oscillator, and controls refresh execution using a control signal 45 from the busy management circuit 28. This refresh control block 43
A-D receives the refresh timing signal 44 from
The block timing signal generation circuits 33 to 36 refresh the RAM section 14 for each block from A to D. The mounting capacity setting switch 51 is connected to the RAM section 1.
This is for setting only a specific block among the A-D blocks 15 to 18 of No. 4 to the mounted state. When the refresh cycle change circuit 53 receives the mounted capacity setting information 55 from the mounted capacity setting switch 51, the refresh cycle change circuit 53 changes the refresh cycle to the one corresponding to a specific block among the A-D block timing signal generation circuits 33 to 36. Corresponding signals of change signals 57-60 are sent out.

As a result, the refresh timing signal 6 from the block timing signal generation circuit corresponding to this specific block is
Any one of 2 to 65 will be suppressed, and the corresponding block will not be refreshed. Further, upon receiving the mounted capacity setting information 55, the refresh cycle change circuit 53 sends a control signal 67 to the busy management circuit 28 to shorten the busy time due to refresh in accordance with the mounted capacity setting information 55. control.

Next, according to FIGS. 2 and 3, RAM1417)A
- The refresh operation will be explained for the case where all of the D blocks 15 to 18 are implemented and the case where some of them are implemented.

First, when all of the A-D blocks 15 to 18 of the RAM section 14 are installed, the situation is as follows.

Mounting capacity setting information 55 is sent from the mounting capacity setting switch 51 to the refresh cycle changing circuit 53, indicating that the mounting of all blocks has been set. The refresh cycle change circuit 53 is all implemented in the A to D block timing signal generation circuits 33 to 36, and sends out refresh cycle change signals 57 to 60 indicating that there is no change in the refresh cycle. Furthermore, the busy management circuit 28
A control signal 67 to the same effect is also sent to the terminal. According to the above, the A-D block timing signal generation circuits 33-36 send refresh timing signals 62-65 to the A-D blocks 15-18 of the RAM section 14, and 15 to I8 are sequentially refreshed. Refresh times 71-74 for AD blocks 15-18 are as shown in FIG. In this case, the total refresh time busy time 75 corresponding to the total refresh time is as shown in the figure.

Also shown is a refresh cycle 76 indicating the repetition time of the refresh operation. During the overall refresh busy time 75 as described above, no requests from the processor or the like are accepted.

When the above refresh cycle 76 is completed, the next refresh is performed on the A-D blocks 15 to 18 in the same way, and in that case, the Δ to D block refresh time 7
8 to 81, and overall refresh busy time 82
becomes as shown.

Next, some of the A-D blocks 15 to 18, for example A, B
A case in which blocks 78 and 79 are implemented will now be described. In this case, the refresh operation for C and D blocks 80 and 81 becomes unnecessary.

Therefore, the mounted capacity setting switch 51 is set to a state in which only the ASB blocks 15 and 16 are mounted, and mounted capacity setting information 55 indicating this is sent to the refresh cycle change circuit 53. Upon receiving this, the refresh cycle change circuit 53 sends a refresh cycle change signal 59.60 indicating this to the C and D block timing signal generation circuits 35.36, and refresh timing signal 6 for the CSD block 17.18.
4.65 will be prevented from occurring. Furthermore, busy management circuit 2
8, a control signal 67 indicating the same effect is sent to
Control is performed to shorten the busy time depending on the implementation status. In this way, Δ,B blocks 15.16 are refreshed.

Δ, B block refresh time 91 and 92, half-mounted busy time 93, and refresh period 94 are as shown in the figure. Further, the A and B block refresh times 95 and 96 and the half-mounted busy time 97 in the next cycle are also as shown in the figure.

As is clear from Figures 2 and 3, the busy time decreases when comparing the case where all A to D blocks 15 to 18 are implemented and the case where only ASB block 15.16 is implemented. ing.

The refresh cycles 76 and 94 are the same for both and do not depend on the installed capacity.

〔Effect of the invention〕

As described above, the refresh device for a storage device according to the present invention sets only a specific block among a plurality of blocks in the RAM section to the mounted state, and does not refresh the blocks that are not set. By changing the required time, it is possible to shorten the busy time due to refresh of a storage device with a small installed capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a refresh device for a storage device according to the present invention, FIG. 2 is a diagram showing the timing of refresh operation when all blocks of the RAM section are mounted, and FIG. FIG. 6 is a diagram showing timing in the case of half-mounting. 11...Address register, 14...RAM section, 15-18...A-D block, 20...
...Data transfer circuit, 43...Refresh control section, 51...
- Mounted capacity setting switch, 53...Refresh cycle change circuit. Applicant NEC Corporation Agent
Patent attorney Umeo Yamauchi 2nd and 3rd country

Claims (1)

[Claims] An address register that once sets the input address and outputs it to the random access storage device divided into a plurality of blocks, and an address register that once sets the input data when writing and sends it to the random access storage device, and when reading a data transfer circuit that once sets and outputs read data from the random access storage device; a refresh control unit that generates a refresh timing signal and executes refreshing by shifting time for each of a plurality of blocks of the random access memory; For multiple blocks of a random access storage device, there is a mounting capacity setting switch that sets only a specific block to the mounted state, and a refresh timing signal is sent to the blocks that are not set to the mounted state by this mounting capacity setting switch. 1. A refresh cycle change circuit for a storage device, comprising: a refresh cycle changing circuit that performs control so as not to transmit data, thereby reducing an effective refresh time in accordance with a mounting state of blocks of the random access storage device.