JPH01211026A - Shift number for normalization deciding device - Google Patents

Abstract

PURPOSE:To shorten the time needed for operations by obtaining the shift number necessary for normalization for addition/subtraction of a floating point mantissa part from the higher two bits of a mantissa and the exponent difference obtained through the digit matching of the mantissa or from all other bits except the most significant bit. CONSTITUTION:A normalization control circuit 106 consists of a combination circuit supplies the outputs Ez and SM2 of an exponent computing element 102, the bits 2' and 2'' of the output of a mantissa computing element 104, and an addition/subtraction instruction signal 108 received from outside and mentioned later and outputs a normalized number of shifts designating signal and a selection signal SEL. With application of the circuit 106, the bit number needed for normalization of the output of the element 104 is calculated by a decoder 105 or based on the five bits including the higher two bits of the output of the element 104. Then the output of the decoder 105 is used only when the circuit 106 is unable to logically decide the bit number necessary for normalization. As a result, the overall time necessary for obtaining the number of shifts for normalization can be shortened on an average in case the addition/subtraction are carried out for the large number of floating points.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an apparatus for determining the number of shifts necessary for normalizing the results of addition and subtraction of floating point numbers.

BACKGROUND ART Addition and subtraction of floating point numbers whose mantissas are represented by sign and absolute value generally follow the following procedure.

Step 1: Digit alignment processing Step 2: Addition/subtraction processing Step 3: Mantissa part absolute value processing Step 4: Normalization processing Step 5: Rounding processing Here, in the normalization processing of step 4, l) the most significant bit of the mantissa part Calculation of the number of shifts required to make the value 1.2) Shifting of the mantissa part by the number of shifts determined.3) Correction of the exponent part by the number of shifts determined.

As a conventional processing device for realizing high-speed normalization processing, especially high-speed index correction, for example,
This is shown in Japanese Patent No. 6840.

FIG. 4 shows a block diagram of this conventional arithmetic processing device, where 1 and 2 are registers that hold human data, and 3 is a register that determines the magnitude of the exponent part of the human data and selects the larger exponent part. 4.5 is a register that holds the mantissa part of the output of the preshifter 3, 6 is a register that holds the exponent part of the output of the preshifter 3, 7 is a parallel adder, and 8 is a register that holds the exponent part of the output of the preshifter 3. A register 9 holds the output of the parallel adder 7, a decoder 9 counts the number of consecutive O's from the most significant bit in the contents of the register 8, 10
is a boss shifter that shifts the contents of register 8 by the number of bits indicated by decoder 9 and normalizes the mantissa; 11 to 26 are adders that add values from +1 to -14 to the output of register 6, respectively; 27 to 42 are adders 11 to 26
A register 43 that holds the output of the decoder 9 is a selector that selects one of the registers 27 to 42 according to the output of the decoder 9.

The operation of the conventional processing device configured as described above will be described next. The data stored in the register 1.2 is input to the pre-shifter 3, and first, the exponent parts are compared. Then, the larger exponent is stored in register 6, the mantissa part of the data with the larger exponent remains unchanged, and the mantissa part of the data with the smaller exponent part is shifted to the right by the exponent difference. .5. The output of register 4.5 is processed by parallel adder 7 and the result is stored in register 8. Further, in parallel with the calculation of the mantissa part, the contents of register 6 are added with +1 to -14 by adders 11 to 26, respectively, and stored in registers 27 to 42. Decoder 9 counts the number of consecutive 0s starting from the most significant bit of the contents of register 8. Then, based on the count result, the output of the register 8 is shifted by the boss shifter 10 to normalize the mantissa. Also, the exponent can be obtained by selecting one of the registers corresponding to the output of the decoder 9 with the selector 43, since the results calculated in advance for all output patterns of the kneader 9 exist in the registers 27 to 42. .

Problems to be Solved by the Invention However, although the above configuration can perform exponent correction at high speed, the circuit scale of the adders 11 to 26, registers 27 to 42, and selector 43 required to realize it becomes enormous. Another problem is that when the number of bits of the mantissa is increased in order to improve calculation accuracy, these resources increase significantly in proportion.

In view of these points, it is an object of the present invention to provide a normalization shift number determination device that can process normalization at high speed and realize it with a small circuit scale.

Means for Solving the Problem The number of shifts required to normalize the floating-point addition/subtraction results is determined by the addition/subtraction instruction signal given from the outside, the upper two bits of the added/subtracted mantissa, and information about the exponent difference obtained in the mantissa digit alignment process. The first method is to determine whether or not the number of shifts is determined, and the second method is to determine the number of shifts required to normalize the result of floating-point addition and subtraction from all other bits except the most significant bit of the added and subtracted mantissas. 2, and selection means for outputting either the shift number obtained by the first means or the shift number obtained by the second means according to the determination result of the first means. It is a decimal point calculation device.

According to the above-described configuration, the present invention calculates the number of bits required for normalizing the floating point mantissa addition/subtraction results by the first means when the number of bits is determined by the first means; If not, it is determined by the second method.

Embodiment FIG. 1 shows a block diagram of a normalized shift number determination device according to an embodiment of the present invention.

In FIG. 1, 100 is a register that holds a floating point number Nl expressed as N1=(-1)"-2"-fl.(1).

Here, el is the exponent, fl is the mantissa in absolute value representation, sl is the sign of the mantissa fl, and fl
has been normalized and satisfies l≦f1<2 (2).

101 is N2= (-1) 92・2°2・[2...
This is a register that holds the floating point number N2 expressed in (3). Here, e2 is an exponent, f2 is a mantissa expressed as an absolute value, S2 is a sign of the mantissa f2, and f2 is normalized, and satisfies l≦f2<2 (4).

102 is from index el in register 100 to register 10
1, and from the result, the index difference signal Ed
(= e t-e2), and the index difference is 0 (el=
e2), a signal SM2 indicating that the absolute value of the exponent difference signal Ed is 2 or more, an exponent operator that outputs the larger exponent et, and 103 is based on the output Ed of the exponent operator 102. If Ed≧0, the mantissa f in register 100
t remains as is, and the mantissa f2 in register 101 is moved to the right.
Bit shift and output, if Ed<0, register 101
The mantissa f2 in the register 100 is the mantissa fl
is a digit alignment circuit that shifts Ed bits to the right and outputs it, 1
04 is a mantissa calculator that performs addition and subtraction on the mantissa output from the digit adjustment circuit 103 and outputs its absolute value. 105 is a mantissa calculator that manually inputs all bits except 21 bits of the output of the mantissa calculator 104 and shifts required for normalization. Decoder that calculates numbers,
106 is composed of a combinational circuit, the output E2.5M2 of the exponent operator 102, and the output 21.211 of the mantissa operator 104.
bit, an addition/subtraction instruction signal 10 (described later) given from the outside.
A normalization control circuit 10 in which B is operated manually and outputs a normalization shift number designation signal and a selection signal SEL as shown in the table.
7 is the selection signal SEL which is the output of the normalization control circuit 106.
The output of the decoder 105, the normalization control circuit 1
108 is an addition/subtraction instruction signal that gives the operation mode to the mantissa calculator 104 and the normalization control circuit 106; 109 is the mantissa; a barrel shifter that normalizes and shifts the output of the arithmetic unit 104 using the output of the selector 107 and outputs a mantissa f as a final result;
Reference numeral 110 denotes an adder that corrects the exponent et selected by the exponent operator 102 using the output of the selector 107 and outputs an exponent e as the final result.

The operation of the floating point arithmetic processing device of this embodiment configured as described above will be explained.

First, the exponent operator 102 calculates the exponent e in the register 100.
Subtract the index e2 in the register 100 from l, et,
Outputs Ez, Ed, 5M2 signals. The digit alignment rEi circuit 103 adjusts the register 100 based on the signal Ed.
The digits of the mantissa fl in the register 101 and the mantissa f2 in the register 101 are aligned. The digit alignment result is input to the mantissa calculator 104, where addition or subtraction is performed as instructed by the calculation instruction signal 108, and its absolute value is output. The output of the mantissa calculator 104 needs to be normalized, but here the output of the mantissa calculator 104
Considering the output of , we get the following.

a) When performing addition in the mantissa calculator 104・el=e2
(Case 1) (Ez=1.Ed=0) Since there is no need to align the digits of the mantissas ft and f2, the mantissa after addition is as follows from equations (3) and (4): 2≦fl+f2<4... (
5). Dividing each side of equation (5) by 2, we get 1≦(f
l+f2)/2<2 (6) and is normalized. Here, division by 2 is realized by shifting one bit to the right.

・If el>el (Ez=0, Ed>O), the digit matching circuit 103 converts the mantissa f2 to the exponent difference el−e for digit matching.
Shift to the right by 2=n bits to obtain 1/m≦f2/m<2/m (7) (here, m=2'). Therefore, from equations (3) and (7), the mantissa after addition is 1< 1+1/m ≦ fl+f2/m< 2+2/
m < 3... (8). Therefore, when the addition result, f 1 + f 2/rn, is shown on a number line, it becomes as shown in FIG.

As is clear from Figure 2, if 21 bits = 1 (case 2), the addition result is 2 ≦ fl + f2/m < 2+2/m...
・It is within the range of (9). Then, dividing each side of equation (9) by 2, l≦(fl +f2/m)/2 < 1+1/m×2
...(lO) and is normalized. That is, normalization is performed by shifting the addition result by one bit to the right. Also, if 21 bit = 0 (
Case 3) The addition result is l ≦ 1+1/m S fl
+f2/m<2 (11), and no normalization process is required.

・In the case of el less el (Ez=0, Ed<0) el>el
From the same argument as in the case of , the mantissa f
Addition is performed by shifting l to the right by exponent difference el - e2 = n bits, and the addition result is 2I bits) = 1, the addition result is shifted to the right l bit (case 2). If 21 bit = 0, the addition result is not shifted (case 3
), normalization is performed.

b) When subtracting with the mantissa calculator 104 el=e2
(Case 4) (Ez=1.Ed=0) Mantissa f1. Since there is no need to align the digits of f2, the mantissa after subtraction is -1<fl-f2< from equations (3) and (4).
1...(12) or -1<f2-fl<1.-(13). Therefore, in order to normalize the subtraction result, it is necessary to shift the subtraction result to the right by one or more bits.

``If el>22 (Ez=O, Ed>O), in order to align the digits as in the case of addition, the mantissa f2 is converted to the exponent difference el-e2
= After shifting to the right by n bits, subtraction of fl-f2/m (here m=2) is performed. Therefore, the mantissa after subtraction from equations (3) and (7) is 0 ≦ 1-2/m < fl -f2/m<2-1
/m<2 (14). When equation (14) is shown on a number line, it becomes as shown in FIG. As is clear from Fig. 3, if 28 bits = 1 (case 5), the subtraction result is l ≦ f 1- f2/m < 2-1 /m
2 (15), and no normalization process is required. Also, if 2 bits = 0, the subtraction result is 0 ≦ 1-2/m < f 1- f 2/rn
< 1 (16) Therefore, for normalization, it is necessary to perform a left shift of one or more bits. However, since m = 2', n = 1.2.3, -(17), in the case of n = 1 (case 6), the lower limit of the subtraction result is 1 -
2/m is 1-2/2 = 0...(
18), and it is necessary to perform a multiple-bit right shift for normalization, but if n≧2 (case 7), the lower limit of the subtraction result, 1-2/rn, is 1-2/4≦1. -2/m
< 1- (19). In other words, when each side of equation (19) is multiplied by 2, l ≦ 2 (1-2/m) < 2 - (20), so in this case, normalize the subtraction result by shifting 1 bit to the left. It turns out that it can be done.

Fist case 1: When el<e2 (Ez=1, Ed<el
> From the same argument as in the case of e2, we can use the mantissa fl as the exponent difference el
-e2=N bits shifted to the right and subtracted, and if the subtraction result is 281 bits = 1, the addition result is not shifted (Case 5) If 211 bits = O and n = 1, multiple bits are shifted to the left (Case 6) n If ≧2, normalization is performed by performing a 1-bit shift to the left (case 7).

Based on the above discussion, the normalization control circuit 10B is configured with a combinational circuit that satisfies the human output relationship in the table.

The case numbers in the table refer to the case numbers shown in parentheses in the above explanation. That is, except for case 4.6, the SEL signal is 1, and the number of shifts necessary for normalization is directly given from the normalization control circuit 10G via the selector 107. In case 4.6, the SEL signal becomes 0 and the number of shifts necessary for normalization is given from the decoder 107 via the selector 107. Then, the output of the mantissa operator 104 is normalized by the barrel shifter 109 according to the output of the selector 107, and the output et of the exponent operator 102 is normalized by the adder 110.
The final mantissa f and finger Wke are respectively obtained. Further, since the decoder 105 does not need to calculate the right shift number but only the left shift number, there is no need to input the bit having a weight of 2' out of the output of the mantissa calculator 104.

Further, the time required to obtain the number of shifts required for normalization is longer in case 4.6 than in other cases.

This is because in case 4.6, all outputs of the mantissa calculator 104 except for the bits with a weight of 21 must be decoded by the decoder 105, but in case 1, case 2 This is because in .3.5.7, after addition and subtraction are completed in the mantissa calculator 104, the number of shifts required for normalization can be determined by decoding the 5-bit input in the normalization control circuit 106. However, when performing a large number of floating point additions and subtractions, these processing times are averaged over the cases that occur, and are faster than the conventional method that always uses a decoder. In particular, even if the number of bits of the mantissa is increased to improve calculation accuracy, the number of manual bits of the normalization control circuit 106 does not change, so the time required to obtain the number of shifts required for normalization is shorter than that of the conventional case. This embodiment is much shorter than the method described above. Therefore, even if the adder 110 performs the index correction after calculating the number of shifts required for normalization as in this embodiment, the correction can be made in the same or shorter time than in the conventional example, and the necessary Hardware resources can also be significantly reduced compared to conventional examples. Further, since the decoder 105 only needs to output the left shift number, there is an advantage that the decoder 105 does not need to output a signal indicating whether it is a left shift or a right shift, and the decoder 105 becomes simpler.

As described above, according to the present invention, by providing the normalization control circuit 106, the number of bits necessary for normalizing the output of the mantissa calculator 104 is calculated by the decoder 105;
The normalization control circuit 10 performs processing in two ways: one uses 5 bits including the upper 2 bits of the output of the mantissa arithmetic unit 104.
6, the output of the decoder 105 is used only when the number of bits required for normalization cannot be determined logically. Therefore,
On average, when performing a large number of floating point additions and subtractions,
The time required to obtain the normalization shift number is reduced.

As described in detail, according to the present invention, the number of shifts necessary for normalizing the mantissa addition/subtraction results is determined by the exponent size determination result obtained in the digit alignment process, the determination result of whether the exponent difference is 2 or more, and the mantissa. A first means for determining whether or not the upper two bits of the result of adding/subtracting the mantissa parts can be determined logically from the addition/subtraction instruction signal given from the outside, and outputting the determined result if the result is determined; The number of shifts for normalization can be determined by providing a second means for determining the number of shifts for normalization from all other bits except for the bit, and using the output of the second means only when the number of shifts cannot be determined by the first means. The time required for the calculation can be reduced on average. Moreover, the first means can be realized with a simple dark-blue matching circuit, and its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a device for determining the number of normalized shifts in an embodiment of the present invention, FIG. 2 is a number line diagram showing the range of addition results, and FIG. 3 is a number line diagram showing the range of subtraction results. FIG. 4 shows a block diagram of a conventional processing device. 100.101...Register, 102...Exponent operator, 103...Digit alignment circuit,
104... Mantissa calculator, 105... Decoder, 10
6... Normalization control circuit, 107... Selector, 108... Addition/subtraction instruction signal,
109... Barrel shifter, 110... Adder. Name of agent Patent attorney Toshio Nakao 1 person Figure 1 Figure 2 7+ '/m 2+ 27m Figure 3 0 / 2 /-2/rn 2- '/m

Claims (1)

[Claims] Based on the addition/subtraction instruction signal given from the outside, the upper 2 bits of the added/subtracted mantissa, and the information about the exponent difference obtained in the mantissa digit alignment process, it is determined whether or not the number of shifts required to normalize the floating point addition/subtraction results can be determined. a first means for calculating the number of shifts in the case of the case; a second means for calculating the number of shifts necessary for normalizing the floating point addition/subtraction result from all other bits except the most significant bit of the added and subtracted mantissa; and a selection means for outputting either the shift number obtained by the first means or the shift number obtained by the second means, depending on the determination result of the first means. Shift number determining device.